PD- 91651C

FB180SA10
HEXFET Power MOSFET
l l l l l l l l

Fully Isolated Package Easy to Use and Parallel Very Low On-Resistance Dynamic dv/dt Rating Fully Avalanche Rated Simple Drive Requirements Low Drain to Case Capacitance Low Internal Inductance

VDSS = 100V RDS(on) = 0.0065W

ID = 180A
S

Description
Fifth Generation, high current density HEXFETS are paralled into a compact, high power module providing the best combination of switching, ruggedized design, very low ON resistance and cost effectiveness. The isolated SOT-227 package is preferred for all commercial - industrial applications at power dissipation levels to approximately 500 watts. The low thermal resistance and easy connection to the SOT227 package contribute to its universal acceptance throughout the industry.

S O T -22 7

Absolute Maximum Ratings

Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG VISO Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Insulation Withstand Voltage (AC-RMS) Mounting torque, M4 srew

Max.
180 120 720 480 2.7 20 700 180 48 5.7 -55 to + 150 2.5 1.3

Units
A W W/C V mJ A mJ V/ns C kV Nm

Thermal Resistance
Parameter
RqJC RqCS Junction-to-Case Case-to-Sink, Flat, Greased Surface

Typ.
0.05

Max.
0.26

Units
C/W

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2/1/99

FB180SA10
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage DV(BR)DSS/DTJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance V(BR)DSS IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ls Ciss Coss Crss Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 100 2.0 93 Typ. Max. Units Conditions V VGS = 0V, ID = 250A 0.093 V/C Reference to 25C, ID = 1mA 0.0065 W VGS = 10V, ID = 108A 4.0 V VDS = VGS, ID = 250A S VDS = 25V, ID = 108A 50 VDS = 100V, VGS = 0V A 500 VDS = 80V, VGS = 0V, TJ = 125C 200 VGS = 20V nA -200 VGS = -20V 250 380 ID = 180A 40 60 nC VDS = 80V 110 165 VGS = 10.0V, See Fig. 6 and 13 45 VDD = 50V 351 ID = 180A ns 181 RG = 2.0W (Internal) 335 RD = 0.27W See Fig. 10 , 5.0 nH Between lead, and center of die contact 10700 VGS = 0V 2800 pF VDS = 25V 1300 = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics

IS
ISM

V SD t rr Qrr ton

Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time

Min. Typ. Max. Units

Conditions MOSFET symbol 180 showing the A integral reverse 720 p-n junction diode. 1.3 V TJ = 25C, IS = 180A, VGS = 0V 300 450 ns TJ = 25C, IF = 180A 2.6 3.9 C di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:

Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

I 180A, di/dt 83A/s, VDD V(BR)DSS, SD

TJ 150C

Starting TJ = 25C, L =43H

RG = 25W , IAS = 180A. (See Figure 12)

Pulse width 300s; duty cycle 2%.

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FB180SA10
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP

1000

I D , Drain-to-Source Current (A)

100

I D , Drain-to-Source Current (A)

VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP

100

4.5V

4.5V
10

10

1 0.1

20s PULSE WIDTH TJ = 25 C

1 10 100

1 0.1

20s PULSE WIDTH TJ = 150 C

1 10 100

VDS , Drain-to-Source Voltage (V)

VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

2.5

TJ = 150 C

R DS(on) , Drain-to-Source On Resistance (Normalized)

ID = 180A

I D , Drain-to-Source Current (A)

2.0

100

1.5

TJ = 25 C

1.0

10

0.5

1 4 5 6 7

V DS = 25V 20s PULSE WIDTH 8 9 10

0.0 -60 -40 -20

VGS = 10V
0 20 40 60 80 100 120 140 160

VGS , Gate-to-Source Voltage (V)

TJ , Junction Temperature( C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance Vs. Temperature

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FB180SA10
20000

C, Capacitance (pF)

15000

VGS , Gate-to-Source Voltage (V)

VGS = Ciss = Crss = Coss =

0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd

20

ID = 180 A VDS = 80V VDS = 50V VDS = 20V

15

Ciss
10000

10

Coss
5000

Crss

0 1 10 100

0 0 50 100 150 200

FOR TEST CIRCUIT SEE FIGURE 13

250 300 350 400

VDS , Drain-to-Source Voltage (V)

Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage

Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage

1000

10000

ISD , Reverse Drain Current (A)

OPERATION IN THIS AREA LIMITED BY RDS(on) TJ = 150 C

1000 10us

I D , Drain Current (A)

100

10

100

100us 1ms

TJ = 25 C
1

10

10ms

0.1 0.2

V GS = 0 V
0.6 1.0 1.4 1.8

1 1

TC = 25 C TJ = 150 C Single Pulse

10 100 1000

VSD ,Source-to-Drain Voltage (V)

VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

Fig 8. Maximum Safe Operating Area

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FB180SA10
200 175

VDS VGS RG

RD

D.U.T.
+

I D , Drain Current (A)

150 125 100 75

-VDD

10V
Pulse Width 1 s Duty Factor 0.1 %

Fig 10a. Switching Time Test Circuit

50

VDS
25 0 25 50 75 100 125 150

90%

TC , Case Temperature ( C)
10% VGS

Fig 9. Maximum Drain Current Vs. Case Temperature

td(on)

tr

t d(off)

tf

Fig 10b. Switching Time Waveforms

Thermal Response (Z thJC )

D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1

0.01

0.001 0.00001

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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FB180SA10
EAS , Single Pulse Avalanche Energy (mJ)
1500

1 5V

1200

ID 71A 100A BOTTOM 160A TOP

VD S

D R IVE R

900

RG
20V

D .U .T
IA S tp

+ V - DD

600

0 .0 1

Fig 12a. Unclamped Inductive Test Circuit

300

0 25 50 75 100 125 150

V (B R )D S S tp

Starting T , Junction Temperature( C) J

Fig 12c. Maximum Avalanche Energy Vs. Drain Current

IAS

Fig 12b. Unclamped Inductive Waveforms

Current Regulator Same Type as D.U.T.

50K

QG

12V

.2F .3F

10 V
QGS VG QGD
VGS
3mA

D.U.T.

+ V - DS

Charge

IG

ID

Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform

Fig 13b. Gate Charge Test Circuit

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FB180SA10
Peak Diode Recovery dv/dt Test Circuit
D.U.T

Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer

RG dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test

+ VDD

Driver Gate Drive P.W. Period D=

P.W. Period VGS=10V

D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt

VDD

Re-Applied Voltage Inductor Curent

Body Diode

Forward Drop

Ripple 5%

ISD

* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS

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FB180SA10
SOT-227 Package Details
4 .40 (.1 73 ) 4 .20 (.1 65 ) 4 38.3 0 ( 1.5 08 ) 37.8 0 ( 1.4 88 ) -A 3 6 .25 ( .246 ) 12.5 0 ( .49 2 ) 25 .7 0 ( 1 .012 ) 25 .2 0 ( .9 92 ) -B 1 7 .50 ( .295 ) 3 0.2 0 ( 1.18 9 ) 2 9.8 0 ( 1.17 3 ) 4X 2.1 0 ( .082 ) 1.9 0 ( .075 ) 8.10 ( .319 ) 7.70 ( .303 ) 0.25 ( .010 ) M C A M B M 2.10 ( .08 2 ) 1.90 ( .07 5 ) -C0.12 ( .005 ) 12.30 ( .4 84 ) 11.80 ( .4 64 ) 2 R FU L L 15.00 ( .590 ) 4 1 K1 A2 H E X FR E D G E IG B T A1 K2 3 2 C H AM FE R 2 .00 ( .0 79 ) X 4 5 7 LE A D A S S IG M E NT S E C 4 1 G S H E XFET S D 3 2

Tube
Q UANTITY PE R TUBE IS 1 0 M4 SR EW AND W ASHE R IN CLU DED

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