Magnetic Random Access Memories (M-RAM) : A truly universal memory?

J. P. Nozires

SPINTEC (Spintronique et Technologie des Composants), URACEA/CNRS n 2512, DRFMC

Abstract Magnetic Random Access Memories (MRAM) are being developed as a potential

replacement for semiconductor-based memories. SPINTEC and LETI are jointly developing state-of-the art architectures and advanced designs with reduced power consumption and addressing errors.

I. Introduction

Recent developments in the physics of spin electronics (see Inset) have enabled the emergence of a new class of non-volatile memories, Magnetic Random Access Memories (MRAM). MRAM combine on paper all the virtues of current silicon-based memories: speed, density, non-volatility, low power consumption, radiation hardness and endurance (see Table 1). The first target for MRAM is replacement of Flash memories, such as those used in cell phones, digital cameras, smart cards etc, which, despite being non-volatile, have a high power consumption, are sluggish at write and are prone to aging effects. In a longer run, MRAM may well become a universal memory which would also be substituted for Static RAM (SRAM) and Dynamic RAM (DRAM). Major Integrated Circuit manufacturers have started extensive research and development efforts and expect to launch the first product by the end of the year. In this article, we describe the MRAM activity carried out in our laboratories on state-of-the art and advanced designs in collaboration with several key players in the field.

II. The basic MRAM cell: The Magnetic Tunnel Junction

In MRAM, the information is no longer stored by electrical charges, as in semiconductor memories, but by two opposite directions of the magnetization vector in a small magnetic nanostructure. The basic MRAM cell [1] is the so-called Magnetic Tunnel Junction (MTJ) which consists of two magnetic layers sandwiching a thin (sub-nm) insulating layer (see Fig. 1). The magnetization of one of the layers, acting as a reference layer, is fixed and kept rigid in one given direction. The other layer, acting as the storage layer, can be switched under an applied magnetic field from parallel to antiparallel to the reference layer, therein inducing a change in the cell resistance of approximately 50%. The corresponding logic state ("0" or "1") of the memory is hence defined by its resistance state (low or high), monitored by a small read current.

Of course, the structure of a true MTJ device is far more complex than just a magnetic/insulator/magnetic tri-layer. Complex stacks of more than ten layers of various materials, with thickness in the nanometer range, compose todays MTJ. The most critical part of fabrication is the tunnel barrier, whose thickness must lie in the 0.5-1 nm range with required uniformities below 0.1 nm over an 8 inch wafer.

Nevertheless, the nature of magnetism is such that as long as thermal stability is achieved, MRAM are inherently fast (magnetization switches in nanoseconds or less), nonvolatile, radiation hard and aging-insensitive.

III. The first generation : Field-Induced Magnetic Switching (FIMS)

A fully functional MRAM memory is based on a 2D array of individual cells, which can be addressed individually. In todays architecture, each memory cell combines a CMOS selection transistor with a magnetic tunnel junction and three line levels (see Fig. 2). (i) At read, a low power current pulse in the lower line level ('control line') opens the transistor to address the selected memory cell. The cell resistance is measured by driving a current from the 'word line' through the MTJ (see Fig. 2a) and comparing to a reference cell located somewhere in the array. (ii) At write, the word lines and bit lines, arranged in a crosspoint architecture on each side of the MTJ, are energized by synchronized current pulses in order to generate a magnetic field on the addressed memory cell (see Fig. 2b). The intensities

of the current pulses are chosen such that only the storage layer at the cross-point of the two lines (the so-called fully selected cell) can be switched, all other cells on any given line or any given column (the so-called half selected cells) being unable to switch. This is possible thanks to a characteristic property of magnetic nanostructures, known as the Stoner-Wolhfarth astroid [2], wherein the switching field is reduced when the magnetic field is applied at an angle with respect to the particle magnetization, as is the case for fully selected cells.

This technology is being used efficiently in the first generation of MRAM devices, as well as in SPINTECs first demonstrators. As shown in Fig. 3, the Stoner-Wohlfarth astroid is measured as a function of the word and bit line current pulses. To prevent selection errors, the current has to be large enough to ensure switching of all selected cells, but low enough to prevent switching of half-selected cells. This defines the write window, which is primarily determined by the switching field distribution in the array.

Albeit functional, the FIMS architecture may reach its limits when the cell size is reduced below 0.1 m; (i) the write power will increase, due to the switching field being inversely proportional to particle size; (ii) the selection errors at write will increase, as the switching field distribution is expected to skyrocket for these dimensions; (iii) the long-term stability of the data will be jeopardized, due to the increasing impact of thermal activation.

IV. Going one step further : Thermally Assisted Switching (TAS)

Achieving sub-0.1m cell size with minimal power consumption is the key challenge for MRAM to break into the big league. One of the techniques developed at SPINTEC is based on thermally assisting switching (TAS) during the write procedure. This simple approach relies on the strong temperature dependence of the magnetic switching field which is encountered in magnetic nanoparticles (the smaller the particle, the steeper this Tdependence). In the TAS mode, the selection transistor is opened at write and a short current pulse is sent through the MTJ simultaneously with the write field current pulses in the word and bit lines (see Fig. 2c). The heat generated in the tunnel barrier (which acts as a resistor) by the current burst is quickly thermalized in the adjacent metallic layers of the MTJ. The resulting decrease of switching field in the storage layer makes it possible to write at reduced current.

There are multiple advantages to this approach: (i) as the selection at write is now mostly temperature-driven, addressing errors are minimized; (ii) despite the onset of an additional heating current, the overall write power can be greatly reduced compared to FIMS and is mostly independent of the cell dimension; (iii) parallel (simultaneous) addressing of cells is now possible with no risk of errors, resulting in an increased speed; (iv) the thermal instability limit can be pushed further back by using materials with larger switching fields at operating temperature. The viability of the TAS concept has just been demonstrated at SPINTEC on test structures with a ten-fold decrease in power consumption. TAS is thus expected to prove a viable alternative for sub 0.1 m cell size, with little or no impact on the memory architecture.

V. The Holy Graal : Spin Polarized Current Induced Switching (CIS)

The recent discovery in ohmic metallic nanostructures of direct magnetic switching by an electrical current (e.g. no magnetic field) [3], opens up the way for a new class of magnetic memories which would be similar in principle to current-driven semiconductor devices. In this case, writing would simply consist in opening the selection transistor and sending a high density current through the junction, just like Flash memories (see Fig. 2d).

A simplified picture of CIS is the following. When a current flows through a magnetic material, it becomes spin polarized, e.g. there is an imbalance between the number of up and down spins carrying the current. When this current hits another magnetic layer, this spin imbalance generates some kind of a torque on the local magnetization, which torque can be large enough to induce a complete reversal of the magnetization. The benefits of such an architecture are enormous: (i) no more addressing errors, as only the selected memory cell is subject to the write current ; (ii) doubling the memory density by eliminating one of the write lines, hence enabling the memory cell and transistor to be stacked, just like in a DRAM ; (iii) the potential for highly parallel addressing, resulting in ultra-fast memories ; (iv) the potential for ultra-small cell size as the thermal stability limit materials requirements are now independent of the current induced switching parameters.

Theoretically, CIS may operate well beyond the 0.1 m cell size. However, the major hurdle that needs to be overcome before the onset of CIS-driven MRAM lies in the large current density which is still required today to induce switching, not only to minimize the power consumption, but also to prevent electrical breakdown of the MTJ. Different routes are currently being addressed at SPINTEC in collaboration with INESC (Portugal).

VI. Conclusion

Recent developments show that MRAM fulfil their promises, in particular in terms of speed and power consumption. Spintecs first demo chip, based on field-induced magnetic switching in a cross-point architecture with 0.2 x 0.4 m_ cell sizes, is expected by the end of the year with the help of ST Microelectronics.. The research effort now has to be focused on the next generations of MRAM, in order to break through the 0.1 x 0.1 m_ cell size limit. Thermally-Assisted Switching and Current-Induced Switching as developed at SPINTEC are two likely routes and the first results obtained are very promising. Demo chips with ATMEL and Cypress Semiconductors should follow.

Acknowledgements O. Redon, B. Dieny, R. Sousa, L. Prejbeanu, B. Rodmacq, S. Auffret, G. Casali, S. Monso, Y. Conraux, A. Deac, and S. Muller of the MRAM team (SPINTEC), P. Gaud, H. Sibuet, F. Ponthenier, F. Allain, A.Toffoli, and J. Cluzel (LETI/DTS), and P. Freitas, Y. Liu, and Z. Zhang (INESC).

[1] M. Jullire, Phys. Lett. A 54, 225 (1975).

[2] E. C. Stoner and E. P. Wohlfarth, Philos. Trans. London A 240, 599 (1948).

[3] F. J. Albert, J. A. Katine, R. A. Burham, and D. C. Ralph, Appl. Phys. Lett.77, 3809 (2000).

Inset Spin electronics

In addition to an electrical charge, electrons carry an individual angular momentum whose origin lies in the electron spinning on itself. This local magnetic moment, named spin moment, is quantized and can take only two values +1/2 (up) and 1/2 (down). In a standard electrical circuit, spin states are equally-populated. In contrast, in ferromagnetic materials, the density of states are different for the two spin configurations (e.g. parallel or antiparallel to the local magnetization), which leads to a net spin polarization of the current. Spin electronics is a new field the aim of which is to take advantage of the additional degree of freedom of current carriers (charge and spin) in order to generate new functionalities. The first practical application of spin electronics can be found in todays (data) read heads in hard disk drives where the so-called giant magnetoresistance is used. MRAM may well be the next product on the near horizon. In the longer run, new devices such as spin transistors, spinLED, spin switch, etc which are already developed at laboratory scale, will eventually emerge as new spin electronics devices.

Write speed Read speed Density Endurability Power Refresh Retention Scalability Write/Erase

DRAM Moderate Moderate High Good High Yes No Bad

Charge (Capacitance)

SRAM Fast Fast Low Good Low No No Good

CMOS Logic

FLASH Slow Fast High Poor Low No Yes Good

Charge (Tunneling)

FeRAM Moderate Moderate Medium Poor Low No Partially Medium

Ferroelectric

OUM Moderate Fast High Good Low No Yes Good

Phase transition

MRAM Fast Fast High Good Low No Yes Good

Magnetization

Table 1: Figure of merit of the various kinds of Random Access Memories : Dynamic (DRAM), Static (SRAM), and Flash are based on semiconductor while Ferroelectric (FeRAM), (PCRAM) and MRAM) are

R/R (%) 20 15 10 5 0

Phase-Change Magnetic( new concepts.

"1 "

"0 "

Figure 1: Magneto-Conductance of a Magnetic Tunnel Junction. In red, the reference layer (rigid). In blue, the storage layer (it switches under external field). The 0 and 1 logic states correspond to a parallel and antiparallel alignment of the reference and storage layers.

(a) Read
current Bit line Word line Control line
Transistor ON

(b) Write - FIMS

Magnetic field current Bit line Word line Transistor OFF

Control line

(c) Write - TAS

current

(d) Write - CIS

Magnetic field current Bit line Bit line

Control line

Word line Transistor ON Control line

Transistor ON

Figure 2: Read and write principles of MRAM with various architectures: (a) Read (common principle); (b) Write in FIMS (Field Induced Switching) mode; (c) Write in Thermally Assisted Switching (TAS) mode; (d) Write in Current Induced Switching (CIS) mode)

Courbe d'astrode pour un point mmoire de 5.7*2m?

Courant axe difficile (A)

0,02 0,015 0,01 0,005 0 -0,005 0 0,01 0,02 0,03 0,04 0,05 0,06 0,07 Courant axe facile (A)

Ecriture possible

Ecriture impossible

Figure 3: Stoner-Wohlfarth astroid measured on MTJ test structures of dimensions 5.7x2 m_ with the cross-point FIMS architecture. Each dot corresponds to an ( Ibit line, Iword line) value enabling switching of the storage layer.

Figure 4: MTJ test structures developed at SPINTEC: (a) full view of the die area with 1x5 MTJ cross-point arrays, isolated cross-point MTJ for dynamic (sub-ns) read/write (bottom left) and in-line MTJ test structures (bottom right); (b) zoom of the cross-point arrays for msize MTJ; (c) 0.2 m width isolated MTJ element after etch.