Forthcoming CMOS Technology in Nanoscale Era

Shashank Mishra#1, Kshitij Bhargava#2, Rohit Tripathi#3 , Piyush Jain#4

Electronics and Communication Engineering (Microelectronics and Embedded Technology) Department
Jaypee Institute of Information Technology, Noida-201307, U.P., India
1
shashankmishra05EI44@gmail.com
2
kbhargava3@gmail.com
3
rohit.tri2008@gmail.com
4
piyush.oct@rediffmail.com

Abstract— CMOS technology has reached to the level of sub- believed that the CMOS device downsizing will approach the
45nm range. It is expected that the nano-CMOS technology will physical limit.
govern the IC manufacturing at least for another couple of
decades. Though there are many challenges ahead, further down-
sizing the device to a few nanometers is still on the schedule of
International Technology Roadmap for Semiconductors (ITRS).
Several technological options for manufacturing nano-CMOS
microchips has been available or will be available very soon. This
paper reviews the challenges of nano-CMOS downsizing and will
focus on the recent developments on the key technologies for the
nano-CMOS in the years to come.

I. INTRODUCTION
Among numerous great inventions made in the 20th
century, electronics is the most important one. Almost every
thing related to human activities, such as power generation,
transportation, entertainment, medical care, is now provided
and controlled by electronics. Semiconductor is strategically
an important technological area for all nations. The electronic
circuit development has been accomplished with the
downscaling of component size since the replacement of
vacuum tubes with transistors 40 years ago. The circuit
characteristics have benefited a lot from the downsizing. We
are now able to integrate millions of CMOS transistors at the
nanoscale level on the silicon chip with only few centimetres
square of area occupied. Right now the operating speed of the
recently developed microprocessor has already reached upto 5
GHz and is expected to increase further. Although recent
trends indicate that the increase in the clock frequency may
gradually get saturated. The CMOS integrated circuits as well
as their core device technology are expected to evolve further
for at least a couple of decades and their importance will be
further increased in future intelligent systems. CMOS device
dimensions have been reduced to a millionth at the production
level in the past 100 years. Hundred years ago, no one could
have ever imagined that the mankind of our time will be able
to make any such electronic components which will consist of
billions of electronic components with dimension smaller than
the bacteria size and those circuits will fulfil the different
needs of the society. Future scaling trends have been predicted
by the International Technology Roadmap for Semiconductors
(ITRS) for 30 years up to 2040, when the physical gate length
is expected to be 1 nm (as shown in figure 1), [2]. It is
Figure 1: Feature size versus time in silicon ICs.
II. CHALLENGES IN SCALING
Device downsizing from 10 µm to the sub-45-nm range
presented a lot of benefits in terms of speed, power, and cost.
But apart from the improvements, reported above, one of the
major problems for performance degradation in the ultra-large
scale circuits is the interconnect delay due to the increase in
the resistance and the capacitance values of narrow and dense
interconnection metal lines (parasitic). Furthermore, the
performance improvement is also questionable for the ultra-
small MOSFET itself. According to the scaling theory, the
drain current per unit gate width should remain constant.
However, a significant reduction of the drain current value per
unit gate width for sub-45nm gate length MOSFETs was
reported recently (as in Fig. 2), [2]. This phenomenon is due
to the non-optimized MOSFET structure and process. On the
other hand, the small drain current (of several tens of micro-
Ampere per micrometer) at the scaled supply voltage becomes
a major concern. Besides, the fringing capacitance of the gate
electrode, and the inversion layer capacitance will also
degrade the performance of the ultra-small MOSFETs (as in
Fig.3), [2]. It is still doubtful at this moment that such a small
MOSFET can be used for high-speed devices. Hence, without
any new technology support, further downscaling may only
result in performance degradation.
Figure 2: Significant reductions of the unit drain currents
Figure 3: Challenging issues further downsizing of MOS transistor
III. IMPROVEMENTS IN CMOS
There have been proposals to try and change the structure
of the transistor itself. Here we are discussing the two most
prominent structural changes: Silicon on Insulator (SOI) and
Double Gate CMOS (DGCMOS). The basic concept of
Silicon on Insulator is fairly simple. Rather than fabricating a
transistor whose body is connected to the substrate (Fig. 4.a),
which is the normal method, an insulating oxide is first
deposited on the substrate and then the transistor is fabricated
on top of that (Fig. 4.b). By doing this the body can be made
electrically isolated from its surroundings. This means that the
bulk to source voltage Vbs is now floating. This design
provides a number of performance benefits. Vbs is now greater
than or equal to zero, which lowers the threshold voltage, Vt,
providing a performance increase. Also, there is no junction
area capacitance. Finally, stacked circuits do not suffer from
the reverse body effect. The new structure also lends itself to
some new uses, such as using the insulating layer for a high
resistance element.
Figure 4.a: Bulk CMOS Gate
Figure 4.b: SOI Gate
There are of course some disadvantages associated with the
new structure as well. While the floating Vbs provides many
benefits, its variability can also become problematic. The
value of Vbs is a function of the present current level in the
gate as well as the history of previous states which the gate
has been in. This means that the threshold of a gate may vary
significantly throughout its operation. Also, if Vbs climbs too
high it can cause pass-gate leakage. There have been
techniques developed to address some of these issues. To test
this technology, IBM redesigned some of their PowerPC line
chips using SOI. They were able to demonstrate a 22-33%
performance increase over the bulk CMOS version of these
chips. They also found that, while implementing SOI
structures it requires a proper understanding of the unique
problems that this technology gets associated with, it was
possible to redesign existing technologies in a reasonable
amount of time. The second structure is more experimental,
but promises great benefits in the future. That structure is the
Double-Gate CMOS (DGCMOS). The basic idea of this
structure is to add an extra gate (or more) to increase coupling
between the gate and the channel. Some have called this the
“ideal structure for scalability”. Most of the people agree that
it is the design of the future, but there are some difficulties to
overcome before them. The difficulties arise in how to
implement the DGCMOS structure. Using traditional
fabrication processes a second gate could be added below the
body. However, the alignment issues of such a gate are
troublesome. The proposed solution is known as the FinFET.
This structure builds the drain, source, and gate up vertically.
(as in Fig. 5).

Figure 5: FinFET structure
This may solve the alignment issue, but there is one other
challenge to overcome. In order to control SCE, the body
thickness must be ¼ of the gate length. This is a daunting
challenge because the gate length is usually the smallest
dimension that can be fabricated. There are some technologies
that may address this, but more work needs to be done in this
area.
The most popular idea is to use carbon nanotubes (CNTs) as
transistors (a configuration example is shown in Fig. 6). This
concept is very appealing because it is still a transistor and
could make use of all the architectural knowledge developed
for CMOS. Carbon nanotubes however do have a long way to
go before they can start replacing the silicon based MOS
transistors. First of all, nanotube transistors developed till date
has shown very poor performance characteristics. Many of the
problems they are exhibiting are similar to the challenges
CMOS is currently facing, such as high off-state leakage and
source-to-drain tunneling. Also, despite the hopes for
chemical self assembly some day, it is still very difficult to
produce nanotube transistors.
Figure 6: Basic carbon nanotube transistor
IV. CONCLUSIONS
Silicon MOSFETs have been the smallest electronic device
for several decades. The gate length used for high
performance logic unit is 45 nm in production and 5 nm in
research. Note that the 5-nm gate length is the distance of 18
atoms and 0.8-nm oxide thickness is two atomic layers only.
Si technology is no doubt the most successful nano-devices.
We do not see that there is any realistic replacement for
silicon devices. Even the Si devices reach the downsizing
limit no matter 10 nm, 5 nm, or 1 nm, other emerging devices
such as molecular transistors will also reach their limit of
downsizing in similar dimensions. It is a critical period for
moving from 45-nm to 10-nm technology within this decade.
Most of the materials and the manufacturing processes used in
the deep-submicron era are now pushing to their physical
limits. New materials and technologies are required for further
down-scaling the device to 10-nm technology and below.
Immersion lithography for ultra fine patterning, strained
channels, nickel salicide, high-k gate dielectric, low-k
interlayer for interconnect, plasma doping, flash and laser
annealing for source and drain doping, elevated source and
drain and three-dimensional MOSFETs for controlling short-
channel effects, would help to overcome the materials and
technological constraints and improve the device performance
in the ultra-small scale. The final remark is a non-technical
issue. We anticipate that this issue will be one of the most
important issues for nano-CMOS technology development in
the next 15 years. We are aware that most of the new mega-
fabs being planned or under construction are in the East and
Southeast Asia, and particularly the Mainland China. In 10 or
15-year’s time, the distribution of semiconductor
manufacturing sites in Asia (including Japan) will be quite
substantial. Currently, Korea and Taiwan are in the first place
for semiconductor memory manufacturing and semiconductor
foundry, respectively. They also lead the technology
development in Asia region. Mainland China seems to be
another super power for semiconductor manufacturing. The
share of China semiconductor manufacturing will keep fast
growing with the support of booming IC design houses,
constructing new fabs with remarkable increase in industrial
investment, and will be the most important huge and rapidly
expending market. As many other industries and other sectors
of electronic products, Mainland China will eventually
become “the factory of the world” in semiconductor
manufacturing in 15 years or longer and will have great
impact on the future nano-CMOS technology.
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