Digital design Issues in Deep and Very Deep

Submicron Era
Rohit Tripathi, Nikita Gupta, Kshitij Bhargava
M.Tech. Microelectronics and Embedded Technology,
Jaypee Institute of Information Technology, Noida
1
rohit.tri2008@gmail.com
2
nikitagupta.1986@gmail.com
3
kbharagava3@gmailcom

The much-debated Moore’s law is expected to
hold for another decade, and we have already
seen the commercialization of 22 nanometer and
18 nanometer technologies. Designing chips in
these nanometer technologies has proven to be a
challenge. Since the cost of manufacturing in
these technologies is so high, only major
semiconductor vendors appear to be geared to
face the technological challenge. The smaller
players in the field are looking for alternate
solutions such as reconfigurable computing
platforms. To push the technological limits and
yet be economically viable, it is important to get
the chips “right-the-first-time.” This article
explores the challenges of semiconductor design
technology that occupy today’s design engineers
and will continue to do so for some years to
come.
Ever since Jack Kilby made the first integrated
circuit (IC) in 1958, nothing has remained the
same except for the incredible rate at which the
IC is shrinking in size. Today’s engineers are
designing IC’s targeted for manufacture with 22
nm and 18 nm technologies. Work is already
ongoing on the 14 nm node. There were
prophecies about the end of the scaling at the turn
of the century when it was believed that the
wavelength of light was a limit on the feature
size. Yet, the deep submicron and the very deep
submicron technology are now realities. As a
consequence, it is now possible to build circuits
which are less than one square centimeter in
surface area and have more than 100 million
transistors on them. With such huge capacity, the
IC’s that we design today are not component
chips but systems-on-chip (SoC) where the
complete functionality of a system is packed into
a small piece of silicon.
While the raw power of semiconductor
manufacturing technology is impressive, it is
only half the story. In today’s IC business the key
to success is able to rapidly design a
differentiated product and quickly bring it to the
market place. However, this cannot be done
without a sophisticated infrastructure of design
components and software to support an efficient
design process that ensures that we manufacture
silicon that is “right-the-first-time”. This
infrastructure which supports the design process
is called: design technology. As the progress of
manufacturing technology into the nanometer
regime has thrown many new complexities into
the design process thereby creating significant
challenges in the field of design technology.
Solving these design technology challenges is
critical to achieving market success with
nanometer integrated circuits.
MAJOR DESIGN ISSUES
Technologies of the deep and Very deep
submicron era have responded to the non-
scalability of threshold voltages by
accommodating higher and higher static leakage
currents. But now a number of problems arising
from continued scaling confront the designer.
These issues include excessive power dissipation
density, gate oxide tunneling current, self heating
of the device and interconnect, and a host of
subsequent reliability issues. Some issues are
followed as:
a) Gate-to-Body Tunneling/Leakage Current:
As the gate oxide thickness is scaled to
maintain gate control, threshold voltage, and
performance, the oxide tunneling leakage
increases. Nitride oxide, which reduces the
leakage by order of magnitude, has been
widely used in the industry to contain this
leakage. Nevertheless, the oxide tunneling
leakage increases for every 0.1 nm decrease
in oxide thickness.
b) Substrate Current due to Impact
Ionization: As the scaling of MOSFETs
proceeds, impact ionization of carriers in the
high field region (velocity saturation or
pinch-off region) becomes serious. The holes
generated during the process of impact
ionization flow through the substrate and
result in a substrate current.
c) Band to band tunneling (BTBT) current: It
occurs at the surface of the depletion layer
under the gate-drain overlap region, is
notable in the sub-threshold region in thin-
gate-oxide MOSFETs when the gate is
grounded and the drain is biased at high
voltage.
d) Polysilicon Gate Depletion: As a gate
voltage is applied to a heavily doped poly-Si
gate, e.g. NMOS with n+ Polysilicon (poly-
Si) gate, a thin depletion layer in the poly-Si
can be formed at the interface between the
poly-Si and the gate oxide. This depletion
layer is very thin because of the high doping
concentration in the poly-Si gate.
e) Self-heating Effect: Heat dissipation is a
critical issue in circuit design. The
temperature rise caused by the power
consumption of devices in a chip may need to
be considered because the device density has
become huge in modern VLSI circuits.
Concluding Remarks
Silicon MOSFETs have been the smallest
electronic device for several decades. Thirty five
years ago, the gate oxide thickness was already in
the nano-scale (120 nm) for commercial
products. The gate oxide thickness is now 1.2 nm
in production and 0.8 nm in research. Note that
the 5-nm gate length is the distance of 18 atoms
and 0.8-nm oxide thickness is two atomic layers
only. Si technology is no doubt the most
successful nano-devices. Even the Si devices
reach the downsizing limit no matter 10 nm, 5
nm, or 1 nm, other emerging devices such as
molecular transistors will also reach their limit of
downsizing in similar dimensions. It is a critical
period for moving from 100-nm to 10-nm
technology within this decade. Most of materials
and the manufacturing processes used in the deep
and very deep-submicron era are now pushing to
their physical limits. New materials and
technologies are required for further down-
scaling the device to 10-nm technology and
below. Immersion lithography for ultra fine
patterning, strained channels, nickel salicide,
high-k gate dielectric, low-k interlayer for
interconnect, plasma doping, flash and laser
annealing for source and drain doping, elevated
source and drain and three-dimensional
MOSFETs for controlling short-channel effects,
would help to overcome the materials and
technological constraints and improve the device
performance in the ultra-small scale. The final
remark is a non-technical issue. We anticipate
that this issue will be one of the most important
issues for nano-CMOS technology development
in the next 15 years. We are aware that most of
the new mega-fabs being planned or under
construction are in the East and Southeast Asia,
and particularly the Mainland China. In 10 or 15-
year’s time, the distribution of semiconductor
manufacturing sites in Asia (including Japan)
will be quite substantial. Currently, Korea and
Taiwan are in the first place for semiconductor
memory manufacturing and semiconductor
foundry, respectively. They also lead the
technology development in Asia region.
Mainland China seems to be another super power
for semiconductor manufacturing. The share of
China semiconductor manufacturing will keep
fast growing with the support of booming IC
design houses, constructing new fabs with
remarkable increase in industrial investment, and
will be the most important huge and rapidly
expending market. As many other industries and
other sectors of electronic products, Mainland
China will eventually become “the factory of the
world” in semiconductor manufacturing in 15
years or longer and will have great impact on the
future nano-CMOS technology.