Sei sulla pagina 1di 169

OPERATIONAL MANUAL

FOR

SP3 DSP TRAINER MODEL : MXS3FK-DSP Rev : 003

MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR, NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038

PHONE : +91-20-25386926/ 29 FAX : +91-20-25386930 EMAIL : mtepl@vsnl.net

URL

:

www.mte-india.com

Table of Contents

Introduction

1

DSP Algorithm Design Flow

1

Design using System Generator:

1

Algorithm Verification and Implementation Design Flow

2

Linking the System and FPGA Design Domains

2

System Modeling and Design

3

Algorithm Development

3

Hardware Generation and Simulation

3

Debug and Verification

3

Implementation of a core generated by MATLAB in Xilinx ISE tool

4

Understanding the Number System

5

Design Example for FIR Filter

6

Steps To Implement the Filter in DSP-Protoboard

6

ADC-DAC Controller in VHDL

6

ADC-DAC Controller in Verilog

9

LAB 1

17

Generate Waveforms using DAC

17

1.1 Introduction

17

1.2 Specifications of DAC AD7541:

17

1.3 Objective

18

1.4 Design Description

18

1.5 Experimental Set up

18

1.6 Procedure

18

1.7 Simulate the Design Using ModelSim

19

1.8 Synthesize the Design Using XST

21

1.9 Running the Xilinx Implementation Tools

22

1.10 Download design into DSP Protoboard

23

1.11 Conclusion

24

LAB 2

26

Verification of Sampling Theorem using ADC-DAC

26

2.1 Introduction

26

2.2 Objective

26

2.3 Design Description:-

26

2.4 Experimental Set up:-

27

2.5 Generate, Synthesize, and Place & Route in Xilinx

29

2.6 For physical verification:

33

2.7 Assignments

33

LAB 3

34

FIR filter using windowing method

34

3.1 Introduction

34

3.2 Objective

34

3.3 Procedure

34

3.4 Assignments

44

LAB 4

45

Design of FIR filter

45

4.1 Introduction

45

4.2 Procedure

45

4.3 Filter Design

45

4.4 Simulate the FIR filter in Simulink

47

4.5 Generate Synthesize and Place and Route

48

4.6 Download the bit file in the

49

4.7 Assignments

49

LAB 5

50

Implementation of aliasing effect

50

5.1 Introduction

50

5.2 Objective

50

5.3 Design Description

50

5.4 Procedure

51

5.5 Simulate the Design Using Modelsim

51

5.6 Synthesize the Design Using XST

51

5.7 Running Xilinx Implementation tool

51

5.8 Assignments

51

LAB 6

52

IMPULSE RESPONSE OF GIVEN FILTER

52

6.1 Introduction

52

6.2 Design Procedure Using MATLAB:

53

6.3 Pulse Generator

53

LAB 7

56

Design Of A Bandpass Filter

56

7.1 Procedure

56

7.2 Assignments

56

LAB 8

57

Design Of A Band Reject Filter

57

8.1 Procedure

57

8.2 Assignments

57

LAB 9

58

Noise Removal

58

9.1 Noise Removal

58

9.2 Hardware Description

58

9.3 Filter Design Procedure using MATLAB

58

9.4 Filter Specifications:

60

9.5 Signal Generator:

60

9.6 Gateway In

60

9.7 FIR Filter Design:

61

9.8 FDA Tool:-

62

9.9 GATEWAY Out

63

LAB 10

65

Compiling MATLAB into an FPGA

65

10.1 Introduction

65

LAB 11

70

Design of A High Pass Filter

70

11.1 Introduction

70

11.2 Procedure

70

11.3 Filter Design

70

11.4 Generate, Synthesize, and Place & Route

75

11.5 Conclusion

76

11.6 Assignments

77

LAB 12

79

Multirate Signal Processing

79

12.1 Introduction

79

12.2 Procedure

79

12.3 Implementation of Design which is generated by MATLAB in Xilinx ISE tool

84

12.4 Assignments

86

LAB 12-A

87

Decimator In Multirate Signal Processing

87

12-A.1 Introduction

87

12-A.2 Procedure

87

12-A.3 Running The Design In Xilinx ISE Software Environment

90

12-A.4: Assignments

93

LAB 12-B

94

Interpolator In Multirate Signal Processing

94

12-B .1 Introduction

94

12-B.2 Procedure

94

12-B.3 Assignments

101

LAB 13

102

Analysis of Audio Signal Using Filters

102

13.1

Introduction

102

13.2 Objective

102

13.3 Design Description

102

13.4

Procedure

102

13.5 Experimental Set up

105

13.6 Further assignments

105

LAB 14

106

Implementation of Stepper Motor Controller

106

14.1

Introduction:-

106

14.2 Objective

106

14.3 Design Description:-

107

14.4

Procedure

108

14.5 Experimental Set up:-

110

14.6 Conclusion: -

110

14.7 Further assignments

110

LAB 15

111

USB Controller

111

 

15.1 USB

111

15.2 USB Interfacing:-

111

15.3 USB Interface Devices:-

111

15.4 Features of FT245BM

112

15.5 General Description of USB-FIFO (FTDI):-

112

15.6

LAB Description

113

15.7

Design Description

113

15.8

Procedure:-

114

15.9

Experimental Setup

116

15.10 Conclusion

116

LAB 16

117

Implementation of 8:1 Multiplexer

117

16.1 Introduction:

117

16.2 Objectives:

117

16.3 Design Description:

117

16.4 Experimental Set up:

118

16.5 Steps to implement the 8:1 multiplexer in the FPGA

118

16.6 Conclusion:-

121

16.7 Assignments

122

LAB 17

123

Implementation of 2:4 Decoder

123

17.1 Introduction:-

123

17.2 Objectives:-

123

17.3 Design Description:-

123

17.4 Experimental Set up:-

123

17.5

Steps to implement the 2:4 Decoder in the FPGA

123

17.6 Conclusion:-

125

LAB 17-A

127

Implementation of 8:3 Encoder

127

17-A .1 Introduction:-

127

17-A.2 Objectives:

127

17-A.3 Design Description:

127

17-A.4 Steps to implement the 8:3 Encoder in the FPGA

127

17-A.5 Experimental Set up:-

129

17-A.6 Conclusion:-

129

17-A.7 Assignments

129

LAB 18

130

Implementation of 8:3 Encoder

130

18.1

Introduction:-

130

18.2 Objectives:-

130

18.3 Design Description:-

130

18.4 Experimental Set up:-

130

18.5 Steps to implement the 8:3 Encoder in the FPGA

130

18.6 Conclusion:-

132

18.7

Assignments

132

LAB 19

133

Implementation of 2 Bit Comparator

133

19.1

Introduction:-

133

19.2 Objectives:-

133

19.3 Design Description:-

133

19.4 Experimental Set up:-

134

19.5 Steps to implement the 2 Bit Comparator in the FPGA

134

LAB 20

136

Implementation Of Binary To Gray Code Converter

136

20.1

Introduction:-

136

20.2 Objectives:-

136

20.3 Design Description:-

136

20.4 Truth Table for Binary to Gray Code:

137

20.5 Experimental Set up:

137

20.6 Steps to implement the Binary to Gray code converter

137

20.7 Conclusion:-

139

20.8

Assignments

139

LAB 21

140

Implementation of T Flip Flop

140

21.1

Introduction:-

140

21 2 Objectives:-

140

21.3 Design Description:-

140

21.4 Experimental Set up:

140

21.5 Steps to implement the T Flip Flop

140

21.6 Conclusion

142

21.7 Further assignments

142

LAB 22

143

Scrolling Of Data On Seven-Segment Display Using Keyboard.

143

22.1 Introduction:-

143

22.2 Objective:-

143

22.3 Experimental Set up:-

143

22.4 Procedure:-

143

22.5 Assignments

146

LAB 23

147

Design Of 4-bit Arithmetic Logic Unit

147

23.1 Introduction

147

23.2 Objective

147

23.3 Design Description:-

147

23.4 Experimental Set up:

148

23.5 Procedure:

148

23.6 Conclusion:-

150

23.7 Assignments

150

LAB 24

151

Temperature Sensing Using ADC-DAC Interfacing.

151

24.1

Introduction:-

151

24.2

Objective:-

151

24.3

Design Description:-

151

24.5

Procedure:-

152

24.6

Assignments

154

LAB 25

155

Design of LCD Controller

155

25.1 Introduction

155

25.2 Objective:-

155

25.3 Design Description:-

155

25.4 Experimental set up:-

156

25.5 Procedure:-

156

25.6 Assignments

158

LAB 26

159

Lift Controller

159

26.1 Introduction:-

159

26.2 VHDL Coding

160

26.3 Objective

160

26.4 Procedure

161

26.5 Assignments

163

INTRODUCTION

DSP Algorithm Design Flow

An FPGA provides the user with a two-dimensional array of configurable resources that can implement a wide range of arithmetic and logic functions. These resources include dedicated DSP blocks, multipliers, dual port memories, lookup tables (LUTs), registers, tri-state buffers, multiplexers, and digital clock managers. In addition, Xilinx FPGAs contain sophisticated I/O mechanisms that can handle a wide range of bandwidth and voltage requirements.

FPGAs are high performance data processing devices. FPGA DSP performance is derived from the ability they provide to construct highly parallel architectures for processing data. In contrast with a microprocessor or DSP processor, where performance is tied to the clock rate at which the processor can run, FPGA performance is tied to the amount of parallelism that can be brought to bear in the algorithms making up a signal processing system. A combination of increasingly high system clock rates (current system frequencies of 100-200 MHz are common today) and a highly distributed memory architecture gives the system designer an ability to exploit parallelism in DSP (and other) applications that operate on data streams. For example, the raw memory bandwidth of a large FPGA running at a clock rate of 150 MHz can be hundreds of terabytes per second.

There are many DSP applications (e.g., digital up/down converters) that can be implemented only in custom integrated circuits (ICs) or in an FPGA; a von Neumann processor lacks both the compute capability and the memory bandwidth required. Advantages of using an FPGA include significantly lower non-recurring engineering costs than those associated with a custom IC (FPGAs are commercial off-the-shelf devices), shorter time to market, and the configurability of an FPGA, which allows a design to be modified, even after deployment in an end application.

Design using System Generator:

System Generator for DSP is a software tool for modelling and designing FPGA-based

signal processing systems in Simulink. System Generator extends Simulink to enable hardware design, providing high level

abstractions that can be automatically compiled into an FPGA. The tool presents a high level abstract view of a DSP system; it will map the system to a

faithful hardware implementation. What is most significant is that System Generator provides these services without

substantially compromising either the quality of the abstract view or the performance of the hardware implementation Simulink provides a powerful high level modelling environment for DSP systems, and

consequently is widely used for algorithm development and verification. Simulink provides a graphical environment for creating and modelling dynamical

systems. System Generator consists of a Simulink library called the Xilinx Blockset, and software

to translate a Simulink model into a hardware realization of the model. System Generator maps system parameters defined in Simulink (e.g. as mask variables in Xilinx Blockset blocks), into entities and architectures, ports, signals, and attributes in a hardware realization System Generator automatically produces command files for FPGA synthesis, HDL

simulation, and implementation tools, so that the user can work entirely in graphical environments in going from system specification to hardware realization. When a System Generator project is created, the software produces VHDL design or

cores from the Xilinx CORE Generator. In addition, many other project files are automatically created. The implementation is made efficient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions.

MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two tools. This gap can be filled by Xilinx System Generator Tool. In below block diagram we shows design flow of two different platforms.

Algorithm Verification and Implementation Design Flow

System Design

Domain

Algorithm design Algorithm design Algorithm design
Algorithm design
Algorithm design
Algorithm design
System verification System verification System verification (floating point) (floating point) (floating point)
System verification
System verification
System verification
(floating point)
(floating point)
(floating point)
Conversion to Conversion to Conversion to fixed point fixed point fixed point
Conversion to
Conversion to
Conversion to
fixed point
fixed point
fixed point
Optimization and Optimization and Optimization and re-verification re-verification re-verification
Optimization and
Optimization and
Optimization and
re-verification
re-verification
re-verification

MATLAB and Simulink

MATLAB and Simulink

GAPGAP
GAPGAP
MATLAB and Simulink MATLAB and Simulink GAPGAP FPGA Design Domain Manual design Manual design entry in

FPGA Design

Domain

Manual design Manual design entry in HDL entry in HDL
Manual design
Manual design
entry in HDL
entry in HDL
Hardware Hardware simulation simulation
Hardware
Hardware
simulation
simulation
Synthesis, place Synthesis, place and route and route
Synthesis, place
Synthesis, place
and route
and route
Timing verification Timing verification
Timing verification
Timing verification

Foundation/Alliance

Foundation/Alliance

Linking the System and FPGA Design Domains

System Design Domain

Algorithm design
Algorithm design
System verification (floating point)
System verification
(floating point)
Conversion to fixed point
Conversion to
fixed point
Optimization and re-verification
Optimization and
re-verification

MATLAB and Simulink

FPGA Design Domain

and re-verification MATLAB and Simulink FPGA Design Domain Automatic generation of HDL Xilinx System Hardware
Automatic generation of HDL Xilinx System Hardware simulation Generator & LogiCOREs Synthesis, place and route
Automatic
generation of HDL
Xilinx System
Hardware
simulation
Generator &
LogiCOREs
Synthesis, place
and route
Timing verification
Hardware simulation Generator & LogiCOREs Synthesis, place and route Timing verification Foundation/Alliance

Foundation/Alliance

Our system designer flow confronts signal processing, control, and project management challenges in the process of developing DSP solutions. The System Generator for DSP design flow encompasses the entire design process.

System Modeling and Design

You can use familiar tools such as Simulink to develop your DSP system models. System Generator for DSP includes a Xilinx Blockset comprised of basic level building blocks such as FFTs and advanced DSP algorithms such as digital down converters. When combined with Simulink, System Generator enables you to build sophisticated DSP systems. By using it with Xilinx Platform Studio, you can also create microprocessor based control circuits. You can also bring in your own HDL modules via, or write MATLAB code for combinational control logic or state machines.

Algorithm Development

MATLAB is an excellent language for creating complex algorithms such as matrix operations and linear algebra. With the Xilinx AccelDSP Synthesis tool, you can automatically translate these algorithms into RTL and export them into a larger Simulink/System Generator system.

Hardware Generation and Simulation

You can use the System Generator tool to automatically generate highly efficient VHDL or Verilog code. To synthesize the VHDL/Verilog you have a choice of tools including Xilinx Synthesis Technology (XST), Synplify Pro from Synplicity or FPGA Advantage from Mentor Graphics. HDL modules can also be incorporated into a Simulink/System Generator design via a black box and co-simulated using ModelSim.

You can also create a VHDL testbench and data vectors with System Generator for DSP. These vectors represent the inputs and expected outputs seen in the Simulink simulation, and allow you to easily see any discrepancies between Simulink and VHDL results. FPGA Advantage can be used to conduct simulations of DSP systems prior to implementation. ModelSim is required for HDL co-simulation.

Debug and Verification

Using high bandwidth hardware in the loop, you can accelerate simulations and verify your designs using FPGA hardware. If ChipScope™ Pro probes are introduced in the system modeling and design phase, they are automatically inserted into the design during hardware generation. These probes facilitate debugging by allowing internal nodes to be observed.

Xilinx System Generator for DSP manages the entire design flow from a single environment

Following files are created by Xilinx System Generator

.vhd - the top level VHDL file for your project. There are additional VHDL files included when your design has more hierarchy.

core - files associated with the generated multiplier core, such as the behavioral simulation models and EDIF file.

corework - subdirectory containing the CORE Generator log file.

.xcf - generated constraints file when XST synthesis is chosen in the System Generator block. Buses in this file are denoted with angle brackets.

.ncf - generated constraints file when Synplify or Leonardo Spectrum is chosen as the synthesis tool. Buses are denoted with parentheses.

.npl - project file for opening the design in Xilinx ISE 6.2i Project Navigator, using your chosen synthesis compiler and ModelSim simulator.

testbench.vhd - the top level VHDL testbench file, associated with the top level VHDL source file in the project

<gateways>.dat - stimulus files for inputs to testbenches, or predicted outputs of testbenches. The .dat files are generated by Simulink simulation and saved for running in

Xilinx testbenches to verify design behavior. In this example, <gateways> refers to the names of the Xilinx gateway blocks, which collect and save the data.

VhdlFiles - a list of VHDL files, and their dependency order, needed for synthesis projects. System Generator's Perl scripts read from this file when creating project files.

Globals - a file containing the characteristics of the design needed by downstream software tools in order to synthesize and implement.

Synplify_fir_filtert.prj - a project file for running this design in Synplify (synthesis tools from Synplicity) if you have chosen it as your synthesis tool in the System Generator block.

XST_fir_filtert.prj - a project file for running this design in XST if you have chosen it as your synthesis tool in the System Generator block.

Spectrum_fir_filtert.tcl - a project file for running this design in Leonardo Spectrum (synthesis tools from Mentor Graphics).

Pn_behavioral.do, pn_posttranslate.do, pn_postmap.do, Pn_postpar.do - compilation and simulation do files for running this design through simulation at different stages. These 4 files are associated with ModelSim simulation through the Xilinx ISE 6.2i Project Navigator.

Vcom.do, vsim.do - default behavioral simulation files for use with ModelSim.

Sysgen.log - log file. xlRunScripts.log - logfileshowing status of post-processing scripts run by System Generator.

Implementation of a core generated by MATLAB in Xilinx ISE tool.

of a core generate d by MATLAB in Xilinx ISE tool. • Simulation : Verifying the

Simulation : Verifying the design specifications after design entry is functional simulation. It Saves the time consumed for physical prototyping

Synthesis : Is the process of creating a representation of a system at a lower level of design abstraction from a higher level representation Synthesis tools provides a means to convert schematic or HDL in real-world hardware. The output of synthesis is a netlist.

For locking physical pins with the designed entity user constraint file(UCF) has to specify by the user.

Implementation : Is the process of placing the design into the specified target technology. Implementation tool reads the standard netlist & fits it into the target device.

Following steps are performed by the implementation tool Mapping:Tool partitions the design into the logic blocks available on the device. Good partitioning results in better performance. Placing : After the logic is partitioned, implementation software searches for the best location to place the logic block among all of the possibilities. Primary goal is to reduce the amount of routing recourses required. Routing : Logical nets are assigned to the physical wire segments in the device that interconnect logic cells.

Programming:

After the design is Implemented, software creates the bitstream ( binary programming ).

The programmable device is configured for the function by downloading the

programming file into target. After the device is programmed, you are ready to test the actual system, with real life inputs and outputs.

Understanding the Number System

Basis of implementing a DSP system are

“A-PRIORY KNOWLEDGE”, meaning a prior knowledge of the available hardware and the signals that, will be applied to the input and are expected at the output.

It is all about “Assigning Meaning to Numbers”, meaning The input signals have to be converted properly to the number system being implemented in hardware The numbers available at the system output have to be understood and then converted to analog domain.

System Generator “System Generator for DSP” ( SysGen) is an EDA tool offered by Xilinx. It acts as a bridge between a design environment which is Matlab (simulink) and the hardware implementation environment, which is a Xilinx FPGA. System generator when loaded with Matlab, adds a Xilinx Blockset in the Simulink Library Browser. This blockset consists of synthesizable blocks for various applications in Communication and DSP. The “System Generator” block, allows automatic generation of VHDL code. This code can be synthesized and implemented in the target device using Xilinx ISE tool.

In this document we the detailed steps to implement a Simple Filter in hardware, using the Matlab (simulink ) and System Generator for DSP Tools. The Filter will be implemented using DSP development board from Mechatronics Test Equipment.

HARDWARE DESCRIPTION

The following is the configuration of the DSP development board.

It has a built-in Signal Generator generates, which generates a Sine wave of amplitude 10V peak to peak.

ADC on board has the following specifications

Resolution - 12 bits.

Input range - ±10V.

Output Format - ADC output can be in straight Binary or 2’s complement format.

DAC on-board has the following specifications

Resolution 12 bits

Output Range - ±10V.

Output Format – Straight Binary.

Crystal oscillator on board has a freq of 4 MHz.

Design Example for FIR Filter

STEPS TO BE FOLLOWED TO DESIGN FIR FILTER IN SIMULINK

Blocks required:

Where to find

FIR

Xilinx - DSP Blockset

Gateway-In, Gateway-out

Xilinx – Basic Elements

Signal Generator

Simulink – Sources

Scope

Simulink – Sinks

System Generator

Xilinx – Basic Elements

Inputs to System Generator Block:

Device Family = Spartan-III (check FPGA device in your DSP PROTOBOARD)

Target Directory = User defined

Check in “Create Test bench” option

Click on “Generate”

Steps To Implement the Filter in DSP-Protoboard

Change the device type to XC3S400-4PQ208.

Add source files : lowpass.vhd, adc_7891.vhd.

Change the name of the component in “lowpass.vhd” according to the entity name in

the VHDL file generated by system generator (project name). Assign the generic number n in “lowpass.vhd” the value equal to the Gateway_out

signal’s bus-width. Add “UCF” file at the “implement design” step.

Configure FPGA.

ADC-DAC Controller in VHDL

--Description: Combines the ADC-DAC Controller module and User Generated module. --Required component : DSP PROTOBOARD --VHDL code for ADC (AD7891) and DAC (AD 7541) interfacing

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adc_dac_test is

generic (n : natural := 21); Port (

clk

reset

: in std_logic; : in std_logic;

-- Local clock -- Local reset signal

----------------------------- For ADC1(7891)---------

adc_clk

: out std_logic; --sampling frequency to ADC

cs_ad7891

: out std_logic; --chip select

convst_ad7891

: out std_logic; --conversion start

wr_ad7891

: out std_logic; --write

rd_ad7891

: out std_logic; --read

eoc_ad7891

: in std_logic; --end of conversion

mode_ad7891

: out std_logic; --mode=1 for parallel

db_7891

: inout std_logic_vector(11 downto 0);--ADC

bidirectional input/output

---------------------------------For DAC-----------------

bit_trun

: in std_logic_vector( 7 downto 0);

dac_sel

: in std_logic_vector(1 downto 0);

--- DAC selection. IL0 and IL1 are used

ch_adc

: in std_logic_vector( 1 downto 0);

dac_out en ); end adc_dac_test;

--- Input channel selection for ADC --- IL6 and IL7 are used for Ch_adc --- 00 for ch1,01 for ch2,10 for ch3,11 for ch4 : out std_logic_vector(11 downto 0); ---Output to DAC : out std_logic_vector( 3 downto 0) ---DAC latch enable

architecture Behavioral of adc_dac_test is

type state_1 is (reset_1, write_cwr, start_conv, read_data);

signal ps_1, ns_1 signal dac_out_s, signal dacout signal div_adc

---This should be changed as per input on board clock

signal decade

signal sampling_clk, wr_s, clk_s, rd_s, convst_ad7891_s

signal db_7891_s

: state_1; : std_logic_vector(11 downto 0); : std_logic_vector(n downto 0); : std_logic_vector(15 downto 0 );

: std_logic_vector( 3 downto 0 );

: std_logic_vector( 11 downto 0 );

: std_logic;

component lowpass -- Change the name of the component in “lowpass.vhd” according to the entity

: in std_logic;

--Name in the VHDL file generated by system generator (project name).

port (

clk

gateway_in

: in std_logic_vector(11 downto 0);

gateway_out

: out std_logic_vector(21 downto 0));

end component; begin -----------------------------Clk Divider------------------------ --Decade counter is used because on board clock is 20 MHz. It can be 40 MHz --or 4 MHz.In case of 20/40 MHz we have to use decade counter to get 2/4 MHz. --In case of 4 MHz bypass decade counter. This arrangement is made so as to --design filter or any other application irrespective of input clk at --particular clock frequency. Otherwise every time we will have to change --frequency of our design. We cannot have similar frequency by direct --division of input clock 20/40/4 MHz. For example 4 divided --by 5 FF to have 62.5KHz.if we want this frequency from 20/40 MHz clock --we get 78.125.

process(clk, reset) begin

if(reset = '1') then decade <= (others => '0'); elsif(clk'event and clk = '1') then if decade="1001" then

decade<=(others=>'0');

else decade <= decade + 1; end if; end if; end process; clk_s<='1' when decade="1001" else

'0';

process(clk_s, reset) begin if(reset = '1') then div_adc <= (others => '0'); elsif(clk_s'event and clk_s = '1') then div_adc <= div_adc + 1; end if; end process;

sampling_clk <=div_adc(2) ; ---Input clock is very fast so divided clock is used as sampling clock to FSM. ----FSM will divide sampling clock ---by four so sampling clock for ADC is 62.5KHz.

adc_clk <= sampling_clk; --- Used just for checking, mapped to output LED OL0.

-------------------------------------------------------------------------

process(reset, sampling_clk) begin if(reset = '1' ) then ps_1 <= reset_1; elsif (sampling_clk'event and sampling_clk = '1') then ps_1 <= ns_1; end if; end process;

-------------------------------------------------------------------------

process(ps_1)

begin case ps_1 is when reset_1 => ns_1 <= write_cwr; when write_cwr => ns_1 <= start_conv; when start_conv => ns_1 <= read_data; when read_data => ns_1 <= reset_1; end case; end process; cs_ad7891 <= '0' when (ps_1 = read_data or ps_1 = write_cwr) else

'1';

wr_s <='0' when (ps_1 = write_cwr) else

‘1';

wr_ad7891 <= wr_s;

rd_s <= '0'when (ps_1 = read_data) else

'1';

rd_ad7891 <= rd_s; mode_ad7891 <= '1'; -- set parallel mode of ADC

--- Write channel number db_7891(5 downto 0) <=

'0' & ch_adc & "000" when wr_s = '0' else

(others => 'Z');

-----------------------------convst------------------------

process(reset, sampling_clk) begin if(reset = '1') then convst_ad7891_s <= '0'; elsif(sampling_clk'event and sampling_clk = '1') then convst_ad7891_s <= wr_s; end if; end process;

convst_ad7891 <= convst_ad7891_s;

--------------------------read adc-------------------------- process(reset, clk,rd_s) begin

if(reset = '1') then db_7891_s <= (others => '0'); elsif(sampling_clk'event and sampling_clk = '0') then if(rd_s = '0') then db_7891_s <= db_7891; end if; end if;

end process; ------------------ write ADC Data to DAC ------------------------- dac_out_s <= dacout(n downto n-11) when bit_trun(0)='1' else dacout(n-1 downto n-12) when bit_trun(1)='1' else dacout(n-2 downto n-13) when bit_trun(2)='1' else dacout(n-3 downto n-14) when bit_trun(3)='1' else dacout(n-4 downto n-15) when bit_trun(4)='1' else dacout(n-5 downto n-16) when bit_trun(5)='1' else dacout(n-6 downto n-17) when bit_trun(6)='1' else dacout(n-7 downto n-12) when bit_trun(7)='1' else dacout(n-8 downto n-12) ; dac_out<= (dac_out_s(11)&( not dac_out_s( 10 downto 0))) +'1' when dac_out_s(11)='0' else dac_out_s(11)&( not dac_out_s( 10 downto 0)); ----------------------DAC selection logic-------------------------- process(dac_sel) begin case dac_sel is when "00" => en<="1000" ; when "01" => en<="0100"; when "10"=> en <="0010"; when "11"=> en <="0001"; when others=> null; end case; end process;

Inst_untitled: lowpass port map( clk =>div_adc(4) , ---Filter is operating at 62.5KHz so we have divided the clock gate way_in =>db_7891_s , gateway_out =>dacout );

end Behavioral;

ADC-DAC Controller in Verilog

// Description: Combines the ADC-DAC Controller module and User Generated module. //Required component : DSP PROTOBOARD //Verilog code for ADC (AD7891) and DAC (AD 7541) interfacing

module lowpassvlog

(smpclk,dac_out,en,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,re

set,clk,dac_sel, bit_trunc,ch_adc,db_7891); output smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891; output [11:0] dac_out; output [3:0] en; input clk, reset; input [7:0] bit_trunc; input [1:0] dac_sel; input [1:0] ch_adc; inout [11:0] db_7891; reg [3:0] en; reg cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,convst_ad7891_s; wire sampling_clk,wr_s,rd_s; wire [11:0] dac_out_s; wire [21:0] dacout; `define reset_1 2'd0

2'd1

`define start_conv 2'd2

`define read_data 2'd3

`define write_cwr

reg [1:0] ps_1; reg [1:0] ns_1; reg [3:0] div; wire [5:0] conc;

wire [11:0] conc1; reg [15:0] div_adc; reg [11:0] adcin,db_7891_s; wire clk_s;

always @ (posedge reset or posedge clk) begin if (reset) div = 4'b0000; else if (div == 4'b1001)

div = 4'b0000;

else

div = div + 4'b0001;

end

assign clk_s = (div == 4'b1001) ? 1'b1:1'b0;

always @ (posedge reset or posedge clk_s) begin if (reset) div_adc = 16'd0; else div_adc = div_adc + 1;

end

assign sampling_clk = div_adc[2]; assign smpclk = sampling_clk;

always @ (posedge reset or posedge sampling_clk) begin if (reset) ps_1 = `reset_1; else ps_1 = ns_1; end

always @ (ps_1) begin case (ps_1)

`reset_1

: ns_1 = `write_cwr;

`write_cwr : begin cs_ad7891 = 1'b0; ns_1 = `start_conv; end `start_conv : ns_1 = `read_data; `read_data : begin cs_ad7891 = 1'b0; ns_1 = `reset_1;

endcase

end

end

assign conc = {1'b0,ch_adc,3'b0}; assign db_7891[5:0] = (wr_s == 1'b0) ? conc : 6'bZZZZZZ;

always @ (posedge reset or posedge sampling_clk) begin if (reset) convst_ad7891_s = 1'b0; else convst_ad7891_s = wr_s;

end

always @ (convst_ad7891_s) convst_ad7891 = convst_ad7891_s;

always @ (posedge reset or negedge sampling_clk) begin if (reset) db_7891_s = 12'b0; else if (!rd_s) db_7891_s = db_7891;

end

always @ (db_7891_s) adcin = db_7891_s;

always mode_ad7891 = 1'b1;

assign wr_s = (ps_1 == `write_cwr) ? 1'b0 :1'b1; assign rd_s = (ps_1 == `read_data) ? 1'b0 : 1'b1;

always @ (rd_s or wr_s) begin wr_ad7891 = wr_s; rd_ad7891 = rd_s;

end

always @ (dac_sel) begin case (dac_sel)

2'b00

: en = 4'b1000;

2'b01

: en = 4'b0100;

2'b10

: en = 4'b0010;

2'b11

: en = 4'b0001;

default : en = 4'b0000;

endcase

end

lowpass u1(.clk(div_adc[4]),.gateway_in(adcin),.gateway_out(dacout));

assign dac_out_s = bit_trunc[0] ? dacout[21:10] :

(bit_trunc[1] ? dacout[20:9] :

(bit_trunc[2] ? dacout[19:8] :

(bit_trunc[3] ? dacout[18:7] :

(bit_trunc[4] ? dacout[17:6] :

(bit_trunc[5] ? dacout[16:5] :

(bit_trunc[6] ? dacout[15:4] :

(bit_trunc[7] ? dacout[14:3]:

dacout[13:2])))))));

assign conc1 = {dac_out_s[11],~dac_out_s[10:0]}; assign dac_out = (dac_out_s[11] == 0) ? (conc1 + 1) : conc1; endmodule

Note :

The component name represented in BOLD (e.g. lowpass) letters is required to be changed according to the entity name in the module generated by user. The value of n must be equal to the bus-width of the Gateway_out signal in the module generated by user.

SPARTAN III PQ208 – connections details of on board peripherals

Clock & Reset

Clock & Reset

Signal

"GCLK1"

"GCLK2"

"RESET"

Spartan III Pin Number

76

77

78

RS232 Serial Port

RS232 Serial Port

"RXD1"

"TXD1"

205

204

 

STEPPER MOTOR INTERFACE

 

"A1_COIL"

 

43

"A2_COIL"

 

42

"B1_COIL"

 

37

"B2_COIL"

 

39

 

RELAY

"RELAY0"

 

40

 

ADC

 

DAC

Signal

FPGA pin

Signal

FPGA pin

Number

Number

"DB0"

45

"DAC0"

81

"DB1"

46

"DAC1"

79

"DB2"

57

"DAC2"

100

"DB3"

58

"DAC3"

97

"DB4"

61

"DAC4"

93

"DB5"

62

"DAC5"

90

"DB6"

63

"DAC6"

94

"DB7"

64

"DAC7"

95

"DB8"

65

"DAC8"

96

"DB9"

67

"DAC9"

102

"DB10"

68

"DAC10"

101

"DB11"

71

"DAC11"

80

"MODE"

72

"EN1"

87

"EOC"

44

"EN2"

85

"\CONVST\"

48

"EN3"

86

"\CS\"

50

"EN4"

74

"\WR\"

52

   

"\RD\"

51

   

Signal

FPGA pin

Signal

FPGA pin

Number

Number

"USB_D0"

106

"USB_D6"

114

"USB_D1"

107

"USB_D7"

115

"USB_D2"

108

"RD#"

116

"USB_D3"

109

"WR#"

117

"USB_D4"

111

"TXE#"

119

"USB_D5"

113

"RXF#"

120

USB INTERFACE

INPUT SWITCHES

Signal

FPGA pin Number

Connecter name and pin number

"IL0"

141

J1-7

"IL1"

140

J1-8

"IL2"

139

J1-11

"IL3"

138

J1-12

"IL4"

137

J1-13

"IL5"

135

J1-14

"IL6"

133

J1-15

"IL7"

132

J1-16

"IL8"

131

J1-17

"IL9"

130

J1-18

"IL10"

128

J1-21

"IL11"

126

J1-22

"IL12"

125

J1-23

"IL13"

124

J1-24

"IL14"

123

J1-25

"IL15"

122

J1-26

KEY SWITCHES

 

Signal

FPGA pin

Jumper name and pin number

Number

"KEY0"

143

J1-6

"KEY1"

144

J1-5

"KEY2"

146

J1-4

"KEY3"

147

J1-3

OUTPUT LEDs

 

Signal

FPGA pin

Jumper name and pin number

Number

"OL0"

161

J2-34

"OL1"

172

J2-24

"OL2"

156

J2-43

"OL3"

171

J2-33

"OL4"

155

J2-36

"OL5"

169

J2-26

"OL6"

154

J2-35

"OL7"

168

J2-25

"OL8"

152

J2-38

"OL9"

167

J2-28

"OL10"

150

J2-37

"OL11"

166

J2-27

"OL12"

149

J1-1

"OL13"

165

J2-32

"OL14"

148

J1-2

"OL15"

162

J2-31

7 SEGMENT DISPLAY

Signal

FPGA pin

Jumper name and pin number

Number

"SEGA"

189

J2-8

"SEGB"

190

J2-7

"SEGC"

187

J2-12

"SEGD"

185

J2-11

"SEGE"

184

J2-14

"SEGF"

183

J2-13

"SEGG"

182

J2-16

"SEGDP"

181

J2-15

 

SEG. DISPLAY SELECTION

"CSDIS0"

175

J2-18

"CSDIS1"

176

J2-17

"CSDIS2"

178

J2-22

"CSDIS3"

180

J2-21

LCD DISPLAY

USER I/O’S

Signal

FPGA pin

Jumper name and pin number

Number

"DL0"

33

J3-32

"DL1"

31

J3-31

"DL2"

29

J3-28

"DL3"

28

J3-27

"DL4"

27

J3-26

"DL5"

26

J3-25

"DL6"

24

J3-24

"DL7"

22

J3-23

"E"

36

J3-33

"R/W"

35

J3-34

"RS"

34

J3-35

Type

FPGA PIN

Connector pin Number

Number

"I/O1_QS"

21

J3-22

"I/O2_QS"

20

J3-21

"I/O3_QS"

19

J3-18

"I/O4_QS"

18

J3-17

"I/O5_QS"

16

J3-16

"I/O6_QS"

15

J3-15

"I/O7_QS"

13

J3-14

"I/O8_QS"

12

J3-13

"I/O9_QS"

11

J3-12

"I/O10_QS"

10

J3-11

"I/O11_QS"

9

J3-8

"I/O12_QS"

7

J3-7

"I/O13_QS"

5

J3-6

"I/O14_QS"

4

J3-5

"I/O15_QS"

3

J3-4

"I/O16_QS"

2

J3-3

"I/O17_QS"

203

J3-1

"I/O18_QS"

200

J3-2

"I/O19_QS"

199

J2-1

"I/O20_QS"

198

J2-2

"I/O21_QS"

197

J2-3

"I/O22_QS"

196

J2-4

"I/O23_QS"

194

J2-5

"I/O24_QS"

191

J2-6

LAB 1

Generate Waveforms using DAC

1.1 Introduction

Analog signals represent real physical parameters with accuracy, but it is difficult to process or store them. It is necessary to translate an Analog signal into a Digital signal. Similarly, a digital signal needs to be translated into an analog signal to represent a physical quantity. Quite often it is also necessary to decode any digital signal, the most obvious method is to use D/A converter for each signal. Therefore it is necessary to study the behaviour of DAC. For that waveform generation using DAC is done. Various waveforms such as square, sine, triangular, ramp etc. can be generated. In this lab ramp waveform is being generated.

DAC:- Digital to analog conversion involves translation of digital signal into equivalent analog signal. Applications of DACs include digital voltmeters, peak detectors, panel meters, programmable gain and attenuation, and stepping motor drive.

1.2 Specifications of DAC AD7541:

DAC type – Monolithic Multiplying DAC structure.

Resolution - 12 bits

Conversion time - 100 ns

Settling time – 600 ns

Output Range – (-10 to +10 Volts, Bipolar)

The two important aspects of the D/A converter are the Resolution & Accuracy of the conversion.

ACCURACY:-Accuracy is a measure of how close the actual output voltage is to the theoretical output voltage.

RESOLUTION:-Resolution is the smallest increment in output voltage and is determined by the LSB. Ex:-If the full scale Analog voltage is 10V, the smallest unit or the LSB is equivalent to 1/2 n of 10V. This is defined as resolution.

DAC AD7541 used on SP3 DSP Protoboard is 12 bit and the Full scale voltage of the analog output block is 10V Hence the resolution of the analog output block is 10V/2 12 LSB = 10/2 12 MSB= ½ full scale = 5V

Full scale output

=(Full scale Value–(1 LSB))

= 10V-(10V/2 12 ). ------For 12 bit DAC

= 9.998V.

Figure1 shows a block diagram of a 3-bit DAC and characteristics of digital input vs. analog output

Figure 1 1.3 Objective After completing this lab you will be able to • Perform

Figure 1

1.3 Objective

After completing this lab you will be able to

Perform the basic design flow for generating Counter in VHDL.

Simulate a VHDL file.

Synthesize a design using XST.

Implement a design using the Xilinx implementation tools.

It will help you to understand behaviour of DAC it should show proper RAMP at the output.

1.4 Design Description

In this lab ramp waveform is being generated, for that you will have to design a counter .Counter output is mapped to DAC input as shown in figure. This will help you to understand behaviour of DAC & interfacing of DAC with FPGA to generate waveforms of different amplitude and frequency.

1.5 Experimental Set up

different amplitude and frequency. 1.5 Experimental Set up In above figure we can implement 3 bit

In above figure we can implement 3 bit loadable up /down counter. with asynchronous reset. Counter output is given to DAC to generate Ramp output waveform.

1.6 Procedure

To design Counter, perform the following steps:

Step 1:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start

Step 2:

Programs Xilinx ISE 7 Project Navigator In the Project Navigator window go on FILE New project select device.

Step 3: Click on FPGA symbol of device and then right click click on new

Step 3:

Click on FPGA symbol of device and then right click click on new source VHDL module give name count Define ports finish.

Step 4:

Generate the Behavioural VHDL Code for the counter.

Step 5:

Check syntax, remove errors if present.

Step 5: Check syntax, remove errors if present. 1.7 Simulate the Design Using ModelSim In this

1.7 Simulate the Design Using ModelSim

In this procedure, simulate your VHDL code to verify that it is functioning correct. After simulation if there is an error, you can go back and make changes, recompile the code, and resimulate.

To run the functional simulation, perform the following steps:

Step 1:

Again generate test waveform using Test bench waveform Editor.

Step 2:

Highlight count_tb.vhd file in the Sources in Project window.

Step 3:

Expand the Xilinx simulator /Modelsim simulator in the Processes for Current Source window.

simulator in the Processes for Current Source window. Step 4: then Model Technology window pops-up, click

Step 4:

then Model Technology window pops-up, click Run ModelSim. The simulation will run. Otherwise on the ISE simulator window waveforms are displayed.

Double-click on Simulate Behavioral VHDL Model. If the modelsim simulator is used

s

Behavioral VHDL Model. If the modelsim simulator is used s Step 5: Verify the operation of

Step 5:

Verify the operation of the counter by looking at the input and output signals in the test bench named *_tb

Note: It may be easier to view the input and output in decimal. This can

Note: It may be easier to view the input and output in decimal. This can be done by highlighting the appropriate signals in the waveform viewer, then use the pull down menus Format Radix Decimal.

Step 6:

After you verify operation you can close ModelSim .If the counter is not functioning correctly, verify your VHDL code and re-run the simulation.

1.8 Synthesize the Design Using XST

Now that design has been verified using the ModelSim VHDL behavioural simulator, you can synthesize your design. We do this by using the Xilinx Synthesis Technology (XST).

To synthesize your design, perform the following steps:

Step 1:

Highlight counter.vhd file in the Sources in Project window.

Step 2:

To run synthesis, right-click on Synthesize, and choose the Run option, or double- click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed.

appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a

A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

Step 3

If there are any errors, you can View Synthesis Report by expanding Synthesis, right- click and Choose the View option; otherwise continue on to the next step.

the View option; otherwise continue on to the next step. 1.9 Running the Xilinx Implementation Tools

1.9 Running the Xilinx Implementation Tools

Once synthesis is complete, you can place and route your design to fit into the FPGA provided on the protoboard (XC3S400-5PQ208), you can also get post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation.

To run the implementation tools, perform the following steps:

Step 1:

Right-click Implement Design, and choose the Run option, or double left-click Implement Design.

Step 1: Right-click Implement Design , and choose the Run option, o r double left-click Implement

This runs the design through Place and Route. You will notice green check marks (or warning exclamations) next to the processes that means finished successfully.

Step 2:

To get the Post Place and Route Timing, run Generate Post-Place & Route Static Timing, and when finished, expand and open the Text. Based Post-Place & Route Static Timing Report.

Text. Based Post-Place & Route Static Timing Report. You can view the results in the console

You can view the results in the console window

1.10 Download design into DSP Protoboard

For Downloading bitstream into DSP Protoboard follow the procedure given below.

Before the implementation write UCF file using User constraints in workspace

Double click on create timing constraints ports Locations

UCF file using User constraints in workspace • Double click on create timing constraints ports Locations

Note: - User constraint file (UCF) is used to lock the input and output which we are going to use.

Step 8: Step 9: Right-click on Generate Programming File, and choose the Run option, or
Step 8:
Step 9:
Right-click on Generate Programming File, and choose the Run option, or double
left-click on Generate Programming File. This will generate the Bitstream.
Double click on Configure Device to download the bitstream.
Step 10:
Connect the CRO probe to the DAC Out terminal to observe “Ramp
waveform” as shown in figure below. Thus the digital input applied through counter is
converted into an analog ramp waveform.
through counter is converted into an analog ramp waveform. 1.11 Conclusion You should now know the

1.11 Conclusion

You should now know the basic design flow for taking VHDL through the design process. You have:

Realized some challenges in writing the VHDL counter.

Run a piece of VHDL code through simulation.

Run synthesis using XST.

Run a synthesized design through the Xilinx implementation tools.

After downloading check output of DAC on Four output analog channel.

1. What is the Implementation Result. See the Place and Route report file and fill in the information below

Number of slices:

Number of global buffers (BUFGMUXs):

Number of IOBs:

2. Open the Post-Place and Routing Timing report, and fill in the information requested below

Maximum clock frequency:

Generate a square and triangular waveform. (Hint. Change the counter direction according to waveform)

3. Maximum clock frequency:

4. Design counter which will give Ramp output waveform of amplitude 2.5V. (Hint – Refer graph of digital input Vs analog output and modify the counter.)

5. Modify the design to change the frequency of Ramp wave

6. What will be the change in the functionality if we want an inverted ramp at the output?

7. How will you change the step size?

8. What will happen if the time scale is changed? Draw the waveform and write down the observations for two different time scales.

9. Write a code to generate sine wave, square wave and triangular wave at the output of the DAC. Try for different values of frequency and amplitude keeping in mind the specifications of DAC.

10. How 4MHz clock frequency can be divided to see counter response on LEDs. If clock is applied directly what would you observe?

11. Define Resolution Time & Settling Time.

LAB 2

Verification of Sampling Theorem using ADC-DAC

2.1 Introduction

Most signals such as speech, biological signals, various communication signals such as audio and video signals, are analog. To process analog signals by digital means, it is first necessary to convert them into digital form. The devices used for this are Analog to Digital converters (ADCs). In many cases it is desirable to convert the processed digital signals into analog form. This process is done by Digital-to-Analog converters (DACs).

In this lab, sampling theorem is verified. According to the Sampling theorem, the sampling frequency should be double or more than double the highest input frequency. The input to ADC is given through an external source and here sampling frequency is fixed. The input frequency can be increased to see the aliasing effect at the output. Aliasing is the process where a sinusoid changes from one frequency to another as a result of sampling or other non-linear action and usually results in a loss of signal’s information. Increasing the input frequency to more than half the sampling frequency gives aliased low frequency waveform at the output.

2.2 Objective

The design example in this lab is to demonstrate

How to write and execute Matlab Simulink program.

How to generate VHDL/VERILOG code from the system generator.

How to modify ADC-DAC program according to your application.

How to use in build function generator.

How to adjust sampling frequency.

2.3 Design Description:-

External/On-Board Analog input can be given to the ADC, it converts applied analog input to 12-Bit Digital signals. This signal is then given to DAC via FPGA and the output is checked at the DAC output.

Five channels of ADC are used, wherein Channel 1 to Channel 4 gets the input from an external source & Channel 5 th is used on board for Thermister.

Output of ADC is then given to FPGA, Conversion Start, ADC clock and channel address signals are generated through FPGA. FPGA receives End of conversion (EOC) from ADC.

FPGA will map ADC output directly to DAC input.

Digital to Analog converter accepts input from FPGA, converts digital data to Analog signal.

Output of DAC is available on the connector. (Refer connector details given below)

data to Analog signal. • Output of DAC is available on the c onnector. (Refer connector

2.4 Experimental Set up:-

Step1:

Open the MATLAB command window by double clicking on the MATLAB

Step2:

icon, which is provided on the desktop. Open the Simulink library browser window by typing Simulink on the

Step3:

command prompt (>> Simulink) or clicking on the Simulink library browser. Now open the new model file by >> File >> New >> Model.

Step4:

Go to Simulink library browser and click on sources and select the signal

Step5:

generator block and drag that into new model file. Then you click on sinks, here you select the scope and drag that on to the

sheet.

Step6:

Then you click on Xilinx block set in the library browser and then click on basic elements and select the system generator block, Gateway In, and Gateway Out blocks and drag them on to new model file.

and Gateway Out blocks and drag them on to new model file. Step7: Fig1. shows the

Step7:

Fig1. shows the Simulink library Now interconnect all the blocks. The following figure shows how it looks

like. Fig. shows how to interconnect the different Simulink block.

The following figure shows how it looks like. Fig. shows how to interconnect th e different

Step8:

Double click on each block, the parameter window will open and select the parameters. For signal generator choose parameters as waveform as sine wave, amplitude as 3V, and frequency as 0.135 rad/sec.

Note: Frequency (rad/sec) = 2πFp / Fs.

Fig. shows how to set signal property of signal generator Simulink block

to set signal property of signal generator Simulink block Now double click on Gate Way In

Now double click on Gate Way In block, the parameter window will open and fill the

Way In block, the parameter wi ndow will open and fill the parameters as given below.

parameters as given below. Step9: Run your simulation and observe the output waveform by double clicking the Simulink scope. Step10: Now double click on the System Generator block , parameter window will open Here you select target device in which you want to implement your design and target directory that is location at which you want to store your VHDL project file. The parameter window looks as shown in figure.

Step11: After selecting the proper device and proper project directory click on Generate . Here

Step11: After selecting the proper device and proper project directory click on Generate. Here the pop up window will open that shows the running of system generator as shown in figure.

shows the running of system generator as shown in figure. Step12 : 2.5 Generate, Synthesize, and

Step12:

2.5 Generate, Synthesize, and Place & Route in Xilinx

Check the generated code in specified folder.

Step1:

Double click on Xilinx project navigator icon, which is provided on the

desktop.

Step2:

Now go to >> File. >> Open project, here you have to specify the path at which your design has been stored.

to specify the path at which your design has been stored. Step3: Step4: Now add the

Step3:

Step4:

Now add the ADC_DAC controller VHDL Design to your file. This is done as:

Right click on the source file and click on add new source. The following shows how it happens.

on add new source. The following shows how it happens. After that you have to write

After that you have to write user constraint file for the ADC_DAC controller VHDL Design. This is also done by right clicking on source file >> new source>>Implement constraint file. >> file name >>next The following depicts that.

Step5: After writing constraint file you go to processes for source window and run the

Step5:

After writing constraint file you go to processes for source window and run the synthesize process. The following depicts that.

run the synthesize process. The following depicts that. Step6: After running synthesize process run the implement

Step6:

After running synthesize process run the implement design. The following depicts that.

run the implement design . The following depicts that. Step7: click on Generate program file .

Step7:

click on Generate program file. and go to the properties. Then pop up window will open. In that you go to start up options and select the desired clock. The following is depicts that.

Step8: The above process will generate the bit file. Now right click on the configure

Step8:

The above process will generate the bit file. Now right click on the configure device and click on the properties. Then pop up window will open. Select the particular configuration mode. The following figure depicts that.

Then pop up window will open. Select the particular configuration mode . The following figure depicts
Then pop up window will open. Select the particular configuration mode . The following figure depicts
Then pop up window will open. Select the particular configuration mode . The following figure depicts

Step9:

downloading bit file into the FPGA.

After selecting the configuration mode you program your device by

Note: System generator generates the code corresponding to the logic in between Gateway In and Gateway Out. The signal generator and the scope used by the system generator are just for simulation.

Use onboard function generator for input signal. Observe the results on CRO. This function generator and CRO are for physical verification.

2.6 For physical verification:

After configuring the device you apply the input signal to any one channel of ADC (ch1, ch2, ch3, ch4) and output of DAC i.e. (Vout1, Vout2, Vout3, Vout4) is applied to CRO and observe if there is any deviation from input

Repeat same procedure for various ADC sampling frequency by changing the positions of DIP switches (IL0, IL1, and IL2) and observe the output.

The above procedure should repeat for square wave and triangular wave inputs.

2.7 Assignments

1 Open the place and route tool and fill the following?

Number of slices consumed:

Number of IOBs:

Number of GBUFs:

2 What would be the effect of change in sampling frequency?

3 Repeat the whole experiment for square & triangular input signal.

4 Change the sampling frequency and input frequency. Observe the aliasing effect on CRO.

5 How to select the sampling frequency of ADC?

6 Write down the specifications of ADC and DAC.

7 What is the maximum input frequency?

8 If two more channels of ADC are used, what will be the

change in

the above code?

9 See the Place & Route report and give the number of global buffers, LUTs, and IOBs.

10 Change the input frequency and observe the change at the output.

LAB 3

FIR filter using windowing method

3.1 Introduction

In this lab, you can study one way to specify, simulate, and implement a FIR filter using the MATLAB Filter Design & Analysis Tool (FDA Tool). The FDA Tool is used to define the filter order and coefficients, and the Xilinx FIR filter Blockset is used for the implementation and Simulink simulation.

MATLAB is a tool which is best suited for DSP algorithm development. Xilinx ISE tool is used for implementation of systems in FPGA. But there is a gap between these two. tools. This gap can be filled by Xilinx System Generator Tool

The algorithms /system can be verified using MATLAB Simulink blocks. Xilinx system generator tool is a part of Simulink tool box. System generator is used to generate VHDL and all supporting files. Xilinx ISE tool. is used to synthesize, implement and programming of FPGA.

Design a FIR Filter using Windowing method for a given frequency response.

Sampling frequency (Fs)

Passband frequency (Fpass)

Stopband frequency (Fstop) =4500Hz

=20000Hz

=3000Hz

Passband attenuation (Apass)

=1dB

Stopband attenuation (Astop)

=80dB

To design the filters by using “window” method. Here we have to design the filter in the FDATool with the desired filter specifications and export the coefficients to the Simulink workspace. Windowing is one of the method for designing FIR filter. Other method is the “frequency sampling” method.

3.2 Objective

After completing this lab you will be able to write and simulate Simulink program. Understanding the basics of building in designing a system generator. Simulate the design in the System Generator. Run the system generator token for generating the VHDL code. Run the designs through System Generator design flow.

3.3 Procedure

Step1:

Open the MATLAB command window by double clicking the MATLAB icon that is provided on the desktop.

Step2:

Open the Simulink window by typing the Simulink at the command prompt (>> Simulink) or clicking on the Simulink Library Browser. The Simulink window will be as shown below.

Step3: • SIMULINK (sources and sinks) • DSP Block set • XILINX Block set Look

Step3:

SIMULINK (sources and sinks)

DSP Block set

XILINX Block set

Look at the blocks that are available on the window. The following are the blocks.

Step4:

Right click on block on the library brow ser and choose help from the MATLAB menu

the library brow ser and choose help from the MATLAB menu This bring up the details

This bring up the details of the block and it also work on the Xilinx block set elements

Step5 : Create a new model file Go to file >> new >> model Step6:
Step5 :
Create a new model file
Go to file >> new >> model