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Data Sheet
High-Performance,
16-bit Digital Signal Controllers
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-60932-889-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Peripheral Features:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • High current sink/source I/O pins: 25 mA/25 mA
intended to be a complete reference • Three 16-bit timers/counters; optionally pair up
source. For more information on the CPU, 16-bit timers into 32-bit timer modules
peripherals, register descriptions and
• Four 16-bit capture input functions
general device functionality, refer to the
“dsPIC30F Family Reference Manual” • Two 16-bit compare/PWM output functions
(DS70046). For more information on the - Dual Compare mode available
device instruction set and programming, • 3-wire SPI modules (supports 4 Frame modes)
refer to the “16-bit MCU and DSC Pro- • I2CTM module supports Multi-Master/Slave mode
grammer’s Reference Manual” and 7-bit/10-bit addressing
(DS70157). • Addressable UART modules with FIFO buffers
UART
2 TM
SRAM EEPROM Timer Input A/D 10-bit
QEI
SPI
Device Pins Mem. Bytes/ Comp/Std Control
I C
Bytes Bytes 16-bit Cap 1 Msps
Instructions PWM PWM
MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 PWM1L/RE0
AN2/SS1/CN4/RB2 4 25 PWM1H/RE1
dsPIC30F2010
AN3/INDX/CN5/RB3 5 24 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 23 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 22 PWM3L/RE4
VSS 8 21 PWM3H/RE5
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/RF3
VDD 13 16 FLTA/INT0/SCK1/OCFA/RE8
EMUD2/OC2/IC2/INT2/RD1 14 15 EMUC2/OC1/IC1/INT1/RD0
28-Pin QFN-S(1)
EMUC3/AN1/VREF- /CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
PWM1H/RE1
PWM1L/RE0
MCLR
AVDD
AVSS
22
28
27
26
25
24
23
AN2/SS1/CN4/RB2 1 21 PWM2L/RE2
AN3/INDX/CN5 RB3 2 20 PWM2H/RE3
AN4/QEA/IC7/CN6/RB4 3 19 PWM3L/RE4
AN5/QEB/IC8/CN7/RB5 4 dsPIC30F2010 18 PWM3H/RE5
VSS 5 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO/RC15 7 15 PGC/EMUC/U1RX/SDI1/SDA/RF2
10
12
13
14
11
8
9
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD2/OC2/IC2/INT2/RD1
VDD
EMUC2/OC1/IC1/INT1/RD0
PGD/EMUD/U1TX/SDO1/SCL/RF3
FLTA/INT0/SCK1/OCFA/RE8
Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Y Data Bus
X Data Bus
16 16 16 16
16
Interrupt Data Latch Data Latch
Controller PSV and Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(256 bytes) (256 bytes)
Address Address
24 Latch Latch
16 16 16
24 X RAGU
Y AGU
PCU PCH PCL X WAGU EMUD3/AN0/VREF+/CN2/RB0
Program Counter EMUC3/AN1/VREF-/CN3/RB1
Address Latch Stack Loop AN2/SS1/CN4/RB2
Control Control
Logic Logic AN3/INDX/CN5/RB3
Program Memory
(12 Kbytes) AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
Data EEPROM
(1 Kbyte) Effective Address PORTB
Data Latch 16
ROM Latch 16
24
IR
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
16 16 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array PORTC
Decode
Instruction
Decode and 16 16
Control
Input Output
10-bit ADC Capture Compare I2C™
PWM1L/RE0
Module Module
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
Motor Control FLTA/INT0/SCK1/OCFA/RE8
SPI1 Timers QEI UART1
PWM
PORTE
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
PORTF
D15 D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
PC22 PC0
0 Program Counter
7 0
TABPAG
TBLPAG Data Table Page Address
7 0
PSVPAG Program Space Visibility Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter
22 0
DOSTART DO Loop Start Address
22
DOEND DO Loop End Address
15 0
CORCON Core Configuration Register
SRH SRL
S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder
Negate
40
40 40
Barrel
16
Shifter
40
X Data Bus
Sign-Extend
Y Data Bus
32 16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16 16
To/From W Array
User Memory
3.1 Program Address Space 0000FE
Space
000100
User Flash
The program address space is 4M instruction words. It Program Memory
is addressable by a 24-bit value from either the 23-bit (4K instructions)
PC, table instruction Effective Address (EA), or data 001FFE
space EA, when program space is mapped into data 002000
Reserved
space, as defined by Table 3-1. Note that the program (Read 0’s)
space address is incremented by two between succes- 7FFBFE
7FFC00
sive program words, in order to provide compatibility Data EEPROM
(1 Kbyte)
with data space addressing. 7FFFFE
User program space access is restricted to the lower 800000
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
Reserved
clear.
Note: The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Configuration Memory
8005BE
Space
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
F7FFFE
Device Configuration F80000
Registers F8000E
F80010
Reserved
FEFFFE
DEVID (2) FF0000
FFFFFE
23 bits
Using
Program 0 Program Counter 0
Counter
Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits
EA
User/ Byte
Configuration 24-bit EA
Space Select
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
TBLRDL.B (Wn<0> = 1)
(Read as ‘0’)
TBLRDH.W
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’) TBLRDH.B (Wn<0> = 1)
3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each pro-
MEMORY USING PROGRAM SPACE gram memory word, the Least Significant 15 bits of
VISIBILITY data space addresses directly map to the Least Signif-
icant 15 bits in the corresponding program space
The upper 32 Kbytes of data space may optionally be addresses. The remaining bits are provided by the Pro-
mapped into any 16K word program space page. This gram Space Visibility Page register, PSVPAG<7:0>, as
provides transparent access of stored constant data shown in Figure 3-5.
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the MSb of the data space EA is set and program For instructions that use PSV which are executed
space visibility is enabled, by setting the PSV bit in the outside a REPEAT loop:
Core Control register (CORCON). The functions of
• The following instructions will require one instruc-
CORCON are discussed in Section 2.4 “DSP
tion cycle in addition to the specified execution
Engine”.
time:
Data accesses to this area add an additional cycle to - MAC class of instructions with data operand
the instruction being executed, since two program prefetch
memory fetches are required.
- MOV instructions
Note that the upper half of addressable data space is - MOV.D instructions
always part of the X data space. Therefore, when a
• All other instructions will require two instruction
DSP operation uses program space mapping to access
cycles in addition to the specified execution time
this memory region, Y data space should typically con-
of the instruction.
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient For instructions that use PSV which are executed
(constant) data. inside a REPEAT loop:
Although each data space address, 0x8000 and higher, • The following instances will require two instruction
maps directly into a corresponding program memory cycles in addition to the specified execution time
address (see Figure 3-5), only the lower 16-bits of the of the instruction:
24-bit program word are used to contain the data. The - Execution in the first iteration
upper 8 bits should be programmed to force an illegal - Execution in the last iteration
instruction to maintain machine robustness. Refer to - Execution prior to exiting the loop due to an
the “16-bit MCU and DSC Programmer’s Reference interrupt
Manual” (DS70157) for details on instruction encoding.
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
15 PSVPAG(1)
EA<15> = 0 0x00
8
Data 16
Space 0x8000
EA 15 23 15 0
Address
EA<15> = 1 0x001200
15 Concatenation 23
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2 Data Address Space When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
The core has two data spaces. The data spaces can be 256 byte data address space (including all Y
considered either separate (for some DSP instruc- addresses). When executing one of the MAC class of
tions), or as one unified linear address range (for MCU instructions, the X block consists of the 256 bytes data
instructions). The data spaces are accessed using two address space excluding the Y address block (for data
Address Generation Units (AGUs) and separate data reads only). In other words, all other instructions regard
paths. the entire data memory as one composite address
space. The MAC class instructions extract the Y
3.2.1 DATA SPACE MEMORY MAP address space from data space and address it using
The data space memory is split into two blocks, X and EAs sourced from W10 and W11. The remaining X data
Y data space. A key element of this architecture is that space is addressed using W8 and W9. Both address
Y space is a subset of X space, and is fully contained spaces are concurrently accessed only with the MAC
within X space. In order to provide an apparent linear class instructions.
addressing space, X and Y spaces have contiguous A data space memory map is shown in Figure 3-6.
addresses.
MSB LSB
Address 16 bits Address
MSB LSB
0x0001 0x0000
SFR Space SFR Space
(See Note)
0x07FF 0x07FE
0x0801 0x0800
2560 bytes
Near
X Data RAM (X)
256 bytes Data
Space
512 bytes 0x08FF 0x08FE
SRAM Space 0x0901 0x0900
0x09FF 0x0A00
(See Note)
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE
X Space
Unused
X Space
X Space
Unused
Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11
dsPIC30F2010
TABLE 3-3: CORE REGISTER MAP
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)
W0 0000 W0 / WREG 0000 0000 0000 0000
W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000
TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000
© 2011 Microchip Technology Inc.
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 29
dsPIC30F2010
NOTES:
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the Effective Address (EA).
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant
value to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
Byte
Address MOV #0x1100,W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
0x1100 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
0x1163
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
2. The Stack Pointer is loaded with a value which IVT Reserved Vector
Reserved Vector
is less than 0x0800 (simple stack underflow). Reserved Vector
Interrupt 0 Vector 0x000014
Interrupt 1 Vector
Oscillator Fail Trap: —
—
This trap is initiated if the external oscillator fails and —
operation becomes reliant on an internal RC backup. Interrupt 52 Vector
Interrupt 53 Vector 0x00007E
Reserved 0x000080
Reserved 0x000082
Reserved 0x000084
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
AIVT Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector 0x000094
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector 0x0000FE
dsPIC30F2010
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 — — — — — — — — INT2IF — — — — IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — — FLTAIF — — QEIIF PWMIF — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E — — — — — — — — INT2IE — — — — IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — — FLTAIE — — QEIIE PWMIE — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — — — — — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0000 0000 0000
IPC6 00A0 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000
IPC9 00A6 — PWMIP<2:0> — — — — — — — — — — — — 0000 0000 0000 0000
IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0100
IPC11 00AA — — — — — — — — — — — — — — — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
6.0 FLASH PROGRAM MEMORY Master Clear (MCLR). This allows customers to manu-
facture boards with unprogrammed devices, and then
Note: This data sheet summarizes features of program the digital signal controller just before shipping
this group of dsPIC30F devices and is not the product. This also allows the most recent firmware
intended to be a complete reference or a custom firmware to be programmed.
source. For more information on the CPU,
peripherals, register descriptions and 6.2 Run-Time Self-Programming
general device functionality, refer to the (RTSP)
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the RTSP is accomplished using TBLRD (table read) and
device instruction set and programming, TBLWT (table write) instructions.
refer to the “16-bit MCU and DSC Pro- With RTSP, the user may erase program memory, 32
grammer’s Reference Manual” instructions (96 bytes) at a time and can write program
(DS70157). memory data, 32 instructions (96 bytes) at a time.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There 6.3 Table Instruction Operation Summary
are two methods by which the user can program this
The TBLRDL and the TBLWTL instructions are used to
memory:
read or write to bits<15:0> of program memory.
1. In-Circuit Serial Programming (ICSP™) TBLRDL and TBLWTL can access program memory in
programming capability Word or Byte mode.
2. Run-Time Self-Programming (RTSP) The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
6.1 In-Circuit Serial Programming and TBLWTH can access program memory in Word or
(ICSP) Byte mode.
dsPIC30F devices can be serially programmed while in A 24-bit program memory address is formed using
the end application circuit. This is simply done with two bits<7:0> of the TBLPAG register and the EA from a W
lines for Programming Clock and Programming Data register specified in the table instruction, as shown in
(which are named PGC and PGD respectively), and Figure 6-1.
three other lines for Power (VDD), Ground (VSS) and
24 bits
Using
Program 0 Program Counter 0
Counter
NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits
Working Reg EA
User/Configuration Byte
Space Select Select
24-bit EA
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS
NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 47
dsPIC30F2010
NOTES:
PIO Module 1
Output Data
Read TRIS 0
Data Bus D Q
I/O Pad
WR TRIS CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TRISB 02C6 — — — — — — — — — — TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111
PORTB 02C8 — — — — — — — — — — RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CA — — — — — — — — — — LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000
PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000
TRISD 02D2 — — — — — — — — — — — — — — TRISD1 TRISD0 0000 0000 0000 0111
PORTD 02D4 — — — — — — — — — — — — — — RD1 RD0 0000 0000 0000 0000
LATD 02D6 — — — — — — — — — — — — — — LATD1 LATD0 0000 0000 0000 0000
TRISE 02D8 — — — — — — — TRISE8 — — TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0001 0011 1111
PORTE 02DA — — — — — — — RE8 — — RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
LATE 02DC — — — — — — — LATE8 — — LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000
TRISF 02DE — — — — — — — — — — — — TRISF3 TRISF2 — — 0000 0000 0000 1100
PORTF 02E0 — — — — — — — — — — — — RF3 RF2 — — 0000 0000 0000 0000
LATF 02E2 — — — — — — — — — — — — LATF3 LATF2 — — 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
CNPU2 00C6 — — — — — — — — — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DS70118J-page 55
dsPIC30F2010
NOTES:
The following sections provide a detailed description of When the CPU goes into the Idle mode, the timer will
the operational modes of the timers, including setup stop incrementing, unless the respective TSIDL bit = 0.
and control registers along with associated block If TSIDL = 1, the timer module logic will resume the
diagrams. incrementing sequence upon termination of the CPU
Idle mode.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a 16-bit Asynchronous Counter Mode: In the 16-bit
free running interval timer/counter. The 16-bit timer has Asynchronous Counter mode, the timer increments on
the following modes: every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
• 16-bit Timer then resets to ‘0’ and continues.
• 16-bit Synchronous Counter
When the timer is configured for the Asynchronous
• 16-bit Asynchronous Counter mode of operation and the CPU goes into the Idle
Further, the following operational characteristics are mode, the timer will stop incrementing if TSIDL = 1.
supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit period register match or falling
edge of external gate signal
PR1
Equal
Comparator x 16 TSYNC
1 Sync
(3)
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
SOSCO/ TON 2
1X
T1CK
SOSCI
TCY 00
C1
SOSCI
SOSCO
C2 R
C1 = C2 = 18 pF; R = 100K
dsPIC30F2010
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR1 0100 Timer 1 Register uuuu uuuu uuuu uuuu
PR1 0102 Period Register 1 1111 1111 1111 1111
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the least
significant word and Timer3 is the most significant word
Note: This data sheet summarizes features of of the 32-bit timer.
this group of dsPIC30F devices and is not
Note: For 32-bit timer operation, T3CON control
intended to be a complete reference
bits are ignored. Only T2CON control bits
source. For more information on the CPU,
are used for setup and control. Timer 2
peripherals, register descriptions and
clock and gate inputs are utilized for the
general device functionality, refer to the
32-bit timer module, but an interrupt is
“dsPIC30F Family Reference Manual”
generated with the Timer3 interrupt flag
(DS70046).
(T3IF), and the interrupt is enabled with
This section describes the 32-bit general purpose the Timer3 interrupt enable bit (T3IE).
Timer module (Timer2/3) and associated operational 16-bit Mode: In the 16-bit mode, Timer2 and Timer3
modes. Figure 10-1 depicts the simplified block dia- can be configured as two independent 16-bit timers.
gram of the 32-bit Timer2/3 module. Figure 10-2 and Each timer can be set up in either 16-bit Timer mode or
Figure 10-3 show Timer2/3 configured as two 16-bit Synchronous Counter mode. See Section 9.0
independent 16-bit timers; Timer2 and Timer3, “Timer1 Module” for details on these two operating
respectively. modes.
Note: Timer2 is a ‘Type B’ timer and Timer3 is a The only functional difference between Timer2 and
‘Type C’ timer. Please refer to the Timer3 is that Timer2 provides synchronization of the
appropriate timer type in Section 22.0 clock prescaler output. This is useful for high frequency
“Electrical Characteristics” for details. external clock inputs.
The Timer2/3 module is a 32-bit timer, which can be 32-bit Timer Mode: In the 32-bit Timer mode, the timer
configured as two 16-bit timers, with selectable operat- increments on every instruction cycle up to a match
ing modes. These timers are utilized by other value, preloaded into the combined 32-bit period regis-
peripheral modules such as: ter PR3/PR2, then resets to ‘0’ and continues to count.
• Input Capture For synchronous 32-bit reads of the Timer2/Timer3
• Output Compare/Simple PWM pair, reading the least significant word (TMR2 register)
will cause the most significant word (msw) to be read
The following sections provide a detailed description,
and latched into a 16-bit holding register, termed
including setup and control registers, along with asso-
TMR3HLD.
ciated block diagrams for the operational modes of the
timers. For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
The 32-bit timer has the following modes:
a write to the TMR2 register, the contents of TMR3HLD
• Two independent 16-bit timers (Timer2 and will be transferred and latched into the MSB of the
Timer3) with all 16-bit operating modes (except 32-bit timer (TMR3).
Asynchronous Counter mode)
32-bit Synchronous Counter Mode: In the 32-bit
• Single 32-bit Timer operation Synchronous Counter mode, the timer increments on
• Single 32-bit Synchronous Counter the rising edge of the applied external clock signal,
Further, the following operational characteristics are which is synchronized with the internal phase clocks.
supported: The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
• ADC Event Trigger to ‘0’ and continues.
• Timer Gate Operation
When the timer is configured for the Synchronous
• Selectable Prescaler Settings Counter mode of operation and the CPU goes into the
• Timer Operation during Idle and Sleep modes Idle mode, the timer will stop incrementing, unless the
• Interrupt on a 32-bit Period Register Match TSIDL (T2CON<13>) bit = ‘0’. If TSIDL = ‘1’, the timer
These operating modes are determined by setting the module logic will resume the incrementing sequence
appropriate bit(s) in the 16-bit T2CON and T3CON upon termination of the CPU Idle mode.
SFRs.
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3 TMR2 Sync
MSB LSB
ADC Event Trigger
Comparator x 32
Equal
PR3 PR2
0
T3IF
Event Flag 1 Q D TGATE(T2CON<6>)
Q CK
TGATE
(T2CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Prescaler
Gate 1, 8, 64, 256
Sync 01
TCY
00
Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
PR2
Equal
Comparator x 16
TMR2 Sync
Reset
0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR3
TMR3
Reset
0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
Sync 1 X
Prescaler
See 0 1 1, 8, 64, 256
NOTE
TCY 0 0
Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used:
1. TCS = 1
2. TCS = 0 and TGATE = 1 (gated time accumulation)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu
TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu
TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu
PR2 010C Period Register 2 1111 1111 1111 1111
PR3 010E Period Register 3 1111 1111 1111 1111
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 65
dsPIC30F2010
NOTES:
16 16
ICx ICTMR
Pin 1 0
Edge FIFO
Prescaler Clock
Detection R/W
1, 4, 16 Synchronizer
Logic Logic
3 ICM<2:0> ICxBUF
Mode Select
ICBNE, ICOV
ICI<1:0>
Interrupt
ICxCON Logic
Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N.
dsPIC30F2010
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu
IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
12.0 OUTPUT COMPARE MODULE The key operational features of the Output Compare
module include:
Note: This data sheet summarizes features of • Timer2 and Timer3 Selection mode
this group of dsPIC30F devices and is not
• Simple Output Compare Match mode
intended to be a complete reference
source. For more information on the CPU, • Dual Output Compare Match mode
peripherals, register descriptions and • Simple PWM mode
general device functionality, refer to the • Output Compare during Sleep and Idle modes
“dsPIC30F Family Reference Manual” • Interrupt on Output Compare/PWM Event
(DS70046).
These operating modes are determined by setting
This section describes the Output Compare module the appropriate bits in the 16-bit OCxCON SFR (where
and associated operational modes. The features pro- x = 1 and 2).
vided by this module are useful in applications requiring OCxRS and OCxR in the figure represent the Dual
operational modes such as: Compare registers. In the Dual Compare mode, the
• Generation of Variable Width Output Pulses OCxR register is used for the first compare and OCxRS
• Power Factor Correction is used for the second compare.
Figure 12-1 depicts a block diagram of the Output
Compare module.
OCxRS
3 Output Enable
OCM<2:0>
Comparator Mode Select OCFA
(for x = 1 and 2)
OCTSEL
0 1 0 1
Note: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare
channels 1and 2.
12.3 Dual Output Compare Match Mode The user must perform the following steps in order to
configure the output compare module for PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation:
or 101, the selected output compare channel is config-
1. Set the PWM period by writing to the appropriate
ured for one of two Dual Output Compare modes,
period register.
which are:
2. Set the PWM duty cycle by writing to the OCxRS
• Single Output Pulse mode register.
• Continuous Output Pulse mode 3. Configure the output compare module for PWM
operation.
12.3.1 SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1.
of a single output pulse, the following steps are
required (assuming timer is off): 12.4.1 INPUT PIN FAULT PROTECTION
• Determine instruction cycle time TCY. FOR PWM
• Calculate desired pulse width value based on TCY. When control bits OCM<2:0> (OCxCON<2:0>) = 111,
• Calculate time to start pulse from timer start value the selected output compare channel is again config-
of 0x0000. ured for the PWM mode of operation, with the
• Write pulse width start and stop times into OCxR additional feature of input fault protection. While in this
and OCxRS compare registers (x denotes mode, if a logic ‘0’ is detected on the OCFA/B pin, the
channel 1, 2). respective PWM output pin is placed in the high-imped-
ance input state. The OCFLT bit (OCxCON<4>)
• Set timer period register to value equal to, or
indicates whether a Fault condition has occurred. This
greater than, value in OCxRS compare register.
state will be maintained until both of the following
• Set OCM<2:0> = 100. events have occurred:
• Enable timer, TON (TxCON<15>) = 1.
• The external Fault condition has been removed.
To initiate another single pulse, issue another write to • The PWM mode has been re-enabled by writing
set OCM<2:0> = 100. to the appropriate control bits.
Duty Cycle
12.7 Output Compare Interrupts For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
The output compare channels have the ability to gener- an interrupt will be generated, if enabled. The IF bit is
ate an interrupt on a compare match, for whichever located in the IFS0 status register, and must be cleared
Match mode has been selected. in software. The interrupt is enabled via the respective
For all modes except the PWM mode, when a compare timer interrupt enable bit (T2IE or T3IE), located in the
event occurs, the respective interrupt flag (OCxIF) is IEC0 Control register. The output compare interrupt
asserted and an interrupt will be generated, if enabled. flag is never set during the PWM mode of operation.
The OCxIF bit is located in the corresponding IFS
status register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
dsPIC30F2010
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
OC1RS 0180 Output Compare 1 Master Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Slave Register 0000 0000 0000 0000
OC1CON 0184 — OCFRZ OCSIDL — — — — — — — — OCFLT1 OCTSEL1 OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Master Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Slave Register 0000 0000 0000 0000
OC2CON 018A — OCFRZ OCSIDL — — — — — — — — OCFLT2 OCTSEL2 OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
13.0 QUADRATURE ENCODER The Quadrature Encoder Interface (QEI) is a key fea-
ture requirement for several motor control applications,
INTERFACE (QEI) MODULE
such as Switched Reluctance (SR) and AC Induction
Note: This data sheet summarizes features of Motor (ACIM). The operational features of the QEI are,
this group of dsPIC30F devices and is not but not limited to:
intended to be a complete reference • Three input channels for two phase signals and
source. For more information on the CPU, index pulse
peripherals, register descriptions and • 16-bit up/down position counter
general device functionality, refer to the
• Count direction status
“dsPIC30F Family Reference Manual”
(DS70046). • Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
This section describes the Quadrature Encoder Inter- • Alternate 16-bit Timer/Counter mode
face (QEI) module and associated operational modes.
• Quadrature Encoder Interface interrupts
The QEI module provides the interface to incremental
encoders for obtaining motor positioning data. Incre- These operating modes are determined by setting the
mental encoders are very useful in motor control appropriate bits QEIM<2:0> (QEICON<10:8>).
applications. Figure 13-1 depicts the Quadrature Encoder Interface
block diagram.
TQCKPS<1:0>
Sleep Input TQCS
2
TCY
0
Synchronize
Prescaler
Det 1 1, 8, 64, 256
1
QEIM<2:0>
0
QEIIF
D Q
TQGATE Event
CK Q Flag
Programmable
QEB
Digital Filter
Programmable
INDX
Digital Filter
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB — TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 0000 0000
DFLTCON 0124 — — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 0000 0000 0000
POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000
MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 79
dsPIC30F2010
NOTES:
PWMCON1
PWM Enable and Mode SFRs
PWMCON2
PWM Manual
OVDCON
Control SFR
PWM Generator 3
PDC3 Buffer
16-bit Data Bus
PDC3
Comparator
PWM
Channel 1 Dead-Time PWM1H
Generator 1 Generator and
PTPER Override Logic PWM1L
FLTA
PTPER Buffer
PTCON
SEVTCMP PTDIR
0 0
Duty Cycle
Period
Period
PWMxH
PWMxL
dsPIC30F2010
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
PTCON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000
PTMR 01C2 PTDIR PWM Timer Count Value 0000 0000 0000 0000
PTPER 01C4 — PWM Time Base Period Register 0011 1111 1111 1111
SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000
PWMCON1 01C8 — — — — — PTMOD3 PTMOD2 PTMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 0111 0111
PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> Dead Time A Value 0000 0000 0000 0000
FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000
PDC1 01D6 PWM Duty Cycle 1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle 2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle 3 Register 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
15.0 SPI MODULE Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
Note: This data sheet summarizes features of is completed, the contents of the shift register
this group of dsPIC30F devices and is not (SPIxSR) is moved to the receive buffer. If any trans-
intended to be a complete reference mit data has been written to the buffer register, the
source. For more information on the CPU, contents of the transmit buffer are moved to SPIxSR.
peripherals, register descriptions and The received data is thus placed in SPIxBUF and the
general device functionality, refer to the transmit data in SPIxSR is ready for the next transfer.
“dsPIC30F Family Reference Manual”
Note: Both the transmit buffer (SPIxTXB) and
(DS70046).
the receive buffer (SPIxRXB) are mapped
The Serial Peripheral Interface (SPI) module is a syn- to the same register address, SPIxBUF.
chronous serial interface. It is useful for communicating In Master mode, the clock is generated by prescaling
with other peripheral devices such as EEPROMs, shift the system clock. Data is transmitted as soon as a
registers, display drivers and A/D converters or other value is written to SPIxBUF. The interrupt is generated
microcontrollers. It is compatible with Motorola's SPI at the middle of the transfer of the last bit.
and SIOP interfaces.
In Slave mode, data is transmitted and received as
15.1 Operating Function Description external clock pulses appear on SCK. Again, the inter-
rupt is generated when the last bit is latched. If SSx
Each SPI module consists of a 16-bit shift register, control is enabled, then transmission and reception
SPIxSR (where x = 1 or 2), used for shifting data in are enabled only when SSx = low. The SDOx output
and out, and a buffer register, SPIxBUF. A control reg- will be disabled in SSx mode with SSx high.
ister, SPIxCON, configures the module. Additionally, a
status register, SPIxSTAT, indicates various status The clock provided to the module is (FOSC/4). This
conditions. clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
The serial interface consists of 4 pins: SDIx (serial CKE bit determines whether transmit occurs on transi-
data input), SDOx (serial data output), SCKx (shift tion from active clock state to Idle clock state, or vice
clock input or output) and SSx (active-low slave versa. The CKP bit selects the Idle state (high or low)
select). for the clock.
In Master mode operation, SCK is a clock output, but
in Slave mode, it is a clock input. 15.1.1 WORD AND BYTE
COMMUNICATION
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPIxSR to SDOx pin and simultane- A control bit, MODE16 (SPIxCON<10>), allows the
ously shifts in data from SDIx pin. An interrupt is gen- module to communicate in either 16-bit or 8-bit mode.
erated when the transfer is complete and the 16-bit operation is identical to 8-bit operation, except
corresponding interrupt flag bit (SPI1IF or SPI2IF) is that the number of bits transmitted is 16 instead of 8.
set. This interrupt can be disabled through an interrupt The user software must disable the module prior to
enable bit (SPI1IE or SPI2IE). changing the MODE16 bit. The SPI module is reset
The receive operation is double-buffered. When a when the MODE16 bit is changed by the user.
complete byte is received, it is transferred from A basic difference between 8-bit and 16-bit operation is
SPIxSR to SPIxBUF. that the data is transmitted out of bit 7 of the SPIxSR for
If the receive buffer is full when new data is being 8-bit operation, and data is transmitted out of bit 15 of
transferred from SPIxSR to SPIxBUF, the module will the SPIxSR for 16-bit operation. In both modes, data is
set the SPIROV bit, indicating an overflow condition. shifted into bit 0 of the SPIxSR.
The transfer of the data from SPIxSR to SPIxBUF will
not be completed and the new data will be lost. The 15.1.2 SDOx DISABLE
module will not respond to SCL transitions while SPI- A control bit, DISSDO, is provided to the SPIxCON reg-
ROV is ‘1’, effectively disabling the module until SPIx- ister to allow the SDOx output to be disabled. This will
BUF is read by user software. allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.
Internal
Data Bus
Read Write
SPIxBUF SPIxBUF
Receive Transmit
SPIxSR
SDIx bit 0
SDOx Shift
clock
SS and FSYNC Clock Edge
Control Control Select
SSx
Secondary Primary
Prescaler Prescaler FCY
1:1-1:8 1:1, 1:4,
SCKx 1:16, 1:64
Note: x = 1 or 2, y = 1 or 2.
dsPIC30F2010
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
16.0 I2C™ MODULE 16.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not • I2C Slave operation with 7-bit addressing
intended to be a complete reference • I2C Slave operation with 10-bit addressing
source. For more information on the CPU, • I2C Master operation with 7-bit or 10-bit addressing
peripherals, register descriptions and
See the I2C programmer’s model in Figure 16-1.
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
16.1.2 PIN CONFIGURATION IN I2C MODE
(DS70046).
I2C has a 2-pin interface: pin SCL is clock and pin SDA
2
The Inter-Integrated Circuit (I C™) module provides is data.
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication 16.1.3 I2C REGISTERS
standard, with a 16-bit interface. I2CCON and I2CSTAT are control and status registers,
This module offers the following key features: respectively. The I2CCON register is readable and writ-
• I2C interface supporting both Master and Slave able. The lower 6 bits of I2CSTAT are read-only. The
operation remaining bits of the I2CSTAT are read/write.
• I2C Slave mode supports 7-bit and 10-bit I2CRSR is the shift register used for shifting data,
addressing whereas I2CRCV is the buffer register to which data
• I2C Master mode supports 7-bit and 10-bit bytes are written, or from which data bytes are read.
addressing I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are
• I2C port allows bidirectional transfers between
written during a transmit operation, as shown in
master and slaves
Figure 16-2.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and The I2CADD register holds the slave address. A status
resume serial transfer (SCLREL control) bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator (BRG)
• I2C supports Multi-Master operation; detects bus
reload value.
collision and will arbitrate accordingly
In receive operations, I2CRSR and I2CRCV together
16.1 Operating Function Description form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
The hardware fully implements all the master and slave and an interrupt pulse is generated. During
functions of the I2C Standard and Fast mode transmission, the I2CTRN is not double-buffered.
specifications, as well as 7- and 10-bit addressing.
Note: Following a Restart condition in 10-bit
Thus, the I2C module can operate either as a slave or mode, the user only needs to match the
a master on an I2C bus. first 7-bit address.
I2CRCV (8 bits)
bit 7 bit 0
I2CTRN (8 bits)
bit 7 bit 0
I2CBRG (9 bits)
bit 8 bit 0
I2CCON (16 bits)
bit 15 bit 0
I2CSTAT (16 bits)
bit 15 bit 0
I2CADD (10 bits)
bit 9 bit 0
I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB
SDA Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
Write
I2CSTAT
Start, Restart,
Stop bit Generate
Read
Control Logic
Collision
Detect
Write
I2CCON
Acknowledge
Read
Generation
Clock
Stretching Write
I2CTRN
Shift LSB Read
Clock
Reload
Control Write
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000
I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111
I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000
I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000
I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000
I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 101
dsPIC30F2010
NOTES:
Write Write
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
‘0’ (Start)
UxTX
‘1’ (Stop)
Control
Signals
Note: x = 1 only.
UxMODE UxSTA
LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control
FERR
PERR
Receive Shift Register Signals
UxRX
0 (UxRSR)
Note: x = 1 only.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
U1MODE 020C UARTEN — USIDL — — ALTIO — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 109
dsPIC30F2010
NOTES:
AVDD
VREF+
AVSS
VREF-
AN0 AN0
AN3 +
S/H CH1 ADC
-
-
16-word, 10-bit
Dual Port
Buffer
Bus Interface
AN2 AN2
AN5 +
S/H CH3
- CH1,CH2,
CH3,CH0 Sample/Sequence
Sample Control
AN0
AN1 Input
AN2 Switches Input MUX
AN3 AN3 Control
AN4 AN4
AN5 AN5 +
S/H CH0
AN1 -
10
R1
VDD
VREF-
VREF+
AVDD
AVSS
C8
1 μF
dsPIC30F2010 VDD
VDD
VSS VSS
VDD
VDD
C5
1 μF
VDD
TAD Sampling
A/D Speed RS Max VDD Temperature A/D Channels Configuration
Minimum Time Min
Up to 83.33 ns 12 TAD 500Ω 4.5V -40°C to +85°C
VREF- VREF+
1 Msps(1) to
5.5V
CH1, CH2 or CH3
ANx
S/H
ADC
CH0
S/H
ANx CHX
S/H ADC
ANx CHX
S/H ADC
ANx or VREF-
ANx CHX
S/H ADC
ANx or VREF-
Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 18-2 for recommended
circuit.
CHOLD
VA CPIN I leakage = DAC capacitance
VT = 0.6V ± 500 nA = 4.4 pF
VSS
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤5 kΩ.
RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
dsPIC30F2010
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
ADCBUF0 0280 — — — — — — ADC Data Buffer 0 0000 00uu uuuu uuuu
ADCBUF1 0282 — — — — — — ADC Data Buffer 1 0000 00uu uuuu uuuu
ADCBUF2 0284 — — — — — — ADC Data Buffer 2 0000 00uu uuuu uuuu
ADCBUF3 0286 — — — — — — ADC Data Buffer 3 0000 00uu uuuu uuuu
ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu
ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu
ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu
ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu
ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu
ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu
ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu
ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu
ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu
ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu
ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu
ADCBUFF 029E — — — — — — ADC Data Buffer 15 0000 00uu uuuu uuuu
ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000
ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA — — — — — — — — — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
© 2011 Microchip Technology Inc.
dsPIC30F2010
19.0 SYSTEM INTEGRATION 19.1 Oscillator System Overview
Note: This data sheet summarizes features of The dsPIC30F oscillator system has the following
this group of dsPIC30F devices and is not modules and features:
intended to be a complete reference • Various external and internal oscillator options as
source. For more information on the CPU, clock sources
peripherals, register descriptions and • An on-chip PLL to boost internal operating
general device functionality, refer to the frequency
“dsPIC30F Family Reference Manual”
• A clock switching mechanism between various
(DS70046). For more information on the
clock sources
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro- • Programmable clock postscaler for system power
grammer’s Reference Manual” savings
(DS70157). • A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
There are several features intended to maximize sys- • Clock Control Register OSCCON
tem reliability, minimize cost through elimination of
• Configuration bits for main oscillator selection
external components, provide Power-Saving Operating
modes and offer code protection: Table 19-1 provides a summary of the dsPIC30F
Oscillator Operating modes. A simplified diagram of the
• Oscillator Selection
oscillator system is shown in Figure 19-1.
• Reset
Configuration bits determine the clock source upon
- Power-on Reset (POR)
Power-on Reset (POR) and Brown-out Reset (BOR).
- Power-up Timer (PWRT) Thereafter, the clock source can be changed between
- Oscillator Start-up Timer (OST) permissible clock sources. The OSCCON register
- Programmable Brown-out Reset (BOR) controls the clock switching and reflects system clock
• Watchdog Timer (WDT) related status bits.
• Power-Saving modes (Sleep and Idle)
• Code Protection
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
programming capability
dsPIC30F devices have a Watchdog Timer, which is
permanently enabled via the Configuration bits, or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator Start-
up Timer (OST), intended to keep the chip in Reset until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a delay on power-up
only, designed to keep the part in Reset while the
power supply stabilizes. With these two timers on-chip,
most applications need no external Reset circuitry.
Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active, but the CPU is shut off. The RC oscillator
option saves system cost, while the LP crystal option
saves power.
Wake-up Request
FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<1:0>
Primary Osc
NOSC<1:0>
Primary
Oscillator OSWEN
Stability Detector
Oscillator
POR Done Start-up
Clock
Timer
Switching
Programmable
Secondary Osc and Control Clock Divider System
Block
Clock
SOSCO
Secondary 2
32 kHz LP
Oscillator
SOSCI Oscillator
Stability Detector POST<1:0>
CF
Fail-Safe Clock
FCKSM<1:0> Monitor (FSCM)
2 Oscillator Trap
to Timer1
EC Primary 1 1 1 0 1 1 CLKO
ECIO Primary 1 1 1 1 0 0 I/O
EC w/ PLL 4x Primary 1 1 1 1 0 1 I/O
EC w/ PLL 8x Primary 1 1 1 1 1 0 I/O
EC w/ PLL 16x Primary 1 1 1 1 1 1 I/O
ERC Primary 1 1 1 0 0 1 CLKO
ERCIO Primary 1 1 1 0 0 0 I/O
XT Primary 1 1 0 1 0 0 OSC2
XT w/ PLL 4x Primary 1 1 0 1 0 1 OSC2
XT w/ PLL 8x Primary 1 1 0 1 1 0 OSC2
XT w/ PLL 16x Primary 1 1 0 1 1 1 OSC2
XTL Primary 1 1 0 0 0 x OSC2
HS Primary 1 1 0 0 1 x OSC2
LP Secondary 0 0 — — — — See Note 1 and 2
FRC Internal FRC 0 1 — — — — See Note 1 and 2
LPRC Internal LPRC 1 0 — — — — See Note 1 and 2
Note 1: The OSC2 pin is either usable as a general-purpose I/O pin or is completely unusable, depending on the
Primary Oscillator mode selection (FPR<3:0>).
2: Note that the OSC1 pin cannot be used as an I/O pin, even if the Secondary Oscillator or an internal clock
source is selected at all times.
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
Illegal Opcode/
Uninitialized W Register
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
19.3.1.2 Operating without FSCM and PWRT FIGURE 19-6: EXTERNAL POWER-ON
If the FSCM is disabled and the Power-up Timer RESET CIRCUIT (FOR
(PWRT) is also disabled, then the device will exit rap- SLOW VDD POWER-UP)
idly from Reset on power-up. If the clock source is VDD
FRC, LPRC, EXTRC, or EC, it will be active
immediately. D R
If the FSCM is disabled and the system clock has not R1
MCLR
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s C dsPIC30F
perspective, the device will appear to be in Reset until
a system clock is available.
Note 1: External Power-on Reset circuit is
19.3.2 BOR: PROGRAMMABLE required only if the VDD power-up slope
BROWN-OUT RESET is too slow. The diode D helps discharge
The BOR module is based on an internal voltage refer- the capacitor quickly when VDD powers
ence circuit. The main purpose of the BOR module is to down.
generate a device Reset when a brown-out condition 2: R should be suitably chosen so as to
occurs. Brown-out conditions are generally caused by make sure that the voltage drop across
glitches on the AC mains (i.e., missing portions of the R does not violate the device’s electrical
AC cycle waveform due to bad power transmission specification.
lines or voltage sags due to excessive current draw
3: R1 should be suitably chosen so as to
when a large inductive load is turned on).
limit any current flowing into MCLR from
The BOR module allows selection of one of the external capacitor C, in the event of
following voltage trip points: MCLR/VPP pin breakdown due to Elec-
• 2.6V-2.71V trostatic Discharge (ESD) or Electrical
Overstress (EOS).
• 4.1V-4.4V
• 4.58V-4.73V
Note: The BOR voltage trip points indicated here Note: Dedicated supervisory devices, such as
are nominal values provided for design the MCP1XX and MCP8XX, may also be
guidance only. used as an external Power-on Reset
circuit.
The Watchdog Timer can be “Enabled” or “Disabled” Note: If a POR or BOR occurred, the selection of
only through a Configuration bit (FWDTEN) in the the oscillator is based on the FOS<1:0>
Configuration register FWDT. and FPR<3:0> Configuration bits.
Setting FWDTEN = 1 enables the Watchdog Timer. If the clock source is an oscillator, the clock to the
The enabling is done when programming the device. device will be held off until OST times out (indicating a
By default, after chip-erase, FWDTEN bit = 1. Any stable oscillator). If PLL is used, the system clock is
device programmer capable of programming held off until LOCK = 1 (indicating that the PLL is
dsPIC30F devices allows programming of this and stable). In either case, TPOR, TLOCK and TPWRT delays
other Configuration bits. are applied.
If enabled, the WDT will increment until it overflows or If EC, FRC, LPRC or ERC oscillators are used, then a
“times out”. A WDT time-out will force a device Reset delay of TPOR (~ 10 μs) is applied. This is the smallest
(except during Sleep). To prevent a WDT time-out, the delay possible on wake-up from Sleep.
user must clear the Watchdog Timer using a CLRWDT Moreover, if LP oscillator was active during Sleep, and
instruction. LP is the oscillator used on wake-up, then the start-up
If a WDT times out during Sleep, the device will wake- delay will be equal to TPOR. PWRT delay and OST
up. The WDTO bit in the RCON register will be cleared timer delay are not applied. In order to have the small-
to indicate a wake-up resulting from a WDT time-out. est possible start-up delay when waking up from Sleep,
Setting FWDTEN = 0 allows user software to enable/ one of these faster wake-up options should be selected
disable the Watchdog Timer via the SWDTEN before entering Sleep.
(RCON<5>) control bit. Any interrupt that is individually enabled (using the cor-
responding IE bit) and meets the prevailing priority
19.5 Power-Saving Modes level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR.
There are two power-saving states that can be entered
The Sleep status bit in RCON register is set upon
through the execution of a special instruction, PWRSAV.
wake-up.
These are: Sleep and Idle.
Note: In spite of various delays applied (TPOR,
The format of the PWRSAV instruction is as follows: TLOCK and TPWRT), the crystal oscillator
PWRSAV <parameter>, where ‘parameter’ defines (and PLL) may not be active at the end of
Idle or Sleep mode. the time-out (e.g., for low-frequency crys-
tals. In such cases), if FSCM is enabled,
19.5.1 SLEEP MODE then the device will detect this as a clock
In Sleep mode, the clock to the CPU and peripherals is failure and process the clock failure trap,
shutdown. If an on-chip oscillator is being used, it is the FRC oscillator will be enabled, and the
shutdown. user will have to re-enable the crystal
oscillator. If FSCM is not enabled, then the
The fail-safe clock monitor is not functional during device will simply suspend execution of
Sleep, since there is no clock to monitor. However, code until the clock is stable, and will
LPRC clock remains active if WDT is operational during remain in Sleep until the oscillator clock
Sleep. has started.
The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset
OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 TUN0 NOSC<1:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits
Legend: — = unimplemented bit
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F2010
DS70118J-page 133
dsPIC30F2010
NOTES:
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
VDD
Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464Ω
CL = 50 pF for all pins except OSC2
VSS 5 pF for OSC2 output
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS40 OS41
Param
Characteristic Min Typ(1) Max Units Conditions
No.
OS61 x4 PLL — 0.251 0.413 % -40°C ≤TA ≤+85°C VDD = 3.0 to 3.6V
— 0.251 0.413 % -40°C ≤TA ≤+125°C VDD = 3.0 to 3.6V
— 0.256 0.47 % -40°C ≤TA ≤+85°C VDD = 4.5 to 5.5V
— 0.256 0.47 % -40°C ≤TA ≤+125°C VDD = 4.5 to 5.5V
x8 PLL — 0.355 0.584 % -40°C ≤TA ≤+85°C VDD = 3.0 to 3.6V
— 0.355 0.584 % -40°C ≤TA ≤+125°C VDD = 3.0 to 3.6V
— 0.362 0.664 % -40°C ≤TA ≤+85°C VDD = 4.5 to 5.5V
— 0.362 0.664 % -40°C ≤TA ≤+125°C VDD = 4.5 to 5.5V
x16 PLL — 0.67 0.92 % -40°C ≤TA ≤+85°C VDD = 3.0 to 3.6V
— 0.632 0.956 % -40°C ≤TA ≤+85°C VDD = 4.5 to 5.5V
— 0.632 0.956 % -40°C ≤TA ≤+125°C VDD = 4.5 to 5.5V
Note 1: These parameters are characterized but not tested in manufacturing.
I/O Pin
(Input)
DI35
DI40
VDD SY12
MCLR
Internal SY10
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM Note: Refer to Figure 22-2 for load conditions.
Delay
TABLE 22-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C
SY11 TPWRT Power-up Timer Period 2 4 6 ms -40°C to +85°C, VDD = 5V
8 16 24 User programmable
32 64 96
SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C
SY13 TIOZ I/O high-impedance from MCLR — 0.8 1.0 μs —
Low or Watchdog Timer Reset
SY20 TWDT1 Watchdog Timer Time-out Period 0.6 2.0 3.4 ms VDD = 2.5V
TWDT2 (No Prescaler) 0.8 2.0 3.2 ms VDD = 3.3V, ±10%
TWDT3 1.0 2.0 3.0 ms VDD = 5V, ±10%
SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μs VDD ≤VBOR (D034)
SY30 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
3: Refer to Figure 22-1 and Table 22-10 for BOR.
VBGAP
0V
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRX
QEB
TQ10 TQ11
TQ15 TQ20
POSCNT
ICX
IC10 IC11
IC15
OCx
(Output Compare
or PWM Mode) OC11 OC10
OC20
OCFA/OCFB
OC15
OCx
MP30
FLTA/B
MP20
PWMx
MP11 MP10
PWMx
TQ36
QEA
(input)
TQ31 TQ30
TQ35
QEB
(input) TQ41 TQ40
TQ31 TQ30
TQ35
QEB
Internal
QEA
(input)
QEB
(input)
Ungated
Index TQ50
TQ51
Index Internal
TQ55
Position Counter
Reset
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SCKX
(CKP = 1)
SP35
SP20 SP21
SP40 SP30,SP31
SP41
SSX
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP72 SP73
SP35
SP30,SP31 SP51
SP41
SP40
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP72 SP73
SP52
SP30,SP31 SP51
SDIX
MSb IN BIT14 - - - -1 LSb IN
SP41
SP40
SCL
IM31 IM34
IM30 IM33
SDA
Start Stop
Condition Condition
SDA
Out
SCL
IS31 IS34
IS30 IS33
SDA
Start Stop
Condition Condition
SDA
Out
AD50
ADCLK
Instruction
Execution SET SAMP CLEAR SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 7 8 5 6 7 8
AD50
ADCLK
Instruction
Execution SET ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
2 – Sampling starts after discharge period. TSAMP is described 6 – One TAD for end of conversion.
in Section 17. “10-bit A/D Converter” (DS70064) of the
”dsPIC30F Family Reference Manual” (DS70046). 7 – Begin conversion of next channel
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Updated the maximum value for parameter DI19 and the minimum value for
parameter DI29 in the I/O Pin Input Specifications (see Table 22-8).
Removed parameter D136 and updated the minimum, typical, maximum, and
conditions for parameters D122 and D134 in the Program and EEPROM
specifications (see Table 22-11).
Section 23.0 “Packaging All package drawings have been updated.
Information”
“Product Identification System” Added the “MM” package definition.
From: Name
Company
Address
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Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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d s P I C 3 0 F 2 0 1 0 AT- 2 0 E / S O - E S
Custom ID (3 digits) or
Trademark Engineering Sample (ES)
Architecture
Package
MM = QFN-S
Flash SP = SPDIP
SO = SOIC
S = Die (Waffle Pack)
Memory Size in Bytes
W = Die (Wafers)
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K Temperature
5 = 49K to 96K I = Industrial -40°C to +85°C
6 = 97K to 192K E = Extended High Temp -40°C to +125°C
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID T = Tape and Reel
Example:
dsPIC30F2010AT-20E/SO = 20 MIPS, Extended temp., SOIC package, Rev. A
08/04/10