I.
INTRODUCTION
A Design Procedure for
the Phase-Controlled
Para1le1- Loaded Resonant
Inverter
ROGER J. KING, Member, IEEE
University of lbledo
High-frequency-link power conversion and distribution based
on a resonant inverter has been recently proposed. The evolution
of several topologies is reviewed, a simple approximate design
procedure is developed for the phase-controlled parallel-loaded
resonant invertefi This design procedure seeks to ensure the
expected benefits of resonant conversion and is veflied by data
from a laboratory 2500 VA, 20 kHz converter. Short-circuit
transienl behavior and fault survival are also briefly addressed.
Manuscript received August 23,1988; revised December 2,1988.
IEEE Log No. 28652
This work was supported by NASA under Grant NAG3-708.
Author’s address: Dep’t. of Electrical Engineering, University of
lbledo, 2801 W. Bancrofi St., Toledo, OH 43606.
$1.00 @ 1989 IEEE
0018-9251/89/V700-0497
IEEE ‘IRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989
Since 1982, there has been considerable interest
in several resonant-inverter topologies which provide
a nearly sinusoidal output voltage [l-71. These are
often introduced as variants of the Mapham inverter
[SI. Resonant inverters have been proposed as the
basis of a high-frequency ac distribution system for
NASA’s Space Station [13], but would also be useful
for ac link power conversion [l],VLF transmitters
or as a general purpose ac source for component
testing. Several of the topologies found in the literature
are reviewed briefly before focusing on the specific
arrangement here referred to as the “phasecontrolled
parallel-loaded” resonant inverter (PC-PRI).
The main purpose here is the determination of
a design procedure for this resonant inverter which
keeps in view the expected benefits of resonant
operation. A simple phasor analysis is introduced as
a useful approximation for design purposes. The load is
considered to be a linear impedance (or an ac current
sink).
A. Derivation of the PC-PRI Topology
Fig. l(a) illustrates a switching structure often
called the voltage-sourced inverter PSI) due to
the “stiff” dc voltage source. When the VSI is
interfaced to the load with the resonant tank also
shown in Fig. l(a), the “parallel-loaded” resonant
inverter (PRI) results. If the resonant tank of Fig.
l(a) is driven below its resonant frequency, C, can
be selected to zero the output reactance xo and
thereby provide perfect load regulation (in the steady
state). An inductor accomplishes the same result
if above-resonance operation is selected. The PRI
provides a low-distortion sinusoidal output voltage for
any switching frequency greater than approximately
60 percent of the resonant frequency. (It is assumed
here that a simple square-wave gate drive is to be
used.) However, the PRI suffers from the lack of line
regulation and protection against load short-circuit.
More complex gating patterns could be used to solve
these problems, but this would negate one of the
chief advantages of a resonant inverter: a predictable
sequence of current commutations in the inverter with
at least some made “easy” by the resonant tank. The
PRI can be operated with the intent of guaranteeing
natural turn-off of thyristor switches having a specified
turn-off time, or merely providing current zeroes in the
correct sequence for gatecontrolled switching devices.
The “modified parallel-loaded” resonant inverter
of Fig. 1@) is better known as the Mapham inverter
[SI. It is found [7, 91 that the input/output performance
of this topology is very similar to that of the PRI
with the exception of a tradeoff of turn-off time
versus blocking voltage. The Mapham inverter
provides an increase in turn-off time at the cost of
497
 Fig. l(a). Voltage-sourced inverter with parallel-loaded resonant
tank. Fundamental-frequency output reactance no nulled by proper
choice of c,.
Fig. l(b). Modified voltage-sourced inverter with parallel-loaded
resonant tank (Mapham inverter). Load regulation improved by
proper selection of C,.
an increase in switch blocking voltage. For the case
of thyristor switches at high frequency, the Mapham
inverter provides a high utilization factor [7,9].
Howexr, for most switches other than thyristors, the
increased blocking voltage of this topology is quite
unpalatable. Gatecontrolled switches need not be
provided with lengthy turn+ff recovery times; ongoing
improvement in switching devices such as IciTs, BJTs,
and metal-oxide-semiconductor fieldeffect transistors
(MOSFETs) suggests that thyristors wiU be displaced
even at fairly high power levels. Simulation shows
[lo] that C, in Fig. l@)can be selected to greatly
improve the load voltage regulation, nulling the output
reactance in the vicinity of a specific loading condition.
The use of C, in this manner precludes using it as
short-circuit protection for the inverter, however.
The Mapham inverter is not considered further here.
If thyristors were used as the switching devices, the
Mapham inverter would be indicated, in which case
performance similar in many respects to that of the
PRI could be expected.
Fig. 2 indicates two phasecontrol approaches
which have appeared in the literature. Fig. 2(a) shows
two series-connected VSIs with a single resonant
tank, driven either at resonance [3], or off-resonance
[14]. This approach has the advantage of balanced
load currents on the two VSIs,and #veri proper
design, predictable commutation sequences in the
inverters. These commutation sequences are not
necessarily the same for both inverters, however.
Fig. 2@) shows a phase control approach in which
the individual inverters together with their resonant
tanks are series connected. As indicated in [6], the
inverter currents can become quite unbalanced in
this resonant converter, however, the commutation
sequences for both VSIs can be the same if properly
designed. This topology, or a similar one based on the
Mapham inverter, has been p r o p d E131 for use in
a high-frequency ac distribution system. The circuit
of Fig. 2@) is the one referred to in the remainder
of this paper as the PC-PRI. Fig. 3 shows a simple
4% IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989
Fig. ?(a). Phaae control using single monant tank.
Fig. qb). Phase control using two resonant tanks.
;:7" {+&-I V S I n2
[-@ ]
iL = I ~ ~ I ~ I W , ~ ~ B I
Fig. 3. PC-PRI based on two half-bridge VSIs Output capacitors
C, provided for below-resonance operation. L1= L2 = L and
c, = cz = c.
implementation of the PC-PRI using two half-bridge
VSIs [6], which avoids the need for an isolation
transformer. It should be remarked that in practice
the two capacitors marked C, would be combined into
a single capacitor "1/2C,".
II. PHASOR ANALYSIS OF THE PC-PRI
A. Assumptions
The analysis presented here is valid only for the
steady state, but consequently is presented in a simple
and compact form. This is appropriate due to the
design-oriented nature of this paper. It has been well
established [6] that the capacitor voltages in Fig. 3 are
lowdistortion sinusoids (< 10 percent THD) under
most circumstances. It is here assumed that the load
is linear, drawing a sinusoidal current in response to
the converter output voltage. The load is therefore
modeled as a sinusoidal current source (sink) for the
purpose of relating key circuit variables to the load
current. m i c a 1 inverter voltage waveforms are shown
in Fig. 4. Because a linear network is being excited
by defined voltage and current sources, a phasor
analysis for the fundamental component of the network
response is appropriate.
The results obtained here could be extended to
include the case of a rectified load. There would
be some loss of accuracy, however, due to the
 From (6) it can be seen that this output reactance
t v
is inductive below resonance, but capacitive above
resonance. The output capacitors C, shown in Fig.
+ - i- 1 L
3 are selected to null this output reactance and thus
0 11 211 311 obtain perfect load regulation. Therefore, C, is chosen
according to
-v
"52 "
- v
c, = C- 1-r2 < 1.
4-4
0
,
TI
I
2n 311
. W S t
r2 '
r

If above-resonance operation is intended, output

(7)

-v inductors are used. Their values would be

1
L, = L- r > 1.
r2- 1'
large third-harmonic input current typical of most The no-load value of q~is calculated
single-phase rectifiers. As pointed out in [2], this leads
to a substantially distorted ac voltage waveform under ,. 2VCOS$
some circumstances. VL = -LOo (V rms). (9)
1-r2

B. Phasor Analysis If the output reactance is nulled, then the output

voltage under any loading condition is given by (9).
The voltages vsl and vs2 of Fig. 4 can be written in Over-current and short-circuit protection would
Fourier-series form: then depend on the ability of the controller to shift
the control angle $ to precisely XI", reducing the
4vs Oo 1
vsl(t>= - - sin(nw,t
r n
+ n$) open-circuit output voltage to zero. It would probably
n =I be wise to use an output reactor somewhat smaller
than that given by (7) or (8) to allow for imperfection
and
in the controller. It is suggested that the gating phase
angle of each inverter be modulated with respect to the
zero-angle reference as shown in Fig. 4. This keeps the
where n is odd. In phasor notation the fundamental phase of the load voltage independent of the regulating
action as shown by (9) and thus prevents dc-side ripple
components of these voltages become
from phase-modulating the ac output.
4vs The phasor inductor currents and capacitor
+sl = -el+
'
= VCCOS$ + jVsin$; (V rms)
voltages are now calculated using (2) and the following
fir
(2) expression for iL:
Vs2 = -e
4Vs _ '
= Vccos$-jVsin$;
I+ (V rms)
fir
where
4vs
VE-. The following results are obtained
Jzr
It is convenient to define the following:
4
sin$ + ZL-cos0
1-9
Resonant Frequency: wo E I (3)
m V r
+ I L -1-r2
Characteristic Impedance: 20E (4)
+j [ cos$
l
sine
l

DrivingResonant Frequency Ratio: r = -.WO

ws
(5)
1
For operation below resonance r < 1; for operation
above resonance r > 1. The fundamental-frequency
+j [
V-sin$-ILZo---cose
1-r2 1-l r2 l
. (12)

output reactance with C, omitted would be Similar expressions are obtained for f 2 and 9 2 .
r The magnitudes of the inductor currents
Xom = j2-Zo. and capacitor voltages yield useful design rating
1- r2

KING: PHASE-CONTROLLED PARALLEL-LOADED RESONANT INVERTER 499

information:
The magnitude of i 2 is given by an expression the
same as (13) with the exception that the argument of
the sine term is (-$ - e). The magnitude of 9 2 is given
by an expression the same as (14) with the exception
+
that the argument of the sine term is (I$ 8). It can be
noted that each of the expressions (13) (14) is of the
form
z2 = f2xy sin($ fe) y2. + (16)
The angles $J and 8 in (16) are the inverter control
angle and the load phase angle, respectively. The
control angle $ ranges from 0' to 90" if operation
down to zero output voltage is required. With a passive
load, 8 lies between -90" and +W. (It is possible
to design for more restrictive limits on 8; however, a
load fault would probably result in a very reactive fault
current.) For the purposes of determining worst-case
design ratings on components, no special limits on $ or
0 are assumed; therefore
-issin($fe)~+i
and, referring to (16),
1x1- lYl 5 14 5 1x1+ IYI.
It is here assumed that 1x1 2 ly(. Applying
(14) gives the following results:
The magnitudes of f 2 and 9 2 are also bounded by
the inequalities (19) and (20). The results of (19),
(20) represent the worst case for these variables
and can therefore be used for component sizing
purposes. However, these worst cases do not occur
simultaneously, so (19), (20) cannot be used for
inverter loss estimation.
The inverter complex-volt-ampere loadings are
found using (2) and (11):
500 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989
and
S2 = Vs2I; = P2 + JQ2.
A , .
(22)
The results of evaluating (21) and (22) are entered in
n b l e I. The real parts of (21) and (22) represent the
real-power loadings on the two inverters; the imaginary
parts represent the reactive loadings. It can be noted
that the inverters have unbalanced loadings in general.
The results obtained thus far are valid for operation
both above and below resonance. However, Fig. 3
is appropriate only for below-resonance operation
and a subtlety in interpretation of (9)-(22) should be
pointed out. Examination of the load voltage V L (9)
shows that it reverses sign above resonance due to
the term (1 - r2). This implies that a current source
which represents energy delivered to the load should
also have a reversed sign. Also, the appropriate output
reactance is now that of an inductor. If the results
of (9)-(22) are to be used for the above-resonance
case, it is suggested that the following changes would
clarify these results: 1) reverse the sign convention
for iL in Fig. 3, and 2) reverse the sign of all terms
containing ZL,such that Ir, continues to represent the
positive-valued magnitude of the load current. These
changes are reflected in the entries of Bble I, which
summarizes the results of this phasor analysis.
Ill. DESIGN PROCEDURE
A. Benefits of Resonant Switching
The design procedure developed here is based on
the expected performance attributes of this resonant
inverter. As implied by the previous section, this
PC-PRI is to appear to its load as a stiff ac voltage
source. This raises the question of determining the
maximum loadcurrent rating. The design procedure
proposed here determines this current rating not in
terms of device ratings, but as that load current for
which the expected benefits of resonant switching
disappear.
Two salient benefits are usually attributed to
resonant switching: lowering of electromagnetic
interference (EMI) through the inherent filtering
provided by the resonant tank and improvement of
the switching device i - v locus to lower switching
losses. It should be noted that these benefits are
obtained at the price of increased switch conduction
losses due to the multiplied switch current and/or
voltage ratings. If slow switches are used, this is a
good trade-off. However, if very fast switches are
available, the nonresonant approach provides lower
losses and a simpler topology as well. Especially
if the PC-PRI considered here is used to supply a
rectifier, the design should be based on the assumption
that relatively slow switching devices are being used
(otherwise a simpler d c d c converter would suffice).
The switchcommutation conditions are therefore
 WLE I occur naturally. Examples include the provision
Results Of Phasor Analysis Of Phase-Controlled Resonant Inverter
of a current zero for turn-off of a thyristor or the
Description Result
provision of a voltage zero for the reverse recovery
of a slow diode. Therefore it is important to know
Inverter 1 whether the inverter current leads or lags the inverter
Output Voltage
voltage because this determines the snubber design
Inverter 2 as well as the possibility of natural commutation.
Output Voltage & 2 = V L - + = - L4vs
-+(Vms) If the inverter output current leads the voltage, the
fir inverter commutation sequence is (referring to the
Load Voltage VL = *low resonance)
I-r left-hand side of Fig. 3) Ql-Dl-Q2-D2-Q1.. . . The
VL = % (above resonance) Dl-Q2 and D2-Q1 commutations are “hard”, requiring
Inductor Current a current snubber to control the reverse recovery
Magnitude (1 or 2)
of the diode as the transistor is turned on. On the
Capacitor Voltage other hand, a lagging inverter output current results
Magnitude (1 or 2) in the commutation sequence Dl-Ql-D2-Q2-D1.. ..
Output Reactor In this c a s the Ql-D2 and Q2-D1 commutations are
Voltage Magnitude characterized by large d v / d t and require a voltage
snubber. The leading currentcommutation pattern
Inverter 1
VIL is useful for natural turn-off of silicon controlled
Real Power Output Pi = cos(+ - 0 ) (below resonance)
rectifiers (SCRS). The lagging current-commutation
P I = %cog+ - e) (above resonance) pattern permits lossless snubbers if the switching
Inverter 2 devices are capable of gatecontrolled turn-off. It is
VIL
Real Power Output PZ = -cos(+ + 0 ) (below resonance) assumed that one of these commutation patterns is
P2 =
%L2
- cos(+ + 8 ) (above resonance)
selected together with a snubber network optimized for
r2 - I the switching devices being used. However, the issue
Inverter 1 of main importance is the possibility of reversal of the
Reactive Power expected commutation sequence. A shift from lagging
output
to leading current, or vice versa, could be disastrous,
resohance) causing commutation failure or excessively high
Qi = switching and snubbing losses. Therefore, the inverter
V2 r VI,
+- -+ -sin(+ - 8) (above operating conditions are to be bounded accordingly.
Znr2-1 9 - 1
resoiiance) Examining the inverter reactive power outputs in
Inverter 2 lhble I reveals that below-resonance operation at no
Reactive Power load is characterized by negative reactive power (the
output tank appears capacitive); above-resonance operation
resonance) at no load is characterized by positive reactive power
(the tank appears inductive). As the magnitude of
the load current (IL) is increased, there comes a
point (depending on q5 and e) at which the sign of
resonance)
the reactive power reverses. A condition on the load
current magnitude such that no reversal of reactive
power flow is possible would be
examined to determine the load-current rating of the
converter. V(min)r 4 Vs(min)r
IZL(< -= - (231
zo Jzw zo *

Note that (23) must apply at the minimum expected

B. Switch-Commutation Conditions dc-side voltage. It is suggested that output-current
limiting be provided in accordance with (23), and that
The results summarized in ’Itible I show that ZObe selected using this inequality.
the inverter output voltage is independent of the
load and the resonant tank impedance; thus there is
ideally perfect load regulation. To obtain guidance C. Design Procedure
in choosing an appropriate characteristic impedance
At this point it is useful to define a “turn-down
for the resonance tank, the expressions for real and
ratio”, the ratio of the maximum dc-supply voltage to
reactive loading on the inverters are next examined
the minimum for which the output regulation is to be
to determine the switch-commutation sequence. The
maintained.
underdamped resonant tank is used to make at least
some of the commutations of the switching devices

KING: PHASE-CONTROLLED PARALLEL-LOADED RESONANT INVERTER 501

 Using (23) as a design equation determines A - TANK CAPACITOR
0 - TANK INDUCTOR
the component ratings in terms of the chosen 0 - COMP. REACTOR
switchinghesonance frequency ratio (r). Setting 0 -UNIT INVERTER

VA R A T I N G
V(min)r
20 =- 9
IL(")

bounds the inverter output currents,

and bounds the capacitor voltages

The switching-frequency volt-ampere rating of an

inductor is
VA(ind) = lf12rZo. (28) .5 1.0 1.5

r =WS
Substituting (9) and (26) into (28) gives the inductor WO

rating in terms of the converter load rating, Fig. 5. Fundamental-frequenq rms VA ratings of key components
normalized with respect to load VA plotted versus frequency ratio.
%"own ratio KTD of 1.0 assumed.
(29)
given converter load-volt-ampere rating. A turndown
Similar results are obtained for the tank capacitor VA ratio KTD= 1 is assumed for this figure.
ratings The component VA ratings indicated by Fig.
VA(cap) = lv12-r (30) 5 clearly suggest that the choice of r be as low as
ZO possible. The Mapham inverter (which is similar, but
or not the same) is traditionally operated with r Z 0.65,

VA(cap) = 1 ( r 2 -k Km)2
2(1- r2)
1 V&,(max).
chosen to give a low-distortion sine-wave output
(31) and long SCR turn-off times [7, SI. It appears that a
tradeoff between distortion and component VA ratings
For the output reactor can also be made for the PC-PRI. For this purpose,
the open-circuit harmonic content in the load voltage is
computed

or
VA(x) = r2VLIL(max). (33) for n = 1,3,5,... . The subscript n represents the
The inverter fundamental-frequency VA rating is (for harmonic number. Therefore, the open-circuit output
each inverter) - is
voltage
2 v cos nf$
LOO.
VA(inv) = V(max)lil = n(1- ( n r ) 2 )

= ;Km(l+ Km)VLZL(max). (34) The total harmonic distortion in the open-circuit

It remains to choose the switchinghsonant
frequency ratio r. Examination of (34) shows that the
required inverter ratings are independent of r for a
given output requirement, thus the choice of above-
or below-resonance operation does not affect the
basic utilization of the inverters. However, (25)-(33)
show that the choice of r has a dramatic effect on the
tank-component ratings for a given output VA product.
To aid in making an appropriate choice, Fig. 5 shows
component VA ratings plotted as a function of r for a
output voltage is calculated using (36) and considering
only the 3rd, 5th, and 7th harmonics. This result is
plotted in Fig. 6 using the control angle f$ as the
parameter of the graph.
The final choice of frequency ratio r is a judgment
call of the designer. The factors influencing this choice
include the following: 1) the total component VA
ratings required translate into volume, weight, and
cost, 2) switch turn-off time is probably not a major
factor if the proposed topology is used instead of the
Mapham topology, and 3) the sensitivity of the load to

502 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989

r = W.
W.
Fig. 6. B t a l harmonic distortion in open-circuit output voltage
versus frequency ratio. Control angle q5 is parameter.
TOTAL COMPONENT VA RATINGS
t
Y
K,,=
K,,=
. .
.5 1.0
r nWS
W.
Fig. 7. Total fundamental-frequenq component VA ratings
required to build PC-PRI based on proposed design procedure.
Design turndown ratio KTD is parameter of graph.
the harmonic content of the system voltage must be
evaluated.
To aid in making this tradeoff, the component VA
rating information of Fig. 5 is summarized in Fig. 7.
The total VA ratings of Fig. 7 include those of the two
tank inductors, the two tank capacitors, and the output
reactor. Only the fundamental-frequency component is
considered in these ratings; however, a check at r = 0.5
reveals that the total rms inductor current is less than
18 percent higher than the fundamental component
only. At r = 0.6 the discrepancy in the rms current
KING PHASE-CONTROLLED PARALLEL-LOADED RESONANT INVERTER
M L E I1
Suggested Phase-Controlled Resonant Inverter Design Procedure
Given: Vs(max), Vs(min), ws, rms load voltage and current Vt
and I t
1. Choose r . (Perhaps 0.6-0.7).
2 Find VL at Vs(min) and cos4 = 1.
v L =2V(min)
-- - 8Vs(min)
1 - r2 J Z s ( 1 - r2)
3. Provide output transformer to scale VL to V;, find IL from
It.
This determines L1, C1, L2, and C2.
5. If below resonance, series combination of output capacitors
If above resonance, series combination of output inductors
2
2Lx = L1-
r2-1'
6. Current limiting should be supplied by controller to limit IL
1.5 to value used above.
rating is less than 5 percent. The results of Fig. 7 are
1.0 therefore reasonable for component rating purposes.
The inverter VA ratings are each related to the load
VA rating, as shown by (M), and independent of the
choice of r.
The suggested design procedure is summarized
in n b l e 11. A value of r between 0.6 and 0.7 is a
reasonable choice if turn-off of the controlled switch
is to be favored. If slow antiparallel diodes must be
used, r > 1 can be used at the cost of a much higher
tank VA rating. The VA rating is given at the switching
frequency: it is possible that a higher switching
frequency is permissable with above-resonance
1.5 operation thereby offsetting the size increase in the
tank components. n b l e I1 provides key component
values; the rating information is provided by (26), (27),
and (34). It is interesting to note that the required VA
ratings increase with the turndown ratio, but at a rate
of less than K&. This is due to the current limiting
assumed for IL.
IV. EXPERIMENTAL VERI FlCATlON
A. Design of Laboratory Converter
A laboratory model of the PC-PRIwas constructed
and data were taken to verify this proposed analysis
and design procedure. The converter was designed
for a dc input voltage of 100 V minimum, using the
topology of Fig. 3 and a load rating of 2500 VA at 20
503
kHz. The initial design used four paralleled MOSFETs ‘CABLE 111
(Motorola MTh4 40”) for each switch, together with Design Parameters and Component Ratings, 2.5 W A , 20 kHz
Inverter
their body-drain diodes. Below-resonance operation
with r E 0.7 was employed. Substantial d i / d t snubbing Value or Rating
was required to control the slow diode-to-MOSFET Value or Rating (As Constructed
commutation. The large d i / d t inductors used (about Item (As Designed) and Operated)
1.1 pH total) rendered the MOSFETs quite vulnerable Input Voltage Range 100 V-150 V 100 v-120 v
to overvoltage in the event of even a single reversed ( K m = 1.51
commutation. It was found to be impractical to Vs(min) 50 V dc 50 V dc
provide a voltage clamp of sufficiently low impedance
to permit the MOSFET switches to interrupt current V(min) 45 v rms 43 v rms
(reduced to 43 V to
under gate control even on a transient basis. (The allow
interrupted current could easily exceed 100 A; the for losses)
energy stored in the d i / d t inductor would have been
r 0.7 0.65
transferred to the clamping circuit.)
The foregoing issue is of no concern in the ws (2a) 20 kHz (2a) 18.4 kHz
steady state because the design procedure guarantees WO (2s) 28.6 kHz (279 28.4 kHz
freedom from commutation reversals; however,
Load Voltage VL 169 V rms 156 V rms
the transient state and load-fault performance
were also investigated. It was found that even this Load Current IL(max) 14.8 A rms 14.8 A rms
conservative design philosophy was inadequate to 20 2.m 1.960
prevent commutation reversal in the event of a load
Dnk Inductor L1, L2 11 pH, 72 A, 101 V 11 p H
short-circuit. Two possible solutions were identified.
Dnk Capacitor Cl, C2 2.78 pH, 59 A, 168 V 2.86 pF
1) Use fast-switching devices (both transistors and Output Capacitors
diodes) and minimal snubbing. (both taken together)
2) Add to the controller current-sensing and logic to In c, 1.45 pF, 15 A, 81 V 1.54 pF
modify the gating patterns during the transient such %tal Component VA 35.7 W A
that a “reversed” commutation is never attempted Inverter Switch 51 A rms S 33 A avg
[151. 150 V peak +snubber
overshoot
Solution 1 is simple and solves the problem
unconditionally, provided there is enough thermal
capacity to ride through a transient overcurrent voltage was reduced by approximately 4 percent in
as the current limiter reacts. This does not seem accordance with the anticipated MOSFET conduction
difficult to arrange. However, this solution abandons losses. The resulting design provides line regulation for
a prime benefit of the resonant inverter: the ability the range 100 V-150 V and requires a total component
to efficiently utilize slow-switching devices. The rating of 36 KVA. The four inverter switches each
implementation of solution 2 is potentially complex. handle 51 A (rms) with a peak voltage of 150 V plus
It requires that the converter jump phase during a snubber overshoot. The ratings of Table I11 represent
transient, and, if improperly designed, might allow a maximum component stress levels at high line and
transient to latch-up the inverter in a limit-cycle type of rated load current, but do not occur simultaneously
response. Solution 2 does preserve the basic advantage for every component. They cannot be used for loss
of resonant power conversion: efficient switching at or efficiency estimation, therefore. A loss-estimation
high frequencies using slow switches. Clearly, solution procedure can be found in [ll].
2 is mandatory for use with thyristors or other slow
high-power switches.
For the purpose of this experimental work, B. Experimental Results: Steady State
solution 1 was implemented by providing fast-recovery
antiparallel diodes (Unitrode UES 2606) and blocking The inverter as actually constructed deviated
the MOSFET bodydrain diodes with Schottky diodes. somewhat from that designed, primarily due to the
No d i / d t inductors were used beyond the estimated use of the resonant tank components which were
350 nH of parasitic layout inductance. The overshoot readily available. The parameters and ratings of
voltage was controlled with a simple nonpolarized the experimental inverter as constructed are also
RC snubber (0.068 pF/1.67R). The implementation summarized in Table 111. Operation above a source
of solution 2 is left for future investigation. voltage of 120 V was not possible due to the voltage
l?ible I11 displays the results of the proposed design drops on the parasitic layout inductances and the 200
procedure. It should be noted that the effective input V ratings of the MOSFETs used.

504 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989
 ~~~
,(bora)
4.0C
3.00
2.00
1 .oo
0 00
0 00 0 50 ;.Ad ' 7,L' ' '
~~~~
I(bO%)
Fig. 8. Theoretical and measured values of normalized
tank-inductor currents (11 and 12) versus normalized load current
(IL). Control angle (4) is parameter.
0 00
0 00 0 50 100
~._.
,i
I(b0.e)
Fig. 9. Theoretical and measured values of normalized
tank-capacitor voltages (VIand V2) versus normalized load current
(IL). Control angle (4) is parameter.
Fig. 8 was generated by plotting (13), giving the
magnitudes of the two tank inductor currents. Three
different control angles ($I = 3", 45O, and 600) are used
as the parameter of this graph. Note that all currents
are normalized with respect to the design-maximum
load current of a b l e I11 (14.8 A). Experimental data
points are also indicated on Fig. 8. These were taken
using a wideband rms-responding instrument.
Fig. 9 was generated by plotting (14), giving the
magnitudes of the two tank capacit.or voltages. As
in Fig. 8, three different control angles ($I = 3 O , 45O,
and 600) are used as the parameter of this graph. All
voltages are normalized with respect to the maximum
load voltage of a b l e 111 (156 V). Experimental data
points taken with an rms-responding meter are also
indicated. The data of Figs. 8 and 9 were taken using
a resistive load bank having a slightly lagging current
(0 = -8'); this was accounted for in the application of
(1317 (14).
Figs. 8 and 9 show generally good agreement
(within 20 percent for all data points except those of
KING: PHASE-CONTROLLED PARALLEL-LOADED RESONANT INVERTER
Fig. 10. Steady state operation with load voltage VL = 73 V
(4 = 60') and load current IL = 15.5 A (1.05 IL (rated)). Upper
pair: Unit inverter 1 output voltage (50 V/div) and current (40
Ndiv). Lower pair: Unit inverter 2 output voltage (50 V/div) and
current (40 Ndiv). See 'Ihble 111.
l r
the $I = 60' curve in Fig. 8) between the measured
data and curves based on the fundamental component
only. There is, however, some discrepancy seen in
Fig. 8 in the tank current, 11, particularly at high
load current and high control angle q5 (reduced load
voltage). Fig. 10 provides an explanation of this. The
upper pair of traces in this photo is the output voltage
and current associated with inverter 1; the lower pair
corresponds to inverter 2. This photo was taken at 105
percent of rated load current with the control angle
$I = 600. It can be seen here that as the tank current
il nulls, its harmonic content becomes high relative to
its fundamental, resulting in an rms value somewhat
higher than expected. This phenomenon does not
affect the accuracy of the inductor design criterion
which is based on the highest expected current.
However, Fig. 10 also indicates that the precise
location of the inverter current zero-crossings cannot
150 be found based only on the fundamental component.
The uncertainty in the precise zerocrossing time is not
a concern if gate-turn-off switches are used and they
are capable of interrupting a small forward current,
It was found experimentally that the design criteria
presented here never resulted in any substantial
reversal of the expected commutation conditions.
These design criteria are therefore deemed an
appropriate simplification for use with gate-turn-off
switches; design with thyristors will require an analysis
providing a more-accurate zero-crossing time. In any
event, a thyristor design should probably be based
on the Maphamderived topology which is capable of
providing an extended turn-off time to its switches [9].
Fig. 11 further illustrates the inverter switch
commutation conditions for a variety of loads. Each of
these photos was taken at IL = 15 A, slightly above the
design maximum value of 14.8 A. From top to bottom
in Fig. 11, the photos correspond to load voltages of
150 V, 73 V, and 0 V. In each photo the upper pair
of traces corresponds to inverter 2 switch voltage
(50 V/div) and current (50 Ndiv); the lower pair
corresponds to inverter 1. Fig. 11 shows the worst-case
nature of these design criteria-the commutation
limit is reached under some, but not all, maximum
loadcurrent conditions. It also shows the unbalanced
loading on the two inverters under some conditions.
505

(4
Fig. 11. Switch voltage (50 V/div) and current (50 Ndiv) with unit
inverter 2 on top and unit inverter 1 at bottom. (a) VL = 150 V
and IL = 15 A. (b) VL = 73 V and IL = 15 A. (c) VL = 0 V and
IL = 15 A.
(This is the reason that the total inverter design VA
must be twice the load rating.)
C. Experimental Results: Transient
Although this design procedure is based on a
steady-state analysis and is primarily concerned with
the steady-state commutation conditions, a discerning
designer will want to know what happens under
transient conditions such as load switching or load
short-circuit. Fig. 12 displays the result of applying
and removing a short-circuit at the output terminals of
the PC-PRI. Fig. 12(a) shows the load current (upper)
and load voltage (lower). It can be seen that a fairly
sluggish current-limiter has been provided, the fault
current leveling off after about 6 cycles. The voltage
transient after removal of the short circuit is due to the
parasitic layout inductance. No output transformer was
used for this test. Fig. 12(b) shows the commutation
conditions for inverter 1 after the inception of the
fault. The inverter output current (upper) is shown
together with the lower switch (Q2D2) voltage
(lower). Referring to Fig. 3, it can be Seen that in the
second cycle of the fault Q2 is interrupting 40 A, an
amount of current having grim implications should any
significant commutating inductance be added to this
circuit. It was this problem, in fact, that led to the use
of fast antiparallel diodes in place of the MOSFET
body-drain diodes. (Voltage snubbers could be added
along with the commutating inductors, but a voltage
506 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 25, NO. 4 JULY 1989
(b)
Fig. 12. Application and removal of short-circuit at PC-PRI output
terminals. (a) Upper: load Current i~ (100 Ndiv). LoweI: load
voltage VL (200 V/div). (b) Upper: unit inverter 1 output current i l
(40 Ndiv). Lower: inverter 1 lower switch voltage (50 Ndiv).
clamp of sufficiently low transient impedance to pick
up the switched current without excessive overshoot
was difficult to implement.) It can also be seen at
the right-hand side of Fig. 12(b) that the normal
commutation sequence is restored by the fourth cycle
of the fault.
The results of this short-circuit test show that if
inverter survival of a load-fault is important, provision
for possible reversed commutation sequences must
be designed into either the controller or the power
circuit. Verification of a proposed solution could be
conveniently made using simulation techniques, or
by the experimental technique used to obtain the
photos of Fig. 12. An electronic shorting switch was
repetitively opened and closed using a timing reference
derived from the controller. It was found that the
timing of the fault within a cycle as well as the fault
duration did make some difference in the observed
results.
V. CONCLUSION
The derivations of several resonant inverters
having a low-distortion sinusoidal-voltage output
were reviewed. The PC-PRI was identified as being
suitable for use with gate-turn-off switches not needing
lengthy turn-off periods to do thyristors. Based on the
intent of lowdistortion operation, a phasor analysis
was proposed as a useful design tool. A predictable
commutation sequence for all switches was considered
important to the preservation of the advantages
normally associated with resonant conversion. A
simple design procedure which ensures this benefit
was proposed and verified using a 2.5 KVA, 20 kHz
experimental inverter. The design procedure also
resulted in predictable worst-case ratings for each
component of the resonant tank and the inverter
switches. For a given load VA requirement, a tradeoff
was made between harmonic distortion and tank VA
rating. Below-resonance operation was found to result
in a significantly lower tank VA requirement. The
experimental results also showed that under transient
conditions such as load short-circuit, a reversal of
the expected commutation sequence is possible. This
should be accounted for in the design of the power
circuit, or prevented by the design of the controller.
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Roger J. King (S’72-M’75) was born in Toledo, Ohio, on September 28, 1950. He
received the B.S.E.E., M.S.E.E., and Ph.D. degrees from the University of Toledo,
Ohio, in 1972, 19775, and 1983, respectively.
Prior to returning to graduate school in 1978, he spent several years designing
analog instrumentation. He is presently Associate Professor of Electriccl
Engineering at the University of Toledo, specializing in power electronics
teaching and research. His research interests include resonant converters, and
transient-modeling techniques for switching converters.
Dr. King is a registered Professional Engineer in the State of Ohio, and is a
member of Eta Kappa Nu, %U Beta Pi, and Sigma Xi.

KING: PHASE-CONTROLLED PARALLEL-LOADED RESONANT INVERTER 507