Lecture 1

Introduction of Digital Design & VHDL

Eng.Emad Samuel

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Introduction:
Digital Design:
What is design?
Given problem spec, solve it with available components
While meeting constraints (size, cost, power)
What is Digital design?
Choose digital logic components to perform specified control,
data manipulation, or communication function and their
interconnection.
Which logic components to choose?
Many implementation technologies (fixed-function components,
programmable devices, individual transistors on a chip, etc.)
Design optimized/transformed to meet design constraints
Digital Design Consists of:

 Combinatorial circuits: are generalizations of gates.

In general, such a circuit has m inputs and n outputs .As Logic
gates,Decoders,Multiplixers,Encoders,Comparators,etc.
 Sequential Circuits: are generalizations of flip-flops.
In general, we define a sequential circuit as a circuit with m
inputs, n outputs, and a distinguished clock input. As Latches,
Flip Flops,Counters,Shift registers,etc.

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Design Levels:

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VHDL:
 VHDL: is a language used for describing digital hardware (it is a
hardware description language)
 VHDL is an acronym for:-
 VHSIC (Very High Speed Integrated Circuit)
 Hardware
 Description
 Language
 Was invented in 1987, was modified in 1993.
Why VHDL?
 VHDL Provides greater flexibility.
 You can reuse early design components.
 You can move your design between multiple vendors and tools.
 VHDL permits you to take advantages of mature software design
practices.
 You can quickly capture your design intent.
 You can more easily manage your design data.

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VHDL Concepts:
Entity:-
 Entity declaration describes the Component interface (inputs &
outputs).

 One entity can have much architecture.

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Architecture:-
 Describes how to implement the component.
It simulates what will happen inside the component (Design
functionality).

Ports:
 Ports of the interface describes the direction in which data is
flowing to/from the component.
– In: Data comes in this port and can only be read within the
entity. (Right side only)
– Out: The value of an output port can only be received from
the entity. It cannot be read. (Left side only)
– Inout: The value of a bi-directional port can be read and
received within the entity model. It can appear on both sides
of a signal assignment.
Data types:
 Bit:’0’or’1’
For one bit: - Bit ,Called Signal.
For more than one bit:-
bit_vector(□downto□) or bit_vector(□ to□), Called Bus.

For example:

If we have 4 bits, we write that: bit_vector(3 downto 0) or bit_vector(0 to 3).

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 Std_logic:

For one bit :-

Std_logic.
For more than one bit:-
Std_logic_vector(□downto□) or Std_logic_vector(□ to□).

 Signed: MSB is sign ,

If Bit ‘1’ = -ve sign, Bit ‘0’ = +ve sign
For example: 1011=-3 , 0101 = +5
 Unsigned: no signed bits.
For example: 1011=11 , 0101 = 5

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Operations:
Logical: =, /=, <, >, <=, >=
Boolean: and, or, nand, nor, xor, xnor, not.
Addition: +
Subtraction or negation: -
Multiplication by integer or real: *
Division by integer or real: /

Example:-

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