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Description Flowchart
z AS Sign of A
z BS Sign of B
z AS & A Accumulator
z AVF Overflow bit for A + B
z E Output carry for parallel adder
5 6
7 8
Description Flowchart
z Q multiplier
z B multiplicand
z A 0
z SC number of bits in multiplier
z E overflow bit for A
z Do SC times
If low-order bit of Q is 1
A ←A+B
Shift right EAQ
z Product is in AQ 11 12
13 14
Algorithm Hardware
z Do SC + 1 times
QnQn+1 = 10
AC ← AC + BR + 1
QnQn+1 = 01
AC ← AC + BR
Arithmetic shift right AC & QR
SC ← SC – 1
15 16
17 18
19 20
21 22
At end of operation,
Q quotient
A remainder
DVF divide overflow
23 24
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43
Fast 44
Slow 45
Very slow 46
Dec Arith Registers for Mult & Div Decimal Multiplication Flowchart
0456 0456
x 0123 0456
56088 + 0456
1368
0136 8 shift
0456
+ 0456
1048
0104 88 shift
+ 0456
0560
0056 088 shift
0005 6088 shift
47 48
49