Morteza H. Panah, Ph.D. P.O.

Box 2143
Santa Clara, CA 95055
408-966-9588
morypanah@ymail.com

EDUCATION
* PhD, Electrical and Computer Engineering, University of California, Davis, 06/
87
o Dissertation: Hardware Architecture, DSP Algorithm design, and simulation of a
new high speed QRNS-Based Digital System for Implementations of Digital Signal/
Image Processing functions and Digital Filters
* MS, Electrical and Computer Engineering, Wayne State University, Detroit, MI,
12/80
EXPERIENCE
Plato Networks, Santa Clara, CA 03/06 - Present
Senior ASIC Architecture, Design and Verification for the 10GBASE_T networking
* System architecture, C implementation, and RTL verifications for the Direct Si
ngle Scan LDPC Min Sum
* Design, C implementation, and RTL for the LLRs used in the LDPC error correcti
on module
* LDPC performance measurements with AWGN surpasses all competitors design specs
* RTL module verifications of digital EQUALIZER, and ECHO, NEXT, and FEXT cancel
lers
* 1CHIP/2CHIPS top level verifications of digital EQUALIZER and ECHO, NEXT, and
FEXT cancellers and system level silicon validations
Cypress Semiconductor / Silicon Packet 01/01 - 03/06
Co Founder and Design Engineering Manager, Silicon Packets (acquired by Cypress
Semiconductor)
* Involved in development of 10G Ethernet product compliant with 802.3ae standar
d
* Responsibility included design definition and specifications implementations f
or the Ethernet and HDLC Packets over SONET Networks with APS System
* Design and RTL coding for all DSP functions including Parallel Pipeline Intern
et CRC, PCS Scrambler/Descrambler, HDLC FCS16 and FCS32, HDLC Scrambler/ Descram
bler, SONET Scrambler/Descrambler, PCS Jitters generate and Jitters check, ATM t
HEC with Error Correction algorithm, eHEC and payload FCS32/16 error detection
* All modules were synthesized and met the timing requirements
* Block and Top Level Verifications of SONET, HDLC, and APS
Embedded Wireless Devices, Inc., Pleasanton CA 01/00 - 01/01
Senior Lead Scientist
* Architecture of DSP chip for the Wireless Networking, Voice Over Internet Prot
ocol/VoIP and Internet Telephony
o Patents are submitted for the DSP architecture and algorithms
* DSP Architecture of the core modules required for the implementation of VoIP
* DSP Architecture of the core modules required for the implementation telephony
algorithm such as LMS, DTMF, CPM tones, Echo Cancellation and Noise Cancellatio
ns
* VoIP Voice Compression Algorithm development and assembly coding for the new p
rocessor
* Verilog RTL, gate level, and timing verification of all DSP hardware modules
* LRC 2kb/s Voice Compression Algorithm assembly coding for the new processor
SONY Semiconductor Group, San Jose, CA 07/99 - 01/00
Project Leader
* Design and development of the AAC decoder and monitor for the Digital TV
* DAT to DVD upsampler design and implementation, and Sine Wave generations for
antenna calibration
Diablo Research, Inc., Sunnyvale, CA 07/98 - 06/99 Full-time Princi
pal DSP Consultant
* DSP design of a Telephony Card /Mini PBX for PC to be used for future Hi-Tech
homes
* System Architecture and DSP Processor Selection, DSP assembly Boot Code for th
e Sharc 21065L, DSP Sharc 21065L SPORTS setup to load FPGA from EPROM, .DSP/FPGA
Code Down Load through the Sharc SPORTS, DSP Operating System Design for DSP ta
sk handling and messaging with the Window NT Drivers, DSP code developments and
implementations for complete HW/FPGA and relay matrix tests and functional verif
ications
Hyundai Electronics America, San Jose, CA 03/96 - 06/98 Principal
* Design and Development of the DSP Vocoders for the CDMA Wireless Phones
* Involved in all phases of DSP System Architecture, projects and task schedules
, DSP design, SPW simulations, OAK assembly codes, Hardware and software interfa
ces and tests of the QCELP 8kb/s / QCELP 13kb/s vocoders for the OAK DSP Process
or
* Algorithm Design, SPW simulation, and OAK assembly code of the Acoustic Echo C
anceller for the CDMA handsets
IBM/Siemens ROLM Communications, Inc, Santa Clara, CA 11/89 - 03/96 Adv
isory Engineer/Senior Scientist, PhoneMail DSP Engineering
* Design of DTMF Receiver for the PhoneMail System to meet TIA and FCC specifica
tions
o The project included the Architecture, Design, Algorithm developments, digital
filter designs, C-simulations, Integer C implementations, ADSP210x DSP code Dev
elopments and testing using the Analog Devices DSP simulators, Hardware tests, a
nd extensive documentation of design and tests
* Design and development of ADSP210x based DSP module to measure the quality of
analog transmission of voice in the LDN Networks
o The module will detect attenuation, spectral distortions, noises, dropouts, an
d amplitude jitters
* Design of the digital equalizer to compensate for the transmission line impair
ments
* Design of a new DSP tone detector for the FAX and TDD and Far End Disconnect (
FED) signals
o This includes the design specifications, mathematical modeling, digital filter
s design, C-Simulations, ADSP code developments and implementations, test with A
DSP210x simulator, and hardware tests
* Design and implementation of the FAX image processing for the PhoneMail System
o The project includes the FAX algorithm design, C-simulation, DSP assembly codi
ng using the Texas Instruments TMS320C3X DSP module

TEACHING EXPERIENCE
University of San Francisco, San Francisco, CA 08/87 - 12/89 Tenure T
rack Assistant Professor and Director of Computer Engineering Dept.
* Research and Teaching Subjects:
o Optical and Wireless Networking, Digital Signal Processing, Voice Compression,
Voice Recognitions, DSP Processors Architecture and Design, Digital Logic Desig
n, Microprocessors Design and Interfaces, Digital Image Processing, Digital Cont
rol, Digital Communications Systems, Mathematical Modeling of Monolithic Filters
, Design and Simulations of single channel and triple channels Monolithic Video
Filters
ACCOMPLISHMENTS
* Held top rank at Universities during studies for BS, MS and PhD
* Awarded a first rank scholarship for periods of MS and PhD
* United States Patent 5528663 and International Patents H04Q 1/30(20060101) ,H0
4M 3/04, and H04Q 1/46 for IBM/Siemens ROLM for the DTMF Receiver Algorithm. Rec
eived distinguishing awards.
* Patents in progress for the DSP architecture and VoIP algorithm
* United States Patent 7047479 the Parallel Implementation of the CRC for the Cy
press Semiconductor 10Gbits OC192 POSIC
* Patents in progress for the Direct Single Scan LDPC for Plato Networks

COMPUTERS SKILLS
* Verilog Programming, VERA Programming, C-Programming, SPW Simulator, MATLAB,
SignalScan, nc Verilog, Simvision, DSP Assembly programming for Sharc 21065L, OA
K, AT&T 1616/1617, TMS320C3X, Motorola 68x, 68HC12 and DSP210X Processors, DOS
, WINDOWS, UNIX

CITIZENSHIP: U.S. CITIZEN