5.

5.6.1
RECEPTION

GENERAL

See diagram 5:15.

The echo signal from the antenna is fed through the waveguide switch, one of the circulators
and a receiver protector to the Mixer, where the RF signal is mixed with an LO signal so that
a 30 MHz IF signal is created. This IF signal is then amplified. The gain can be controlled
from the Control Table in two different ways. In the case of step attenuation (STEP ATT) the
signal is attenuated by a constant value. In the case of Sensitivity Time Control (STC) a
range-tied attenuation is obtained w h i c h can be regulated manually.

The IF signal is bandpassfiltered and split into two signals. One of these is fed to an amplifier
and envelope detector, which gives a raw video signal. The other is fed through three
attenuators and an amplifier. The attenuators are controlled by PRF CH- and 40 KM-buttons.
The amplifier has variable gain manually controlled from the MGC-potentiometer on the
Control Table. Afterwards the signal is divided in two channels. Each signal is phasedetected
against a 30 MHz reference signal, which is phaseshifted 90° between the channels. The two
phasedetected quadrature signals are called I- and Q- signals.

The phase of the quadrature signals contains the Doppler information. The division into
quadrature channels means that the Doppler signal is detected at maximum amplitude and
also in such a way that phase blindness is avoided.

The two bipolar video signals are then filtered so that the IF bandwidth is adapted to the
transmitter's pulse width in both range areas.

Troubleshooting is facilitated because the reception circuits are provided with automatic
function supervision. Light emitting diodes indicate the whereabouts of the fault so that it can
be traced to the defective unit.

The radar is also equipped with switches, by means of which the various functions can be
simulated by connecting test stimuli. It is also equipped with a digital display, where the
receiver's noise level can be read-off.

5.6.2 RF RECEPTION AND IF AMPLIFICATION

See diagram 5:16.

The echo signal received from the antenna passes through the waveguide switch,
a circulator and a receiver protector to the mixer, which is a balanced diode
mixer. In this mixer the received RF signal is mixed with the LO signal so that a
30 MHz IF signal is formed.

The IF signal is amplified in an amplifier and the gain can be altered with two
voltage-controlled diode attenuators, as step attenuation (STEP ATT) or as a
time (range) variable attenuation (STC).

The signal is filtered in an 800 kHz bandpass filter and then divided up into
two channels: one for envelope detection to give a raw video unipolar signal
and the other for phase detection to give two quadrature bipolar video signals.

Operation and control

The gain of the IF signal can be altered with two voltage-controlled diode
attenuators. Diode attenuation is engaged from the control table by means of
push-buttons STC ON and STEP ATT. These push-buttons generate the signals
"NEDOMK" and "ASTDTB" to the amplifier.

When step attenuation is selected, a constant voltage is connected to the

attenuators so that a 30 dB attenuation is obtained. In the case of STC, the
attenuators are controlled by a sweep voltage from a sweep generator.

The sweep voltage gives a range-tied attenuation as according to figure 11.

The sweep generator is triggered by a sync pulse, "PNEDSYB", which is

received from the pulse generator in the Signal Processing Unit at each
transmission pulse. The sweep generator generates a falling voltage, the start
value of which is determined by the position of the STC potentiometer on the
Control Table. This potentiometer causes a parallel-shift of the attenuation
curve as shown on the dashed line in figure 11.

Only step attenuation will be obtained if both buttons, STC and STEP ATT, are
depressed.

Figure 11. Sensitivity Time Control

Supervision

The diode currents in the mixer are monitored so that check voltages are obtained. These
voltages are compared with threshold values. If the mixer currents are too low the
"VLARMT" signal will be generated, this signal illuminates the RX lamp on the Radar
Panel.

Testing

The Radar Panel contains special test terminals, where the mixer diode currents can be
measured.

Unipolar video

The IF signal from the Microwave Unit is also fed to the Envelope Detector where it is
amplified, limited and envelope-detected. It is then forwarded through a 200 kHz low pass
filter and an emitter follower to measuring terminals on the Radar Panel, where the unipolar
video (raw video) can be measured with an oscilloscope. The limiter gives maximum 2.5 V
amplitude on the output signal.

The unipolar video is fed to the pcb DATA SELECTOR, where a choice can be made between
this video and a recorded video from a tape deck. Selection is made with push-button
PLAYBACK on the Radar Panel. The selected raw video is connected into the Indicator when
the R-VIDEO button on the Control Table is pressed.

5.6.3PHASE DETECTION

See diagram 5:17.

5.6.4BIPOLAR VIDEO

The IF signal from the Microwave Unit is fed into the IF-Phase Detector, the
task of which is to give a bipolar video containing information about eventual
Doppler shifts. Detection takes place in two quadrature channels, which are
phase-shifted 90°.

The signal is amplified and limited in the IF-Phase Detector. Three attenuators
are connected both before and after the limiter. Attenuator 2 is used for attenuate
the IF signal 3 dB in the 20 km range mode so that the same noise level is
obtained in both range areas. This attenuation compensates that the filter in
Filter Amplifier for 20 km range has twice as big bandwith as the filter for 40
km.
 Attenuators 1 and 3 are controlled from the Control Table by means of push-
button , which gives the signal "PRFVXM" so that either the attenuator before
or the attenuator after the limiter is engaged. When transmitting in PRF-change
mode, the control signal "PRFVXM" is treated so that attenuator 1 (before the
limiter) is connected. This means that the signal is attenuated prior to entering
the limiter, that only signals with high amplitudes are limited and that clutter is
not limited.

When staggered PRF is employed, attenuator 1 (before the limiter) is

disconnected. The signal to the limiter will then be 20 dB greater than normal.
The amplitude of undesirable clutter signals is thereby limited in the limiter.
This is necessary because the Doppler filter suppresses clutter signals worse in
staggered PRF than in PRF-change. To maintain the total gain at a constant
level, the signal is instead attenuated 20 dB in attenuator 3.

The limitation level of the limiter is adjusted by the knob MGC on the Control
Table. The nominal value of the noise is 071 ± 2. The actual value can be read-
off on a digital display on the Radar Panel, when the push-button NOISE I/Q is
pressed.

The limited signal is fed to a bandpass filter (bandwidth 4.5 MHz) and then to
two phase detectors, I and Q, which also receive a reference signal from the
Reference Oscillator.

The reference signal to one of the phase detectors is shifted 90° in phase. Therefore, the bipolar
video signals on the outputs of the p h a s e detectors will be phase shifted 90°. In this way the
video signal will be divided into quadrature signals.

The quadrature signals are treated alike, but individually, in the two channels o f the Filter
Amplifier.

Depending upon which range mode has been chosen, the signal will be filtered in one of two
LP filters. These filters have different limiting frequencies. In the 40 km mode the limiting
frequency is 62 kHz and in the 20 km mode the limiting frequency is 125 kHz. The filters
match the bandwidth t o the transmitter's pulse width in both range modes.

After being amplified the I and Q video signals are forwarded to the pcb AID
CONVERTER. Both signals can be checked in measuring terminals on the Radar Panel.

5.6.5GENERATION OF THE 30 MHz REFERENCE SIGNAL

 A stable, 30 MHz reference signal is required for phase detection. This signal
is generated by a crystal oscillator in the Reference Oscillator. It is amplified and
fed directly to the phase detector, where it is used for quadrature detection.

Square pulses are generated in a pulse former by the 30 MHz signal. After
frequency division, a 15 MHz signal is obtained which is sent to the pcb PRF
GENERATOR in the SPU as a clock signal for producing trigg signals to the
radar. The square signal from the frequency divider is formed into a 15 MHz
sinus signal in a bandpass filter. This sinus signal is used as a reference signal
when phase-locking the RF and LO signals. The 15 MHz signals can be checked
in measuring terminals SPU REF and RFG REF on the Radar Panel.

The reference oscillator also contains a crystal oscillator with a frequency of 30

MHz + f, where f = 2 kHz. The oscillator is used when parts of the IFU and the
Signal Processing Unit are being tested.

5.6.6TESTING

Two tests can be performed to check the IF phase detection function:

• IF test
• Doppler test

The tests are activated by the push-buttons TEST STIMULI IF and DOPPL on
the Radar Panel.

When the IF test is being carried out, a 30 MHz test signal is fed to the Phase
Detector. The test signal is attenuated just so much that the limiting circuits are
activated.

The second oscillator sends a reference signal to phase detectors I and Q; this
signal has a frequency of 30 MHz +t f, where of 2 kHz. This means that the
Doppler filter's attenuation band is shifted 2 kHz and that the test signal can
thereby pass the filter.

During the Doppler test, the reference signal to phase detectors I and Q is taken
from the oscillator with the frequency of 30 MHz +1- f. Thereby the ground
returns can pass the filter.
 5.7

5.7.1
SIGNAL PROCESSING

GENERAL

See diagram 5:15

The quadrature signals from the IFU are fed to the AID CONVERTER board where they are
sampled and time-multiplexed, so that both signals from the I and Q channels can be
processed in the same digital Doppler filter.

The analogue and time-multiplexed video signal is AID converted before being fed into the
digital filter.

The digital Doppler filter is a sixth degree high pass filter, the task of which is to separate
target echoes from ground return and other clutter signals with a certain maximum Doppler
frequency. The filter is built up of three filters of the second degree.

The first filter consists of two transversal (forward-coupled) filter links of the first degree with
fixed filter constants. The second and third filters each consists of a recursive (feedback) filter
link of the second degree with variable filter constants. the magnitude of which is dependent
upon the selected PRF-type (PRF-changing or staggered PRF), PRF (at PRF-changing) and
selected range mode (at staggered PRF), so that the total filter is given an adequate frequency
characteristic.

After the filtering process, the undesirable clutter signals have been suppressed and normally
only the target echo signals remain.

The video signal is re-formed to one channel on the MODULUS EXTRACTOR board by
extracting the absolute values of the two quadrature signals and by summing them as follows:

ill+ I wheniljlQI

+,2i whenhkIQI

It is desirable to keep the risk of false target detection (the false alarm rate) constant and
independent of the input noise level. This function is obtained by dividing the value of the
processed bin by the mean value of the eight surrounding bins in CFAR (Constant False-Alarm
Rate) circuits. The quotient is a measure of whether the signal can be regarded as a target
echo or as noise. The quotient then can be attenuated manually for adoptation to different
types of jamming.

The spread of t h e quotient is reduced by integrating over a number of sweeps.

The quotient value is then compared with three threshold values so that target
presentation on the Indicator can be obtained in four brightness levels, where
a strong target echo gives an indication with a high brightness level. No
indication is obtained at the lowest level (no target). The four levels are
transferred by means of a 2-bit signal, so-called synthetic video.

Delays of the signal-processed video signal give a time difference between the
raw video and the synthetic video. T h e synthetic video is therefore delayed
further s o that it i s synchronised with the raw video signal from the next
transmission pulse.

Jamming that exceeds a certain level are supervised with a jammer bearing
indicator and the direction to the jamming source is presented on the Radar
Indicator.

A 15 MHz signal from the reference oscillator in the IFU is used for
generating trigg pulses.

In the SPU the offset-binary code is used, which means that the greatest
possible number is represented by only "ones", the number zero by "one"
followed by "zeroes" and the smallest possible (most negative) number by
only "zeroes". Thus the sign information is in the first bit ("one" for positive
numbers including number zero, and "zero" for negative numbers). After Filter
3 the SPU mainly uses positive numbers and the sign bit is often omitted.

5.7.2 MULTIPLEXING AND AID CONVERSION

See diagram 5:18.

The bipolar video in the I and Q quadrature channels is fed from the IFU to the
A/D CONVERTER board where the signals are first sampled and
multiplexed, i.e. time-shifted. In this respect, a selector feeds the I video to
sampling circuit S/H 2, where it is sampled. At the same time, the Q video is
fed to sampling circuit S/H 1 where it is sampled and where the resultant value
is retained on the output. After a fixed time the selector will switch over and
allow the sampled Q video to pass. It is then once again sampled in the
sampling circuit S/H 2.
Sampling pulses: S/H 1 t 0-sampling
S/H 2 t I-sampling
Selector t Q-resampling

Signals: Before the selector

time

means not sampled signal

means sampled signal

Figure 12. Sampling and Multiplexing

The interval-time which corresponds to a pair of I sample and Q sample (In and Qn) is
called range bin n, see figure 12. The range bins are successively delayed during the
signal processing in the SPU.

The sampling rate is determined by the selected range mode and determines the length
of the range bins. In the 20 km range, one bin represents 320 metres. In the 40 km
range, one bin represents 640 metres.

After passing through S/H 2 the video is A/D converted according to the method
of successive approximation. The converter consists of a comparator,
approximation logic and a D/A converter. The approximation logic converts the
analogue signal to a digital one, bit by bit, starting with the most significant bit
(MSB). The approximate digital signal is D/A converted and then compared
with the input signal. The signal from the comparator controls the conversion
in the approximation logic until the least significant bit (LSB) has been
determined.

After the A/D conversion, the digital signal is clocked out to the Doppler filter
 for digital filtering.

Clock pulses to the sampling circuits, the A/D converter and the output circuit
are generated internally by the signals "TRCLADC" and "-TRSPSA" from the
PRFGENERATOR board.

5.7.3 DIGITAL FILTERING

The video signal is processed in a digital Doppler filter so that clutter signals, for
example ground echoes, are suppressed.

The Doppler filter is a sixth degree high pass filter built-up of three second order
filters called Filter 1, Filter 2 and Filter 3.

The filter constants are fixed in Filter 1 but can be changed in Filters 2 and 3
(see Diagram 5:17).

Filter 1

See diagram 5:18.

The digital video signal is fed from the AID converter to Filter 1 on the FILTER
1 board. This filter is transversal, i.e. forward-coupled, and consists of two first
degree filters. The value of the video signal from the corresponding range bin
during the previous sweep is subtracted from the input signal to the filter. This
subtraction is performed by adding the 2's complement of the old value to the
new value. The output signal from Filter 1 is therefore the result of an
amplitude-comparison between three successive sweeps.

Internal synchronizing pulses and clock signals to the FILTER 1 board are
obtained from the board's own clock pulse generator, which is clocked by the
"SPCL" signal (3.75 or 1.875 MHz) from the CLOCK PULSE GENERATOR
board.

On the board input there are circuits that synchronize the signal processing in the Doppler
filter with the AID converter.

The FILTER 1 board is included in the functional supervision system, and is checked every 8
seconds. This is done by using a known test signal from the TEST CIRCUITS 1 board as an
input signal. The use of this signal is controlled by two signals: "TEST", which is emitted
during the supervision interval, and "STIMSET" which is emitted during bins 6-10. During
other bins the input signal to Filter 1 is zero.
The test result is fed out in series form to the TEST CIRCUITS 2 board, where it is compared
with a check value. To do the feeding out a parallel/series converter is loaded with the test
result, which is shifted out when the converter receives a start pulse from a control circuit. The
control circuit is activated by the "TESTFl" and "Q09" signals. The testing procedure is
described in detail in the section "Functional Supervision".

Filter 2

See Diagram 5:19.

Filter 2 is a recursive filter of the second degree, made up of the two boards FILTER 2
SUMMATION and FILTER 2 DELAY AND CONSTANT GEN.

On the FILTER 2 SUMMATION board the input signal from the FILTER 1 board is added to a
feedback signal from the FILTER 2 DELAY AND CONSTANT GEN board. The feedback
signal is composed of two signals delayed one and two sweeps respectively. The sum signal is
rounded off and forwarded to circuits used for limiting the absolute value of the signal. These
circuits are also used to select a signal with value zero immediately prior to functional
supervision. Because the filter is recursive it must be "empty" when the test signal is given.

The limiting of the signal value is done by feeding the sign bit and the two most significant
bits to control logic circuits while the remaining bits are fed to a data selector. The three bits
control the data selector so that the signal is either unchanged (when it is within the limits), or
changed to just "ones" (too great input signal), or changed to just "zeroes" (negative input
signal with too great absolute value). After the data selector the signal is completed with the
sign bit from the control logic circuits.

The control logic circuits also senses the "CLEARl" signal, which is given when the filter is
to be "emptied". The output signal from the data selector is then just "zeroes". These are
completed with the sign bit "one" from the control logic cirucits so that the number zero is
obtained.

The output signal is fed in two directions, forward for future summation and also to the
FILTER 2 DELAY AND CONSTANT GEN board.

In the FILTER 2 DELAY AND CONSTANT GEN board the signal is inverted and delayed
one sweep and then divides itself into two branches.

One branch is inverted and once more divided into two branches, one of which goes to Data
Selector 1 and then to the feedback circuits while the other branch forms a forward-coupling,
which consists of an inverter, a division circuit, a summation circuit and a multiplicator. In
this way, -14/8 of the (one sweep) delayed signal is added to the signal that has been delayed
a total of two sweeps. The sum signal is fed to the FILTER 2 SUMMATION board where it
is added to the non-delayed signal from the data selector on the FILTER 2 SUMMATION
board. The sum signal is normalized in relation to the noise by multiplying the signal by a
certain value, this value is dependent upon the type of PRF and the range mode.

The signal from Data Selector 1 and the two-sweeps delayed signal are fed to the feedback
circuits. The feedback constants (filter-) in the loop are variable and are selected with Data
Selector 1 and Data Selector 2.

Control signals t o these are:

T2PRFSA staggered PRF

T2PRFH high PRF
T240KMF 40 km range

The feedback signal is fed to the FILTER 2 SUMMATION board input where it is added to the
input signal from the FILTER 1 board.

During functional supervision the test result is parallelseries converted before it is sent to the
TEST CIRCUITS 2 board for comparison with the correct values. The "TESTF2" signal
controls the series output together with clock signals.

Filter 3

See Diagram 5:20.

The filtering continues in Filter 3, which functions in the same way as Filter 2 although its
filter constants have other values.

The feedback signal and input signal are added together, rounded off and limited on the
FILTER 3 SUMMATION board. After this, the signal is fed to the FILTER 3 DELAY AND
CONSTANT GEN board.

The feedback constants of Filter 3 are selected with Data Selector 1 and Data Selector 3. In
Filter 3 one forward-coupling constant is also variable, and is selected by means of Data
Selector 2.

The three data selectors are controlled from a common control logic.

During functional supervision the test result is fed out in series form from a parallel/series
converter on the FILTER 3 SUMMATION board.
5.7.4 ENVELOPE EXTRACTION AND LIMITING

See diagram 5:21.

The Doppler-filtered, digital video signal, i.e. time multiplexed I and Q videoes,
is forwarded to the MODULUS EXTRACTOR MLD LIMITER board where
the absolute values of the I and Q videoes first are extracted. The absolute values
are used for envelope extraction, i.e. for re-forming a non-multiplexed video
signal the value of which is approximately v/I 2 + Q2.

When the absolute values of the I and Q videoes are extracted the value of the I
video is obtained during the first half of the range bin and the Q video during the
second half. The video signal is delayed bin and is then compared with the
non-delayed video signal so that absolute values of corresponding I and Q
videoes for each bin are compared, figure 13.

IQnI
n+11
Qn+11
II
n+21
I Qn+21

U-

Signal after absolute value extraction

Signal after delay

Comparison time

Figure 13. Delay and Comparison

The comparator controls two data selectors which, together with a division circuit and a
summation circuit, extract the following:

Il + ; 2 when III >_ IQ

I Ql +I F/2 when 11 < IQI
(approximation for V I2 + Q2)

The resultant video signal is fed to a limiter, which limits the signal upwards, thereby
decreases the effect of isolated disturbances and strong target signals. This is done by
comparing the video signal with a comparison signal constituting the upper limiting level.

The value of the comparison signal is four times the mean value of the eight surrounding
range bins. If this value should be less than a fixed reference, then the comparison signal will
instead get the same value as the fixed reference.

When the video signal is greater than the comparison signal, the latter will be selected.
Otherwise, the video signal will be selected.

The absolute values of the I and Q videoes are also tapped from the circuit board. The signal is
used for noise measurements.

5 .7 .5 MEAN LEVEL DETECTOR (MLD) AND CFAR

See diagram 5:21 and 5:22.

SPU is designed to give a certain f a l s e alarm rate for white noise. The false
alarm rate is kept constant, even if the noise varies, by dividing the signal in
the processed range bin by the mean value of the signals in the eight
surrounding range bins.

The ratio is used (after integrating over several sweeps) as a measure of

whether the signal should be regarded as noise or target echoes.

This function is called CFAR, Constant False Alarm Rate, and is divided upon
three circuit boards:

s MLD DELAYING CIRCUIT, Diagram 5:21

• MLD ACCUMULATOR, Diagram 5:22
s RATIO EXTRACTOR, Diagram 5:22

Mean level detection for the first and last range bins takes place in a special way
since there are not eight surrounding bins. The procedure is described later in
this section.
 When range bins 5-56 are being processed the 12-bit binary video signal will
pass Data Selector 1, be forwarded to Delayer 1 and then to Delayer 2. These
delayers give a delay equivalent to five range bins. The value of the processed
range bin is fed from the output of Delayer 2 to the MLD ACCUMULATOR
board and also through Data Selector 2 to Delayer 3 where the signal is delayed
a further four range bins. So the signal from Delayer 3 is delayed nine range bins
in relation to the input signal to Delayer 1. Delayers 1, 2 and 3 can be regarded
as a 9 x 12 bit shift register, through which are shifted the signals from the
processed bin and the eight surrounding bins.

The output signal from Delayer 3 is subtracted from the input signal (signal to
Delayer 1) that passes Data Selector 3.

The difference signal (in point A, figure 14) is fed to the MLD
ACCUMULATOR board, to which is also sent the output signal from Delayer 2,
i.e. the value of the processed bin.

The MLD ACCUMULATOR board includes a summation circuit, which gives

the sum of the contents in one bin and its eight surrounding bins (point B). This is
done by adding (in point B) the difference signal in point A to the signal in point B
which is the previous sum in point B delayed one bin. In this way the sum will be
modified so that it is ready for the signal processing of the next bin.

The sum of the values of the processed bin and the eight surrounding bins (point C) is fed to a
subtraction circuit, where the value of the processed bin is subtracted (point D). The remainder
is divided by eight to give the mean value of the eight surrounding range bins (point E).

Delayer 1 Delayer 2 Delayer 3

MLD DELAYING CIRCUIT MLD ACCUMULATOR

!+
Delaye
A C E

Value of the signal processed bin

Figure 14. Mean Level Detector

Example:
When e.g. range bin 24 is being processed, the shift register will have the following contents:

(Xn = the value for range bin n)

X28 X27 X26 X25 X24 X23 X22 X21 X20

t
Delayer 1 Delayer 2 Delayer 3

The value of the processed bin is found on the output of Delayer 2. The value of bin 29 is found
on the input to Delayer 1.

The values for the different points in the Mean Level Detector are then:

X29 X 2 0

Content in point C

CX ++X
2 0 + X 2 1 . . . 2 s

za + ( X 2 9 -X

22 + X23 + 2 4 + X25
D

E
X+X
2 0 21
26 + X27

Content in point A

Sum of values of nine bins

D. X
2 0 +X 21+X 22 23 + X 2 4 25 +X
26 + X27 28 - X 2 4

(where X24 is the value of the processed bin)

E: content in D 8
The result in point D is the sum of the eight surrounding bins i.e. four bins with lower
numbers (X20 to X23) and four bins with higher numbers (X25 to X28) than the processed bin
(X24). The mean value is obtained after dividing by eight (point E).

The contents of the shift register are changed when bin 25 is to be processed:

X29 X28 X27 X26 X25 X24 X23 X22 X21

Delayer 1 Delayer 2 Delayer 3 The values in the Mean

Level Detector are modified as follows:

21

FX X
30 2 1

GX 2 1 + X22 +....+X 29 + (X 30 -

HX + X + . . . + X
21 22 29

IX 2 1 -~ X22 +.... + X29 - X25

Jcontent in D 8

In this way the mean value of the eight surrounding bins is obtained for the next processed
bin 25
(X ).

(End of the example)

When the first four range bins are processed there are only 0-3 previous bins. Therefore the
mean value is formed in a special way. When the first signal-processed bin (X1) is found on
the input of Delayer 1, the MLD is connected as in figure 14, i.e. X1 is fed both to Delayer 1
and to the Accumulator delayer.

The connection of the MLD is changed when range bins 2-5 are found on the input of
Delayer 1, see figure 15.

MLD DELAYING CIRCUIT ' MLD ACCUMULATOR

A
Delayers 1 and Delayer 3
2

Figure 15. Apperance of the Mean Level Detector when the range
bins 2-5 are found on the input of Delayer 1.

The input signal to Delayer 1 is then also fed to Delayer 3 through Data Selector 2.

The contents of Delayers 1, 2 and 3 after the first clock pulses are shown in figure 16.

Delayer 2
Delayer 1 Delayer 3

1 CP

X4

t
The signal processed bin

Figure 16. Contents of the delay chain when the first range bins are processed.
 This connection of the MLD (figure 15) also means that the output signal from Delayer 3
is subtracted from the input signal to Delayer 1 multiplied by 2.

The contents of the Mean Level Detector when bin 1 is processed, will be:

A:

B: X1 + 2X2 + 2X3 + 2X4 + 2X5 + (Xs -

X2)

C: X1 + 2X2 + 2X3 + 2X4 + 2X5

D: 2X2 + 2X3 + 2X4 + 2X5

E: content in D
8

In this case, a weighted average of the four subsequent range bins (2-5) is used instead.

When range bin 2 is to be processed the Mean Level Detector will work in the normal way as
described previously (see figure 14). Figure 17 shows the contents of the delay chain, the mean
values, etc in different time positions.

0
to
x
+ 0
o X+
X +
+ UO v+ X
X 0
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X + o`
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C 0 0 -- N M
r N M V ul to n 00 CI t D l 0 t o 40 tD

Figure 17. Mean Level Detection

When the last four bins are being processed, the signal from Delayer 2 is fed back to the
input of the delay chain through Data Selector 1 so that a weighted mean value is obtained for
the bins, see figure 18.

Starting contents

Feedback of the bin 56 value

Feedback of the bin 57 value

Feedback of the bin 58 value

Feedback of the bin 59 value

X60 X59 X58 X57 X56 X55 X54 X53 X52

 X56 X60 X59 X58 X57. X56 X55 X54 X53

X57 X56 X60 x59 X58 X57 X56 X55 X54

X58 X57 X56 X60 X59 X58 X57 X56 X55

X59 x58 x57 X56 X60 X59 x58 X57 X56

Figure 18. Contents of delay chain when the last rangebins are being processed.

This gives a modified mean value for the last range bins in almost the same way as the first
bins.

The mean value and the value of the processed bin are both clocked through output circuits
and then forwarded to the RATIO EXTRACTOR board. The mean value is also fed to the
MODULUS EXTRACTOR MLD LIMITER board where it is used for limiting the video
signal.

At the beginning of each sweep the delay chain (Delayers 1, 2 and 3) is reset by the signal
"Q04KI". This is done so that the values of the range bins from the previous sweep do not
influence the mean value during the next sweep. The delayer in the MLD
ACCUMULATOR is reset by Q04K5".

When the frequency, range mode, PRF-type or PRF are altered, the mean value will be
blocked by the selector on the output. Instead, a signal consisting of the number zero will
be selected.

The Mean Level Detector is tested during functional supervision by setting the contents in
Delayers 1, 2 and 3 and the Accumulator delayer to specified test values.The mean value
then obtained is parallel/series converted and sent in series form to the TEST CIRCUITS 2
board, where it is compared with a check value. (See section "Functional Supervision" ).

The signal from the selector in the MLD ACCUMULATOR (mean value or the number
zero) is forwarded to the RATIO EXTRACTOR board and to the TIME ALIGNMENT,
JAMMER BEARING INDICATOR board, where it is used for jammer bearing indication.
Only the most significant bits are needed in this respect because only the strongest signals
are interesting.

In the RATIO EXTRACTOR board the contents of the processed bin are divided by the mean
value of the eight surrounding bins.
The value of the ratio can also be attenuated; this attenuation is determined by the CFAR
THRESHOLD switch on the Control Table.

The ratio is extracted first through an approximate conversion to 2's logarithms of the mean
value and of the value in the processed bin and then the difference between these logarithms
is formed.

Before the mean value is converted to its logarithmic equivalent it will be limited downwards
so that the ratio, after division, does not become too great. This is why the mean value is
compared with a reference, the value of which is 3 dB under the normal noise value.

The CFAR function can be disconnected by means of the CFAR OFF button on the Radar
Panel. A fixed mean value (= normal noise level) will then be coupled to the Ratio Extractor
through Data Selector 2.

The value of the processed bin and the mean value are dealt with in the same way during
logarithmic conversion. Each value forms a number, which is split- up into a mantissa (m)
and a characteristic (k). This number can then be written as m x 2'`. A sensor registers the
position of the most significant "one". The position then determines the characteristic of the
number. The mantissa is obtained by using the four bits nearest below the most significant
"one". In practice, the most significant "zero" is sensed since negative logic is used.
Afterwards, the mantissas and characteristics are subtracted and compiled so that the 2's
logarithm of the ratio is obtained.

A fixed value is also added to the value of the processed bin so that the difference cannot be
negative.

The ratio can be attenuated for other input signals than white noise by subtracting a value
determined by the CFAR THRESHOLD switch on the Control Table.

To obtain the real ratio the number must be antilogarithmically converted. The number is
therefore fed to a combination data selector, which codes out the antilogarithmic value of
the ratio. Selection of combination is performed by a selector logic, which is fed with the
number's characteristic.

The ratio must be limited in the combination selector; otherwise the signal will be "spread
out" in time after integration. The value of the ratio is limited to the number 3.875 and
consists of only five bits, which are forwarded to the INTEGRATOR board.

When the frequency, PRF-type, PRF or range mode are changed, the signal from the Ratio
Extractor will be blocked by signal "LBlIQOl". Instead, a fixed value (the number 1.0) will
be fed to the integrator, which then comes into operation quicker than during test when the
input signal is reset.
5.7.6

INTEGRATION

See diagram 5:23.

A five-bit signal is fed from the RATIO EXTRACTOR board to a double integrator on the
INTEGRATOR board.

Integration is carried out to obtain more destinct amplitude levels on the signal. This is
illustrated by figure 19.

Target echo and noise after

integration
~"'

Target echo and noise before integration

 x
(Amplitude)

Figure 19. The probability densities for the amplitude of target echo signals and noise signals

The unbroken lines, which represents the probability densities before integration,
shows that there is great variation in amplitude. If the target detection threshold
have to be set at amplitude X0, then there would be a risk of false detections
caused by a noise signal (the lined area in figure 19).

Another amplitude distribution is obtained after the signal has been integrated
(the broken line), i.e. there is a lesser spread in amplitude. This decreases the risk
of a noise signal causing a target echo (false alarm).

The double integrator is shown in figure 20.

Figure 20. The integrator

The constants in the integrator will vary according to the selected range mode:

K2
20 km 40 1/16
km 1/8

The value already in the integrator, which is the integrated value from the corresponding
bin during the preceding sweep is subtracted from the input signal to the integrator. The
difference is then divided by 8 or 16, depending upon the selected range mode. The result is
fed to a summation circuit. Because the difference can be negative, a sign bit will also be
read-out to the summation circuit. The integrator's value is added to the divided signal and
the sum is forwarded to the next integrator. The sum is also read into a delayer (shift
register), which gives the delay of one sweep (T).

The second integrator works in the same way as the first.

The result from the second integrator is clocked out through a feed circuit and inverted
before being fed to the THRESHOLD SWITCHES, THRESHOLDS board. However, the four
least significant bits are not forwarded. These are only used during integration when greater
accuracy is required.
The integrators are reset by the "CLEARY' signal when functional supervision starts up.
The result of the functional supervision is fed through a parallel/ series converter and then to
the TEST CIRCUITS 2 board.

The integration causes a certain bearing error, i.e. the antenna will not point at the target
when the echoe is presented on the PPI. This error is corrected by calibration.

5.7.7THRESHOLD SWITCHING

See diagram 5:23.

Target echoes are presented on the PPI in three different brightness levels. These
levels are dependent upon target range, target cross section and radial velocity.
The levels are obtained by comparing the integrated signal with three reference
threshold values. The threshold values are different for both range modes.

The result from the three comparators is fed to a decoder (summation circuit),
which forms the synthetic video signal consisting of two bits.

During functional supervision, special threshold levels will permit the two-bit
synthetic video to obtain a specified value. If any other value is generated, the
supervision circuits will detect this and give an alarm.

5.7.8TIME ALIGNMENT

See diagram 5:24

As previously described, the synthetic video signal has been delayed in the IFU
and SPU. This means that there will be a considerable time difference between
the raw video and the synthetic video.

This difference in time is compensated in time alignment circuits, where the

synthetic video is delayed still further so that it coincides with the raw video
signal from the following (next-in-line) transmission pulse.

The two-bit synthetic video is fed to a level selector on the TIME ALIGNMENT
JAMMER BEARING INDICATOR board. If a jammer bearing has been
indicated, then this will select a synthetic video with brightness level 2 (See
section "Jammer Bearing Indication").

The video is then delayed in a read/write memory, one for each video bit.
 The address to the memory is obtained from two counters; one used when
writing-in, the other when reading-out. These counters give addresses 0-63, and a
selector makes sure that the correct address is selected for input and output.

Counter 2, which gives the read-out addresses, is started by pulse "Q00". Counter 1, which
gives the write-in addresses, is started by pulse "Q10".

Pulse "Q00" arrives before "Q10" so that the first bin is read-out before the last bin is
written-in.

A total of 60 range bins are forwarded, although the delay memory is designed for 64. The
last four bins are therefore blocked by a blocking circuit (pulse "Q60") until pulse "Q00"
arrives.

The blocking circuit and the delay memory are both isolated from subsequent circuits by
means of an isolating circuit. When the memory is addressed for writing in the synthetic
video value, this same value will also be seen on the output from the memory. This, of
course, is undesirable. The input value is therefore blocked by the isolation circuit so that it
is not forwarded to the PPI.

Synthetic video is fed from the isolating circuit to a summation circuit, where the video
signals from the TRAINING EQUIPMENT can be added.

If the sum of these two video signals is too great, a signal will be yielded to a level sensor.
This sensor activates a limiter so that the synthetic video is limited to a maximum level.

The synthetic video can also be blocked in the limiter, firstly during automatic functional
supervision and secondly when playing back from a video recorder.

The synthetic video is fed to the Extractor, where synthetic video or extractor video can be
selected. The selected video is fed to the IN/OUT BUFFER 1 board and then on to the
Indicator. It is also fed to measuring terminals, one for each bit, on the Radar Panel.

During functional supervision the circuits on the TIME ALIGNMENT, JAMMER

BEARING INDICATOR board are activated so that a synthetic video with a specified
value should be obtained after the isolating circuit. This test result is fed to the
INTEGRATOR board, from where it is forwarded to the functional supervision circuits for
checking.

5.7.9 J A MM ER B E AR I N G IN DI C A TI O N
 See diagram 5:24.

The TIME ALIGNMENT, JAMMER BEARING INDICATOR board also

includes circuits for jammer bearing indication.

A jammer bearing is indicated by means of bins 40-52 being illuminated on the

PPI in brightness level 2. The actual indication is obtained by, among other
things, sensing the mean value of the eight bins surrounding bin 54. This value
can be regarded as a noise mean value and is obtained from the MLD
ACCUMULATOR board.

An increase in noise in the eight surrounding bins will raise the mean value. This
therefore gives an indication of the noise level. The mean value will, of course,
also increase if many target echoes are received in the eight surrounding bins, but
this is highly improbable.

The following conditions must be fulfilled before an indication is given:

•The noise mean value must be at least 12 dB above the normal noise level.

The noise mean value must be greater than half (6 dB below) the maximum
value measured during the preceding antenna scan.

•The maximum values from the two preceding antenna scans must both have
been 12 dB above the normal noise level.

•Radar silence must not have been ordered. (During radar silence there will be
no generation of the RF or LO signals. This causes the Mixer Unit in the
RFG to self-oscillate, which means that the noise level will increase so
much that the jammer bearing indication can be brought into function. This
is not desirable).

The noise mean value from the MLD ACCUMULATOR board is compared in
comparator 1 with reference 1, which is 12 dB above the normal noise level.

For each transmission pulse the noise mean value will be compared with the value
stored in the max.value register. This register stores the highest noise mean value
measured during an antenna scan. Then comparison is performed in comparator 2.
If the noise mean value is highest, it will be fed into the register to replace the
existing value.

After each antenna scan, the value in the max. value register is transferred to the storage
register. The value is still left in the max. value register but it is shifted down 6 dB after
being transferred.

The storage register contains the max.noise mean value of the previous antenna scan. This
value is divided by 2 and the result is compared in comparator 3 with the present noise mean
value. The value is also compared in comparator 4 with reference 2 (12 dB above the
normal noise level).

The signals from comparators 3 and 4, which give two of the conditions for jammer bearing
indication, are fed to the "condition gate" on the jammer bearing indicator.

The signal from comparator 4 is also delayed for a time period equal to one antenna . scan. The
output signal from the delayer shows whether or not the max. noise mean value from the
two previous antenna scans is 12 dB above the normal noise level.

If a jammer bearing is indicated, the condition gate will yield a signal that must be delayed if
it is to arrive at the same time as the relevant synthetic video, which has been delayed in the
integrator. A bearing error will arise if the indication should not happen to arrive at the
same time as the relevant synthetic video.

The delay for both range modes is:

20 km: 24 PRF periods (sweep)

40 km: 12 PRF periods (sweep)

A selector makes sure that the correct time compensation is obtained.

The jammer bearing indicating signal is fed to a gate that allows it to pass to a level
selector, which selects between the synthetic video and a video with brightness level 2. The
gate has two control signals, one for blocking the jammer bearing signal and one for
allowing it to pass. This means that the jammer bearing signal controls the level selector so
that the video with brightness level 2 is shown on the Indicator for range bins 40-52 when a
jammer bearing is indicated.

5.7.10FUNCTIONAL SUPERVISION

See diagram 5:25.

5.7.11GENERAL

The Signal Processing Unit is provided with an internal automatic functional

supervision system, which makes sure that the SPU is functioning correctly.
 Supervision is carried out about every 7:th second (7.3 sec), asynchronous with the
antenna rotation so that the blind sector which occurs is located in different
bearings during each supervisory period. The functional supervision circuits are
divided up onto two circuit boards, TEST CIRCUITS 1 and TEST CIRCUITS 2.

During functional supervision the bipolar video signal is replaced by a digital test
signal, which is fed to the FILTER 1 board. The control and logic signals, used for
the functional supervision, are generated from a ROM on the TEST CIRCUITS 1
board and are thus pre-programmed. The processed test signal is compared in five
test points with the correct values, which are stored in the memory. Light diodes on
the TEST CIRCUITS 2 board will light up if the two values do not coincide. At the
same time, the TESTFEL" signal is yielded and this illuminates the SPU light
diode on the Radar Panel.

The light emitting diodes on the TEST CIRCUITS 2 board indicate the incorrect
circuit boards as follows:

Test point 1 FILTER 1

Test point 2 FILTER 2 SUMMATION and FILTER 2 DELAY AND CON-

STANT GEN

Test point 3 FILTER 3 SUMMATION and FILTER 3 DELAY AND CON-

STANT GEN

Test point 4 MODULUS EXTRACTOR MLD LIMITER, MLD

DELAYING CIRCUIT and MLD ACCUMULATOR (three
boards)

Test point 5 RATIO EXTRACTOR, INTEGRATOR, THRESHOLD SWITCHES

TRESHOLDS and TIME ALIGNMENT JAMMER BEARING
INDICATOR (four boards)

During the whole functional supervision period, the synthetic video from the
signal processing circuits will be blocked so that the Indicator does not present the
synthetic video formed during functional supervision.

5.7.12 SUPERVISION FUNCTIONS

Functional supervision is started by the "TRSPTS" signal, which is sent to the

start logic on TEST CIRCUITS 1. The start logic performs the following:
 •Generates the "TEST" signal, which indicates that the functional supervision
has started up. "TEST" activates Data Selector 3 on TEST CIRCUITS 2
so that the memory's pre-programmed control and logic signals are selected
for forwarding to the SPU.

•Generates the "CLEAR2" signal, which resets the contents of the result register
and thereby turns off any lights diodes that are indicating faults.

Gives a loading pulse to a counter, which is set to a starting value from

where it starts to count. The counter gives addresses to the memory, where
the test signal, control signals and logic signals are stored.

•Triggers a frequency divider, which controls the test signal to FILTER 1 so

that the sign is alternated from sweep to sweep.

•Generates the "CLEARl" signal, which resets the output from Data Selector 1.

The two signals "CLEARl" and "TEST" are fed to the SPU, where they prepare
different circuits for functional supervision.

The "CLEARl" signal activates:

•FILTER 2 SUMMATION.

The input signal to the filter is reset for a certain period of time so that
"residue" from the feedback loop does not influence the test result.

• FILTER 3 SUMMATION.

The same as FILTER 2 SUMMATION.

•INTEGRATOR.

Blocked (for the same reason as the resetting of Filters 2 and 3).

The "TEST" signal activates:

•FILTER 1
The "TEST" signal, together with the "STIMSET" signal and clock pulse "Q02", feeds
the test signal into FILTER 1.
•MLD DELAYING CIRCUIT
The delaying circuits in the Mean Level Detector are set to special values which,
together with the test signal, give the test result.
• RATIO EXTRACTOR
The ratio is set, together with the "LB1IQ0l" signal, to a fixed value so that it is easier
for the integrator to settle when function supervision starts up.

•THRESHOLD SWITCHES
THRESHOLDS
Special threshold values are engaged for level detection.

When the counter on "TEST CIRCUITS 1" receives a loading pulse from the start logic, it will
start counting in time with the CLOCK PULSE GENERATOR. The counter's eight bits give
an address to the memory where the test values for the I channel are stored. Equivalent values
are fed out for range bins 6-10, and other values are set to zero. The test values for the Q
channel are fixed (value 3.0) and are equivalent for all range bins.

Tests values for the I and Q channels are fed out alternately through Data Selector 1 so that a
multiplexing is performed.

The test signal is forwarded through a phase inverter, which alters the sign of the signal on
every other transmission pulse so that a signal with a Doppler frequency of PRF/2 is obtained.
The test signal is fed from the phase inverter to the input on FILTER 1.

The memory also contains the control and logic signals which are used during functional
supervision. These are fed to Register 2 on the TEST CIRCUITS 2 board, from where they
are forwarded at the correct time through Data Selector 3 and out to the units included in the
functional supervision.

When the test signal has been processed, the result is checked in five points. The Address
Pulse Generator on TEST CIRCUITS 1 gives command pulses to these points so that the
test result is parallel/series converted and then forwarded in series form to TEST
CIRCUITS 2. There, the test results are sent, one at a time, through Data Selector 2, which
is controlled by the three least significant bits from the counter on TEST CIRCUIT 1.

The test result consists of 16 bits in series form from each one of the five test points.

After passing through Data Selector 2, the test result is sent to a series/ parallel converter
and then onwards to a comparator, where it is compared with the correct value obtained from
the memory (12 bits) and Register 1 (4 bits). If the compared values are not alike, then this
will be indicated by light diodes on the TEST CIRCUITS 2 board. At the same time, the "-
TESTFEL" signal is yielded. The light diodes indicate the source of the faults. The fault
indication will remain until the fault has been rectified or until the result register has been
reset.

After all the test results have been checked, the counter will stop and furthermore, the
"TEST" signal will cease. Data Selector 3 selects the real control and logic signals to the
signal processing circuits.

The synthetic video for the Indicator is blocked on the TIME ALIGNMENT, JAMMER
BEARING INDICATOR board by the "-TRLB2" signal during the whole time that "TEST"
is being emitted and even for 30 PRF periods after "TEST" has ceased. When the video is no
longer being blocked, the functional supervision will be concluded and the SPU will resume
its normal function.

The logic circuit at the bottom of the diagram controls two of the input signals (A 40 KM, -
A PRFVX) to Data Selector 3.

The logic circuit controls that the staggered filters in the reciever allways are chosen, in 40
km mode.

In the tables on the right hand side of the diagram, it could be found to which diagram the
signal is fed, the name on the PCB and pin number of the inlet.