DA FOR FIR FILTERS

Chapter 1:

INTRODUCTION

In the recent years, there has been a growing trend to implement digital signal processing
functions in Field Programmable Gate Array (FPGA). In this sense, we need to put great effort in
designing efficient architectures for digital signal processing functions such as FIR filters, which
are widely used in video and audio signal processing, telecommunications and etc.

Traditionally, direct implementation of a K-tap FIR filter requires K multiply-and-

accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity
and resource usage. To resolve this issue, Croisier first presented DA, which is a multiplier-less
architecture. This technique is based on using 2's complement binary representation of data, and
the data can be pre-computed and stored in LUT. As DA is a very efficient solution especially
suited for LUT-based FPGA architectures, many researchers put great effort in using DA to
implement FIR filters in FPGA.

Partrick Longa introduced the structure of the FIR filter using DA algorithm and the
functions of each part. Sangyun Hwang analyzed the power consumption of the filter using DA
algorithm. Heejong Yoo proposed a modified DA architecture that gradually replaces LUT
requirements with multiplexer/adder pairs.
The main problem of DA is that the requirement of LUT capacity increases exponentially
with the order of the filter, given that DA implementations need 2Kwords (K is the number of
taps of the filter). And if K is a prime, the hardware resource consumption will cost even higher.
To overcome these problems, this paper presents a hardware-efficient DA architecture.
This method not only reduces the LUT size, but also modifies the structure of the filter to
achieve high speed performance.
The proposed filter has been designed and synthesized with ISE 7.1, and implemented on
a 4VLX40FF668 FPGA device. Our results show that the proposed DA architecture can
implement FIR filters with higher speed and small resource usage in comparison to the previous
DA architecture.

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Chapter 2:
FILTERS
A system or network that selectively changes characteristics of a signal is a filter.
There are 2 types of filters.
• Analog filter
• Digital filter
Analog Filter:
Analogue filters are a basic building block of signal processing much used in electronics.
Amongst their many applications are the separation of an audio signal before application
to bass, mid-range and tweeter loudspeakers; the combining and later separation of multiple
telephone conversations onto a single channel.
Some of the examples are
Simple filters. The frequency dependence of electrical response was known for capacitors
and inductors.
Image filters. Image filter theory grew out of transmission line theory and the design
proceeded in a similar manner to transmission line analysis.
Network synthesis filters. The mathematical bases of network synthesis.
Digital filter:
Digital Filters can be very complicated devices, but they must be able to map to the
difference equations of the filter design. This means that since difference equations only have a
limited number of operations available (addition and multiplication), digital filters only have
limited operations that they need to handle as well. There are only a handful of basic components
to a digital filter, although these few components can be arranged in complex ways to make
complicated filters.
There are two types of filters in the digital realm:
• Infinite Impulse Response (IIR) filters
• Finite Impulse Response (FIR) filters

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Infinite Impulse Response (IIR) filters:

IIR filters are harder to design than the FIR filters, but the benefits are extraordinary: IIR
filters are an order of magnitude more efficient than an equivalent FIR filter. Even though FIR is
easier to design, IIR will do the same work with fewer components, and fewer components
translate directly to less money. IIR filters differ from FIR filters because they always contain
feedback elements in the circuit, which can make the transfer functions more complicated to
work with.

The transfer function of an IIR filter contains both poles and zeros. Its impulse response
never decays to zero (though it may get so close to zero that the response cannot be represented
with the number of bits available in the system).

Finite Impulse Response (FIR) filters:

Finite impulse response (FIR) filters are the most popular type of filters implemented in
software. This introduction will help you understand them both on a theoretical and a practical
level.

Simple filters are usually defined by their responses to the individual frequency
components that constitute the input signal. There are three different types of responses. A filter's
response to different frequencies is characterized as pass band, transition band, or stop band.

If we define the discrete time impulse function as

The response of an FIR filter to δ[n], denoted as h[n], will decay to zero after a finite
number of samples. The transfer function of an FIR filter contains only zeros and either no
poles or poles only at the origin.

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Chapter 3:
DISTRIBUTED ARITHMETIC
Distributed Arithmetic is one of the most well-known methods of implementing
FIR filters. An FIR filter of length K is described as:

Where h[k] is the filter coefficient and x[k] is the input data. For the convenience
of analysis, x'[k] =x[n - k] is used for modifying the equ. land we have:

Then we use B-bit two's complement binary numbers to present the input data:

Where xb[k] denotes the b th bit of x[k], x [k] e {O, i }.

Substituting 3 into 2 yields:

In equ.4, we observe that the filter coefficients can be pre-stored in LUT, and addressed
byxb [xb[O],xb[i],...,xb[K-i]].This way, the M\AC blocks of FIR filters are reduced to access and
summation with LUT.

Original LUT-based DA implementation of a 4-tap (K=4) FIR filter is shown in Fig3.

The DA architecture includes three units: the shift register unit, the DA-LUT unit, and the
adder/shifter unit.

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Figure 3. Original LUT-based DA implementation of 4-tap FIR filter

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Chapter 4:
PROPOSED DISTRIBUTED ARITHMETIC
4.1: Proposed DA-LUT unit
In Fig. 4.1.1, we can see that the lower half of LUT (locations where b3 = I ) is the same
with the sum of the upper half of LUT (locations where b3 = 0 ) and h[3]. Hence, LUT size can
be reduced 1/2 with an additional 2xilmultiplexer and afull adder, as shown in Fig.4.1.1

.
Figure 4.1.1. Proposed DA architectures for a 4-tap FIR filter (23-word LUT implementation of DA)

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By the same LUT reduction procedure, we can have the final LUT-less DA architectures,
as shown in Fig.4.1.2. The proposed DA-LUT unit dramatically reduces the memory usage, since
all the LUT units can be replaced by multiplexers and full adders. On other side, for the use of
combination logic circuit, the filter performance will be affected. But when the taps of the filter
is a prime, we can use 4-input LUT units with additional multiplexers and full adders to get the
tradeoff between filter performance and small resource usage.

Figure 4.1.2. LUT-less DA architectures for a 4-tap FIR filter

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4.2: Proposed DA architecture for high order FIR filters

As the filter order K increases, the LUT size (2K_words) grows exponentially. We can
divide the K-tap FIR filter into L groups of smaller filters ( K = L xM ). Hence the LUT size is
reduced to L x 2M -words, then we have:

We'd better set M=4, because only under this condition can we take optimal advantage
based on the 4-input LUT structure of FPGA, as shown in Fig.4.2. If we cannot obtain M=4 after
the calculation, we can use both the proposed DA-LUT unit and the original 4-input DA-LUT
unit to achieve our goal.

Figure 4.2 Proposed DA architectures for a K-tap (k=L X 4) FIR filter

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4.3: Proposed DA architecture for high speed implementation of FIR filters

The FIR filters consume B clock cycles to complete its functions once if we implement
them using the bit-serial DA architecture. We can use a full-parallel version of the DA
architecture to improve the design performance, as shown in FIG.4.3.
The DA-LUT units are copied B times and then we can look up these DA-LUT tables at
the same time. Hence the can the FIR filters using the proposed DA architecture consume only
one clock cycle to complete its functions once. But we have to note that, the resource usage
increase more than B times of the bit-serial one's, since we need to use pipeline registers and
additional adders. Whether we choose this architecture is tied to specification for a given
application, and basically depends on requirements in terms of filter performance and hardware
resource cost.

Figure 4.3. Proposed DA architectures for high speed implementation of FIR

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Chapter 5:
IMPLEMENTATION
To evaluate the performance of the proposed scheme, a 70-TAP low pass FIR filter is
implemented. The sampling frequency was defined at 40 MHz, the bandwidth of pass band
equaled 2 MHz and the precision for input and filter coefficient were 13 and 12 respectively.
Firstly, the prototype low pass FIR filter was designed using the McClellan-Parks design
algorithm. The impulse response and the frequency response are shown in Fig 5.1 and 5.2.

Fig 5.1- impulse response

Fig 5.2- Frequency response

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The 70-tap FIR filter had symmetrical structure, so we could reduce it to 35-tap.Then we
divided the 35-tap filter into 7 smaller filters each having 5-tap DA-LUT units. The 5-tap DA-
LUT unit could be implemented by a 4-input LUT with an additional 2 xl multiplexer and a full
adder. To validate the correct functionality of the full-parallel DA architecture, we copied each
5-tap DA-LUT unit 13 times to test whether we could get the final result every clock cycle or
not.
Finally, Hardware implementation was synthesized using ISE7.1 on a 4VLX40FF668
FPGA device. The sampling frequency fs of the input signal was 40 MHz, it had a carrier
frequency of 9 MHz and a bandwidth of 2 MHz As show in Fig 5, after mixed with cos(2πf0/fs)
the signal got into the filter.

Fig 5: simulation system

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Chapter 6:
HARDWARE
When distributed arithmetic techniques are employed in Field Programmable Gate Arrays
(FPGAs) to implement digital signal processing algorithms, performance levels achieved are
orders of magnitude greater than those obtained with traditional signal processors.
Over many years the size and performance of Field Programmable Gate Arrays (FPGAs)
have increased dramatically and many advantages have been made of their reconfigurable nature
and flexibility in their functionality. Some FPGAs also provide commonly used functions such as
carry logic and memory which simplify design. FPGAs can be used to implement many DSP
algorithms effectively. The common approach to using an FPGA to implement a DSP algorithm
has been to directly replace a processor, or array of processors. The motivation to perform this
migration has typically been the relatively low system performance (i.e. sample rates) achievable
by the sequential processors compared with a more parallel distributed arithmetic solution
possible in FPGAs.

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Chapter 7:
RESULT
The output is shown in Fig.7.we have got the final result every clock cycle.

Fig 7: output of the filter

We validated the result with a Mat lab code. To illustrate the merits of the proposed DA
architecture, the full parallel version of the original DA architecture was also implemented on a
4VLK40FF668 FPGA device. The results are listed in Table 1.
we can see in Table. 1, the performances go in favor of the proposed DA, mainly in
resources usage, and similar speed as well.

Table. 1. Hardware resources usage/frequency performance of the original DA and

proposed DA.

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Chapter 8:
FUTURE WORK

A Distributed Arithmetic (DA) for highly efficient multiplier-less FIR filter designed on
FPGA can be used for the following future application to obtain the High speed, highly efficient
less memory architecture.
 Telecommunications
 Wireless/satellite communications
 Video and audio processing
 Biomedical signal processing.

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CONCLUTION

This paper presents the proposed DA architectures for high-order filters. The
architectures reduce the memory usage by half at every iteration of LUT reduction at the cost of
the limited decrease of the system frequency. We also divide the high-order filters into several
groups of small filters hence we can reduce the LUT size also. As to get the high speed
implementation of FIR filters, a full-parallel version of the DA architecture is adopted.
We have successfully implemented a high-efficient 70- tap full-parallel DA filter, using
both an original DA architecture and a modified DA architecture on a 4VLX40FF668 FPGA
device. It shows that the proposed DA architectures are hardware efficient for FPGA
implementation.

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REFERENCE

 A.Croisier,D.J.Esteban,,M.E.Levilion,and V.Rizo, "Digital Filter for PCM Encoded

Signals", U.S.Patent No.3,777,130, 1973

 Partrick Longa, Ali Miri, "Area-Efficient Fir Filter Design on FPGAs using Distributed
Arithmetic" IEEE International Symposium on Signal Processing and Information
Technology, pp:248-252,2006

 Sangyun Hwang, Gunhee Han,Sungho Kang, Jaeseok Kim, "New Distributed Arithmetic
Algorithm for low power FIR Implementation", IEEE Signal Processing Letters, Vol.11,
No5, pp: 463-466,May, 2004

 Heejong Yoo, David V.Anderson, "Hardware-Efficient Distributed

o Arithmetic Architecture For High-order Digital Filters", IEEE
o International Conference on Acoustics, Speech and Signal Processing, Vol.5,pp:
125-128,March,2005

 Wangdian, Xingwang Zhuo "Digital Systems Applications and Design Based On Verilog
HDL", Beijin: National Defence Industry press 2006

 Mcclellan J.H. Parks, T.W. Rabiner, L.R. "A computer program for designing optimum
FIR linear phase digital filters":. IEEE Trans. Audio Electroacoust. Vol. 21, No.6,
pp:506-526, 1973.

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