A Software Radio Development Platform PCP2000

-Partnering ‘C6x with Virtex FPGA

M.Jian, S.R. Bai, K.T. Heng, W.H. Yung
Centre for Wireless Communications, National University of Singapore
20 Science Park Road, #02-34/37, TeleTech Park, Science Park II, Singapore 117674
baisr@cwc.nus.edu.sg

Abstract handling both GSM and W-CDMA modes. These two

modes share a common IF front-end and can be
Software Radios have been widely studied as a solution switched to each other by software reconfiguration.
to support multiple competing and incompatible air
interface standards in future wireless communications. One possible architecture is shown in Fig. 1, where the
However, the current state of the art in general purpose wide-band IF signal is digitised by an A/D converter. IF
digital signal processor (DSP) is inadequate to support processing including channel extraction, frequency
this concept. In this paper, a Programmable conversion and pulse shaping, are performed by the
Communications Processor platform (PCP2000), FPGA; while base-band processing including
partnering Virtex Filed Programmable Gate Array modulation/ demodulation, channel coding/decoding
(FPGA) with ‘C62x DSP Evm, is introduced to provide and speech encoding/decoding etc. realised in DSP.
an ideal platform towards developing high complexity
signal processing algorithms. As an example, the
implementation of a dual-mode GSM/W-CDMA
receiver based on software radio concepts is described. A/D Baseband
Converter Processing
IF Processing (demodulation
(channel extraction
1. Introduction frequency conversion
channel decode
Speech decode
Clock Gen. pulse shaping etc.) etc.)
The basic idea behind software radio is to move the Synthesizer
A/D converter as close as possible to the antenna and
realize all demodulation and signal processing functions Virtex FPGA
by software [1]. With this ideal architecture, a single PCP2000 Module 'C62x DSP
receiver could be reprogrammed to accommodate any Evm
standards by simply software reconfiguring the Fig. 1 Software Radio Receiver Architecture
platform.
Specifications of GSM and W-CDMA receiver are
Specialised digital signal processor is viable for given in Table 1 [3].
relatively narrow-band systems (say below 40kHz)
where the sampling rate is within the DSP manageable GSM
level [2]. However, it is too expensive for DSP to Channel spacing 200kHz
process at high data rate, resulting in high power Transmission bit rate 270.833kbps
dissipation. Hence, it is often more efficient for a Receiver sensitivity -102 dBm
dedicated engine to be used. This can be in the form of Required CNR for demodulation 9 dB
an ASIC which can be designed to minimise power, or
W-CDMA
another co-processor, specific to processing of certain
Channel spacing 5MHz
algorithms. However, for a multi-mode system, having
dedicated ASICs pertaining to a particular system is not Transmission bit rate 4.096Mc/s
desirable. A flexible solution in the form of a re- Spurious response at 10MHz ≥ 60 dB
configurable logic device FPGA is preferred instead. Adjacent channel selectivity at 5MHz ≥ 33 dB

In the project of developing a dual-mode GSM/W-
CDMA receiver, each of the physical layer function is
studied to some detail. Implementation complexities in
DSP and/or FPGA are measured and from there, a
decision is made for an optimised hardware/software
solution.
2. GSM/W-CDMA Dual-mode Receiver
The idea of this dual-mode receiver is to define and
realise a practical software radio architecture capable of
Table 1 Specifications of GSM and W-CDMA
Input bandwidth of IF signal from RF module is BW =
5MHz centered at fIF = 68 MHz, which covers one W-
CDMA channel. As shown in Fig. 2 and Fig. 3, the
sampling rates for GSM and W-CDMA are chosen to
be 16MHz and 16.384Mhz respectively.
GSM IF Processing
After A/D conversion, the digital IF signal will be
further converted to base-band by a digital mixer. To
 simplify the hardware complexity, the carrier frequency fractional conversion. The value at non-integer samples
fIF is chosen to be an odd multiple of a quarter of the are interpolated from the adjacent samples. After
sampling frequency as given in Eq (1). Thus, the mixer evaluation, linear interpolation is chosen as it is the
can be performed by multiplying the input signal with most efficient way with minimum computation.
the sequences [0 1 0 -1 …] and [1 0 -1 0 …] being
digital representations of the sin- and cosine signals at a To satisfy the GSM requirement, a compensation FIR
quarter of the sampling frequency. filter is used to attenuate the block signal at 200kHz.
n This filter is a simple 5-tap low pass FIR filter that has
fIF = fs, n = 1,3,5,... Eq (1) a further 10dB attenuation at 200kHz while keeping the
4 in band requirement.
[1 0 -1 0 ...]
W-CDMA IF Processing
2 H1(Z) 16
FIF=68MHz
Fs=16MHz For W-CDMA, the sampling frequency fS is chosen to
BW=5MHz
Mixer High decimation filter be 16.384MHz which is four times the chip-rate of W-
CIC
CDMA. As given in Fig.3, the 16.384MHz frequency is
H1(Z) 16
synthesized from the reference 16 MHz by a factor of
2
128/125. Numerical control oscillator (NCO) provides
[0 1 0 -1 ...] the 2.464 MHz reference to digitally mixed the
digitized IF signal down to base-band. The NCO used
H2(Z) 13/12 here is a simplified version with a look-up table size of
0.2708MHz
=1xBaud rate only 256 x 16 bits. Dithering technique is used to
Compensation Fractional Rate
FIR filter Conversion reduce the spurious in the NCO as well. The digital
To baseband mixer is a 8x8 multiplier and the pulse shaping matched
processing H2(Z) 13/12 filer is a 48-tap root raised cosine filter with roll-off
factor of 0.22.
Fig. 2 IF Architecture of GSM
As the IF processing functions are extremely power
NCO
hungry and timing critical, they are implemented on
(2.464MHz) FPGA. Table 2 below summarises the implementation
in terms of CLB counts of the Xilinx Virtex FPGA.
Pulse Shaping
FIF=68MHz Filter 16.384MHz GSM CLB Count
Fs=16.384MHz =4x4.096 chip rate
BW=5MHz Mixer
Digital Mixer 11
CIC filter 159
To Baseband
processing
Rate Converter 250
Pulse Shaping
Filter Compensation FIR filter 45
Total for I & Q channels 915
W-CDMA
Fig. 3 IF Architecture of W-CDMA Digital Mixer 60
Pulse shaping filter 516
In GSM, the desired channel will be extracted from the Total for I & Q channels 1161
5MHz wide-band signal, this is realized by filtering.
Other signals such as blockers and adjacent interfers Table 2 FPGA CLB Count of IF Processing Unit
may be much larger than the desired signal. This
demands that the filtering in IF processing should have GSM Base-band Processing
high attenuation outside the desired channel. On the
other hand, the sampling rate after the mixer is still very The GSM receiver base-band processing functions
high, and hence, filtering should be efficient for include the Channel Equaliser, De-interleaver, Channel
implementation. As a result, a Cascade Integer Comb Decoder and Speech Decoder. These functions are
(CIC) filter is selected [4]. The CIC filter is a recursive traditionally performed using a DSP such as the
FIR filter with linear phase response. The advantage of TMS320C54xx DSP. The simplified block diagram for
the CIC filter is that the CIC filter is multiplierless and the GSM Baseband processor is shown in Fig.4.
can therefore be implemented at very high speeds.
In the evaluation of processing complexity, a
Since the sampling frequency fs is not an integer times TMS320C6201 DSP was used. This processor offers a
of the baud rate fb=13/48 kbp/s in GSM, a digital maximum of 1600 MIPS using 2 sets of 4 independent
fractional conversion is necessary. The fractional processing units. Table 3 gives the processing
conversion rate is R=13/12. Interpolation technique is requirements of the various modules. The figures are
an efficient method that can be used to implement
computed for an active Traffic Channel (TCH) Slot
transmission, and the codes have been ‘C’-optimised. Synchronisation

Frame
Frequency Timebase
Synchronisation
Offset Offset

Syn-
chroniser FPGA Multipath
Searcher
I
Viterbi De- Channel Speech
Channel Viterbi Speech
Equaliser Interleaver Decoding Decoding RAKE Combing
Deformating Decoding Decoding
Q
si sq Di D q ci cq

Channel Channel
Estimator Estimation

Code generator
Fig. 4 GSM Receiver Base-band Functions (walsh and Gold codes)

Module MIPS Fig. 6 W-CDMA Receiver Base-band Functions

Viterbi Equaliser & 25.7
Channel Estimator Module CLB Count
Channel Decoder & DeInterleaver 9.6 DLL 987
Speech Decoder (Full-Rate) 0.6 Memory Interface 123
Speech Decoder 2.3 Total 1110
(Enhanced Full-Rate)
Total : 35.9 (FR) Table 4. FPGA CLB Count of W-CDMA Base-band
37.6(EFR) Processing

Table 3. Processing MIPS of GSM Base-band 3. Development Platform – PCP2000

Modules
W-CDMA Base-band Processing
The WCDMA receiver base-band processing functions,
as shown in Fig. 5 and Fig. 6, include Timing
synchronisation, Multipath Searcher, Delay Locked
Loop (DLL), RAKE receiver with Channel Estimation,
Channel Decoder and Speech Decoder.
Due to the high sampling rate, the multi-fingers RAKE
receiver, DLL and despreading unit, are implemented
on the FPGA. The remaining processing functions
which functions at lower data rate are implemented on
the DSP. The algorithms were not exhaustively studied
as the project concentrates on system architecture
design and dual-mode receiver feasibility study. Hence
the DSP processing requirement is not reported in this
paper. Table 4 gives the FPGA implementation results
of W-CDMA base-band processing.
The PCP2000 module plugs in with a ‘C62x Evm,
providing an ideal platform for the dual-mode receiver
implementation described in section 2. Fig. 7 shows a
picture of this module.
The processing core of this module is a Xilinx Virtex
series FPGA, supported by high-speed, high dynamic
range ADC, DAC, programmable clock management
circuit and dual-port SRAM. This module plugs in
nicely with TI’s ‘C5402, ‘C6211 DSK, ‘C62x/’C67x
and PCI2040, ‘C5410 Evm. Its programmable nature
allows for the exploration of various signal processing
techniques, hence providing a flexible solution for
software radio development.
The PCP2000 can also function as a standalone module
for general purpose digital circuit development,
providing a solution for fast ASIC prototyping. The
overall architecture of PCP2000 is given in Fig. 8.

Code generator
Features and hardware specifications of PCP2000 are
(Walsh and Gold codes) outlined as following.
si sq
ri FPGA
Delay Di Memory
rq Locked Dq Interface DSP
Loop A standard HQFP 240-pin socket is designed on the
PCP2000 module, hence it is able to support various
Virtex series FPGAs ranging from XCV300 to
Time
Based XCV800. It can also be extended to support Virtex-E
Counter and Virtex-EM series FPGA, which has the same IO
packaging.
Fig. 5 DLL Architecture

Fig . 7 PCP2000 Module
Fig. 8 Architecture of PCP2000
ADC/DAC
AD9042 is a high speed, high performance, low power
analog-to-digital converter, with maximum 41 MSPS,
providing 80 dB Spurious-free Dynamic Range
(SFDR). AD9762 is a 12-bit 125 MSPS digital-to-
analog converter.
Clock Management
A 16 MHz, ±1ppm Voltage Control Temperature
Compensating Crystal Oscillator (VCTCXO) is used as
a reference clock source. On board PLL frequency
synthesizer provides a programmable clock generator
from 4 MHz to 33 MHz. External clock source can be
used through standard SMA connector.
Dual-port SRAM
An 8kx16 bits dual-port SRAM is connected to the
FPGA as well as the DSP Evm to pass data between
FPGA and DSP. It can also function as the FPGA’s
external memory for signal processing functions that
have dedicated memory requirement.
CPLD
Xilinx XCR5064 CPLD is used as a controller for
FPGA configuration, PLL synthesizer programming,
memory address decoding and other glue logic design.
FPGA Configuration and Debugging
Two modes of configuration are designed for the
FPGA. The SelectMAP mode takes data from an
EPROM controlled by the CPLD device. The IEEE
1149.1 JTAG Boundary-Scan mode can perform
configuration and on-chip debugging through a
computer serial port.
Power Supply
Voltage conversion circuit on-board, enables the power
supply to be obtained from the DSP Evm or from a
standard PC power supply via 4-pin Molex connector.
RF Interface and Test Pins
A 28-pin header is defined to interface with the RF
module, which can be also used as generic test pins.
Conclusion and Future Work
Given the inadequacy of current general purpose DSP
to handle the software radio’s signal processing
requirements at high sampling rate, PCP2000,
partnering high performance ‘C6x DSP with Virtex
FPGA, appears to be an ideal platform for developing
high complexity signal processing algorithms. This
paper has introduced the implementation of a dual-
mode GSM/W-CDMA receiver on the PCP2000
platform, whose fully programmable nature offers the
clear benefit of interoperability across incompatible
communications systems.
The authors are currently engaged in developing
PCP2001 platform, i.e. developing multi-mode receiver
architecture based on software radio concept. In
addtion, research into FPGA dynamic re-configuration
is in progress and will be reported in future
publications.
Reference:
[1] Jeffery A. Wepman, “Analog-to-digital converters
and their applications in radio receivers”, IEEE
Communications Magazine, vol. 36, no.5, pp.39-45,
May 1995.
[2] James McCloskey, “Applications of VHDL to
Sorfware Radio technology”, IEEE, Verilog HDL
Conference and VHDL International Users Forum,
1998.
[3] M. Jian, W.H. Yung, S.R. Bai, “An efficient IF
architecture for dual-mode GSM/W-CDMA receiver of
a software radio”, Mobile Multimedia Communications,
IEEE international workshop, 1999.
[4] Eugene B. Hogenauer, ”An economical class of
digital filters for decimation and interpolation”, IEEE
Trans. On Acoust., Speech, Signal Processing, vol.
ASSP-38 no. 2, pp. 356-360, April 1981.