What is

POR, LVD and WDT

1
 Power-On Reset
Definition: Restoring a device, register, or memory to a predetermined state when power is
applied.

• Ensuring that the MCU starts at a known address with registers in defined state when power
is first applied.
• POR circuit is required to assert the RESET signal only when supply voltage has stabilised
reach a minimum required voltage.
• Clock oscillations should also be stabilised before asserting RESET signal.

• Failure to carry out a proper POR may result in registers and memory contents of MCUs in
undetermined/incorrect states. It can cause MCUs to fail or be in an unrecoverable state.

• External POR circuits (e.g. RC circuit) or internal POR circuit with voltage comparator and
timer to delay the RESET signal when voltage level is reached

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Power-On Reset (cont)
VCC [V]

Vdet

time
Internal
state in CPU Reset Reset Released
Reset
delay

VCC [V]

time

3
 Low-voltage Detection
• Definition: Detection of supply voltage cut-off and brownouts.

• It monitors the supply voltage and generates an internal Reset or Interrupt when
that voltage drops too low.
• In some cases, after voltage drops below a predefined value, the voltage is
monitored for a few clock cycles to ensure voltage drop is not due to
noise/glitches.
• The Reset or Interrupt can be used to safely power the system down or back up
memory before shutdown etc.

4
 Low-voltage Detection (cont)

VCC [V]
Brownout
5.0

Vdet Vdet = 3.8V ± 0.5V

2.7

Power supply cut-off

time
Internal
state in Reset Released CPU Reset Reset Released
Reset

Interrupt

5
 Watchdog Timer
• Used mainly to reset MCU during program runaway or other incorrect program
execution.
• When the WDT underflows, either a Watchdog Timer Interrupt or a Reset can be
generated.

• The application program could periodically reload the WDT timer before it
underflows to ensure that an interrupt or reset isn’t generated. If the program
goes out of control, this periodic reload would not happen. Therefore, the WDT
would generate either an interrupt or a Reset that would cause the application
program to revert to a known (safe or preferred) state.

6
 Watchdog Timer (cont)

Count = H’FF
(maximum)

Count = 0

Watchdog Overflows
Watchdog Timer starts User program resets WDT counter
or set to other values so that it
does not overflow

Internal Reset Signal

Reset Generated

7
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