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Recently, Gundlach et al. reported a mobility of 2.1 The layouts of the BC and TC TFTs are presented in
cm /V-s for organic pentacene thin film transistors 共TFTs兲
2 Figs. 1共a兲 and 1共b兲, respectively. The TFT fabrication started
from thermal growth of SiO2 gate dielectric of thickness t ox
with the on/off ratio as high as 108 . 1 These numbers compare
⫽290 nm and t ox⫽250 nm for BC for TC TFTs, respec-
very favorably with mainstream ␣-Si:H TFT technology.
tively, on a highly doped Si substrate, which served as a
Simple pentacene-based circuits such as five-stage ring os-
common gate electrode. The gate dielectric surface was
cillators with propagation delay of 73 sec have been
ozone cleaned and treated by a self-assembled octadecyltri-
demonstrated.2 A relatively simple technology with low gate
chlorosilane 共OTS兲 agent prior to the pentacene active region
dielectric and active layers deposition temperatures3 allows deposition. Such a treatment considerably improves penta-
fabricating organic TFTs on virtually any substrate including cene TFT performance.7 For the BC TFTs, gold was depos-
flexible ones, and therefore makes organic TFTs attractive ited on the gate dielectric and source and drain contact pads
for low-end circuits and large-area applications. Moreover, were patterned prior to the pentacene active layer deposition
organic TFTs are natural candidates to the drivers of organic from a commercially available pre-purified powder. In case
light emitting diodes 共OLEDs兲, which have already been of the TC TFTs, the source and drain contact pads were
used in high-resolution active matrix displays.4 formed by gold deposition on top of the pentacene active
Contemporary pentacene organic TFTs have different layer through a shadow mask. More details on the TFT fab-
designs. One of them is the so-called top source and drain rication process can be found elsewhere.8 The gate length L,
contact 共TC兲 TFT design, where both source and drain con- defined by the source-drain pads spacing, was 30 m for the
tact pads are deposited on top of an active layer through a TC TFTs and 20 m for the BC TFTs. The gate width W
shadow mask. The TC TFTs are the easiest to fabricate and 共contact pads width兲 was 220 m and the pentacene active
they showed superior characteristics over TFTs of other layer thickness was 50 nm for both types of TFTs.
designs.1 However, there is no suitable procedure to pattern We used an HP 4156B Precision Semiconductor Param-
the TC TFT active layer to isolate the devices from each eter Analyzer to measure the DC electrical characteristics of
other. TFTs of another design, where drain and source con- the TFTs. In order to minimize effects of environment on the
tact metal is deposited on the gate dielectric and patterned TFT characteristics,9 we placed our probe-station in a light
prior to the active layer deposition, are referred to as bottom isolated dry-nitrogen ambient. The pentacene active layer
source and drain contact 共BC兲 TFTs. A special procedure has was mechanically removed around the measured TFTs in
been developed to pattern nonchemically the TFT active order to minimize the drain current leakage.
layer between individual TFTs on a substrate.5
In this article we present a model simulating DC charac-
teristics of both TC and BC TFTs. We also present an III. MEASURED DC CHARACTERISTICS
equivalent circuit allowing us to simulate a highly nonlinear Figures 2共a兲 and 2共b兲 show the measured TC TFT output
source and drain series resistance for the BC TFTs. Prelimi- and transfer characteristics, respectively. The BC TFT
nary results for the TC TFT modeling were reported at current-voltage characteristics resemble those for the TC
ISDRS-99.6 TFTs. However, the BC TFTs have a highly nonlinear region
in the output drain current I D –drain-source voltage V DS
a兲
Electronic mail: neclip@rpi.edu characteristic at low V DS , as shown in Fig. 3. The TC TFT
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J. Appl. Phys., Vol. 88, No. 11, 1 December 2000 Necliudov et al. 6595
FIG. 1. 共a兲 Bottom source and drain and 共b兲 top source and drain pentacene
TFT layouts. FIG. 3. Measured output TC 共circles兲 and BC 共squares兲 TFTs characteris-
tics. The drain current is normalized to allow comparison of both TFT
characteristics. Drain-gate voltage V GS ⫽⫺60 V for both TFTs.
FET⫽ 0 冉 V GS ⫺V T
V AA 冊 ␥
, 共2兲
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6596 J. Appl. Phys., Vol. 88, No. 11, 1 December 2000 Necliudov et al.
FIG. 4. Modeling of TC pentacene TFT 共a兲 output and 共b兲 transfer charac-
teristics. Modeling parameters are listed in Table I.
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J. Appl. Phys., Vol. 88, No. 11, 1 December 2000 Necliudov et al. 6597
Mobility,
Gate length L, R S ,R D , cm2/V-s at 0 , Diode
TFT width W, m Ohm V T ,V V GS ⫽⫺60 V cm2/V-s ␥ V AA ,V
TC L⫽30 1⫻10 5
⫹5 ⫽0.22 10 0.45 3⫻10 5
¯
W⫽220
BC L⫽20 5⫻104 ⫹13 ⫽1.2 10 0.38 1.9⫻104 10
W⫽220
1
gate-voltage dependent mobility at high V GS reaches the mo- D. J. Gundlach, C. C. Kuo, S. F. Nelson, and T. N. Jackson, 57th Device
bility value ⫽1.1 cm2 /V-s extracted from the 冑 I d,sat⫺V GS 2
Research Conference Digest, June 1999, pp. 164–165.
H. Klauk, D. J. Gundlach, and T. N. Jackson, IEEE Trans. Electron De-
characteristic at high V GS . vices 20, No. 6, 289 共1999兲.
3
Y. Y. Lin, D. J. Gundlach, S. F. Nelson, and T. N. Jackson, IEEE Trans.
Electron Devices 44, No. 8, 320 共1997兲.
V. CONCLUSION 4
P. E. Burrows, G. Gu, and S. R. Forrest, Proc. SPIE 3363, 269 共1997兲.
5
H. Klauk, D. J. Gundlach, M. Bonse, and T. N. Jackson, 46th International
We presented the results of the TC and BC TFT DC Symposium of the American Vacuum Society Technical Program, 1999,
characteristic simulations by a gate-voltage dependent mo- p. 85.
6
P. V. Necliudov, M. S. Shur, D. J. Gundlach, and T. N. Jackson,
bility model. The model simulates both above- and below-
ISDRS—99 Proceedings, 1999, pp. 373–376.
threshold regimes of the TC and BC TFTs operation. Unlike 7
T. N. Jackson, Y. Y. Lin, D. J. Gundlach, and H. Klauk, IEEE J. Sel. Top.
TC TFTs, the BC TFTs exhibit nonlinearities in the output Quantum Electron. 4, No. 1, 100 共1998兲.
8
characteristics at low V DS . We attributed those features to Y. Y. Lin, D. J. Gundlach, S. F. Nelson, and T. N. Jackson, IEEE Trans.
Electron Devices 44, No. 8, 320 共1997兲.
the effect of nonlinear series resistances. We proposed an 9
P. V. Necliudov, M. S. Shur, S. L. Rumyantsev, D. J. Gundlach, and T. N.
equivalent circuit incorporating a pair of diodes in series Jackson, Symposium JJ, MRS Fall Meeting, 2000.
10
with the source and drain parasitic resistances to model the L. Torsi, A. Dodbalapur, and H. E. Katz, J. Appl. Phys. 78共2兲, 1088
measured BC TFT output characteristics. The diode ideality 共1995兲.
11
D. B. Slater, Jr., L. A. Larkin, G. M. Johson, A. V. Suvorov, and J. W.
factors were the fitting parameters. The proposed model al- Palmour, 53rd Annual Device Research Conf. Digest, University of Vir-
lowed us to obtain a good fit of the BC TFT output charac- ginia, 1995, p. 100.
teristic in the 0⬍ 兩 V DS 兩 ⬍60 V range. 12
P. V. Necliudov, S. L. Rumyantsev, M. Shur, D. J. Gundlach, and T. N.
Jackson, J. Appl. Phys. 共in press兲.
13
K. Lee, M. S. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device
Modeling for VLSI 共Prentice-Hall, Englewood Cliffs, NJ, 1993兲, pp. 301–
ACKNOWLEDGMENTS
316.
14
M. Shur and M. Hack, J. Appl. Phys. 55共10兲, 3831 共1984兲.
DARPA 共Program Monitor Dr. G. Henderson兲 has sup- 15
K. Lee, M. S. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device
ported this research under Contract No. N61331-98-C-0021 Modeling for VLSI 共Prentice-Hall, Englewood Cliffs, NJ, 1993兲, pp. 494–
via subcontract from Sarnoff Corporation. 512.
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