JOURNAL OF APPLIED PHYSICS VOLUME 96, NUMBER 12 15 DECEMBER 2004

Gated four-probe measurements on pentacene thin-film transistors:

Contact resistance as a function of gate voltage and temperature
Paul V. Pesavento, Reid J. Chesterfield, Christopher R. Newman, and C. Daniel Frisbiea)
Department of Chemical Engineering and Materials Science, University of Minnesota,
Minneapolis, Minnesota 55455
(Received 21 June 2004; accepted 20 August 2004)
We describe gated four-probe measurements designed to measure contact resistance in
pentacene-based organic thin-film transistors (OTFTs). The devices consisted of metal source and
drain electrodes contacting a 300-Å-thick pentacene film thermally deposited on Al2O3 or SiO2
dielectrics with a p-doped Si substrate serving as the gate electrode. Voltage-sensing leads extending
into the source-drain channel were used to monitor potentials in the pentacene film while passing
current during drain voltage 共VD兲 or gate voltage 共VG兲 sweeps. We investigated the potential profiles
as a function of contact metallurgy (Pt, Au, Ag, and Ca), substrate chemistry, VG, and temperature.
The contact-corrected linear hole mobilities were as high as 1.75 cm2 / V s and the film sheet
resistance and specific contact resistance were as low as 600 k⍀ / 䊐 and 1.3 k⍀ - cm, respectively,
at high gate voltages. In the temperature range of 50– 200 K, the pentacene OTFTs displayed an
activated behavior with activation energies of 15– 30 meV. Importantly, the activation energy
associated with the contact resistance showed no dependence on contact metal type at high gate
voltage. Also, the activation energies of the contact resistance and film resistance were
approximately the same. Above approximately 200 K and below 50 K, the mobility was essentially
temperature independent. © 2004 American Institute of Physics. [DOI: 10.1063/1.1806533]

I. INTRODUCTION measurements on pentacene OTFTs using a gated four-probe

technique, in which the channel potential is sensed at two
In the last few years, work by a number of research
points between the source and the drain. While this approach
groups has shown that the properties of the source and drain
does not provide the exquisite detail of a full potential map-
contacts in organic thin-film transistors (OTFTs) can have an
ping by KFM, it is relatively easy to implement and allows
important effect on the overall device performance.1–8 Ef-
variable-temperature resistance measurements without the
forts have been made to lower the contact resistances in OT-
need for a UHV-AFM. Four-terminal measurements on
FTs by doping the semiconductor at the metal-organic
a-Si:H TFTs have been extensively reported,12–15 and recent
interface6 or by increasing contact area by switching from
studies of field-effect transistors based on organic single
“bottom contact” to “top contact” device geometries.7,8 How-
crystals have also exploited four-probe geometries,16–19 but
ever, to date, there have been relatively few direct measures
so far there have been very few four-terminal measurements
of contact resistance in OTFTs. Jackson and co-workers re-
on OTFTs. Recently, Yagi et al. reported an initial study of
cently published transmission line studies that showed that
four-terminal pentacene OTFTs.20 Our work presented here
specific contact resistivities were approximately 40 k⍀ - cm
includes a full study of contact resistance in top contact pen-
for Au bottom contacts8 and 3 k⍀ - cm for Au top contacts7
tacene OTFTs as a function of gate voltage, temperature, and
on pentacene.
metal work function. In addition, we report the temperature
A powerful alternative to the transmission line method is
dependence of the contact-corrected linear mobility for pen-
to map the potential profile across operating OTFTs, as can
tacene films over the range of 4 – 300 K.
be done using Kelvin probe force microscopy (KFM).9–11
Sharp voltage drops, which are observed in the profiles,
highlight the resistive bottlenecks to current flow. For ex- II. EXPERIMENT
ample, large contact resistances lead to large voltage drops at
A. Sample preparation
the contact-semiconductor interfaces. Dividing the voltage
drop by the current yields the contact resistance. Recently 1. Substrate preparation
Nichols et al.9 and Puntambekar et al.10 have reported poten- Pentacene thin films were grown on silica and alumina
tial profiling of pentacene OTFTs by KFM. In addition, substrates purchased from Silicon Valley Microelectronics,
Burgi et al. have demonstrated potential mapping of poly- Inc (SVMI). The silica substrates consisted of 3000 Å of
thiophene OTFTs as a function of temperature, which allows thermal oxide on p-doped (Boron) silicon wafers. As re-
a better assessment of the carrier transport mechanisms at the ceived, the wafers had an oxide on each side: one side pol-
contacts and in the film.11 ished and the other unpolished. The polished side had a rms
Here, we report variable-temperature contact resistance roughness not more than 2 Å (typically ⬍1.5 Å) in a 5
⫻ 5 ␮m window as measured via atomic force microscopy
a)
Electronic mail: frisbie@cems.umn.edu (AFM). In order to use the wafers as backside gate elec-

0021-8979/2004/96(12)/7312/13/$22.00 7312 © 2004 American Institute of Physics

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 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
trodes, the oxide on the unpolished side was removed and an
ohmic contact was fabricated. First, to fabricate the gate
electrode, photoresist was spun on the polished side as a
protective layer. The wafers were then dipped in a hydrof-
luoric solution to strip the oxide from the unpolished side.
The photoresist was then stripped by an overnight acetone
soak, sonication in an acetone-methanol-isopropanol se-
quence, followed by a de-ionized water spin rinse/dry and an
O2 plasma clean. An ohmic gate contact was fabricated by
depositing 100 Å Al and 900 Å Au, then performing a rapid
thermal anneal at 450 ° C for 60 s to diffuse the Al into the
silicon. The gate oxide capacitance was measured to be ap-
proximately 10 nF/ cm2. The Al2O3 substrates consisted of
1500 Å of plasma-enhanced chemical vapor deposited
(PECVD) Al2O3 on p-doped (Boron) silicon wafers. As re-
ceived from SVMI, the alumina had a rms roughness of ap-
proximately 10– 20 Å in a 5 ⫻ 5 ␮m window via AFM. In
order to facilitate good film growth, the alumina was then
polished by Polishing Solutions International LLC via
chemical mechanical polishing until the rms roughness was
less than 2.5 Å. After polishing, the alumina thickness was
nominally 1330 Å ± 35 Å, being thicker at the center of the
wafer and thinner at the edges. Because the Al2O3 dielectric
was deposited on the polished side of the wafer and there
was no thermal oxide on the back, the fabrication of an
ohmic contact to the gate electrode backside required only a
metal deposition and a rapid thermal anneal. The gate oxide
capacitance was measured to be approximately 40 nF/ cm2.
2. Pentacene purification
Pentacene source material was purchased from Sigma-
Aldrich. It has been shown that source material purity is a
key issue in device performance. The as-received pentacene
was only 97% pure so it was purified in a temperature-
gradient sublimation apparatus similar to that used previ-
ously to grow single crystals of organic semiconductors.21,22
The experimental apparatus consisted of an outer quartz tube
approximately 60 cm in length and 5 cm in diameter
wrapped with heating tape and insulation. One end of the
tube was fed with an ultrapure carrier gas and the other ex-
ited to a mineral oil bubbler. A small inner quartz tube served
as a holder for the source, whereas another longer one served
as the location for material deposition. Key-operating param-
eters used to purify the material were carrier gas (Ar
99.999%), pressure 共1 atm兲, Ar flow rate 50 mL/ min),
source temperature 共280– 290 ° C兲, and deposition tempera-
ture (approximately 250 ° C). The sublimed material was de-
posited in several distinct bands, those with higher sublima-
tion temperatures depositing first and those with lower
sublimation temperatures traveling further down the tube.
Purified pentacene deposited approximately 10– 15 cm
downstream from the source. The first crop of pentacene was
harvested from the growth tube and was used as the source
material for a second gradient sublimation. A total of three
sublimations were carried out and the final purified material
was used as the source for the thin-film evaporations.
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Pesavento et al. 7313
3. Pentacene film deposition
The growth of pentacene thin films was accomplished
via vacuum sublimation. The experimental apparatus con-
sisted of a vacuum thermal evaporation system from Denton
Vacuum (model DV-502) equipped with a diffusion pump, a
Radak I source furnace from Luxel Corp., and a water cooled
and resistively heated copper substrate block. Cartridge-type
heaters from Watlow were employed for substrate block
heating. The temperature of the substrate block was mea-
sured by a K-type thermocouple embedded within the sub-
strate block and controlled by a Eurotherm on/off style tem-
perature controller. Substrate temperature was held within
approximately ±1 ° C of the desired deposition temperature.
The purified pentacene source charge was placed in an alu-
mina crucible and loaded into the Radak furnace. The silica
and alumina substrates were cleaved into approximately 1
⫻ 1 cm pieces. Silicon dust generated by the cleaving pro-
cess was blown from the surface by a stream of dry nitrogen
gas. Silicon and dust particle removal was verified by AFM.
Stainless-steel shadow masks were clipped to the samples to
define the area of deposition. Film masking was performed
to reduce leakage current to the gate and to provide the
proper potential probe alignment, as described afterwards.
The thickness during deposition was monitored in situ via an
Inficon quartz crystal microbalance (QCM) thickness mea-
surement system. The shutter was kept closed until the
source temperature was approximately 120 ° C. Key-
operating parameters of the deposition process were chamber
pressure (typically 1 ⫻ 10−6 and 4 ⫻ 10−7 Torr at the start and
end of deposition, respectively), substrate temperature
共80 ° C兲, source temperature (150 and 180 ° C at the start and
end of deposition, respectively), deposition rate
(⬍0.1 Å / s for the first 60 Å, slow ramp to 0.4 Å / s by
100 Å, then 0.4 Å / s to 300 Å), and final thickness
共300 Å兲. Immediately after reaching a thickness of 300 Å,
the shutter was closed and substrate heating was terminated.
The substrate reached 25 ° C in approximately 5 min.
4. Metal contact deposition
Deposition of the top contact metal electrodes (Au, Pt,
Ag, and Ca) was accomplished via thermal evaporation. Au
and Pt were deposited in a turbo-pumped vacuum thermal
evaporation system from Denton Vacuum (model Benchtop
Turbo III), which was equipped with a wound tungsten fila-
ment source from R. D. Mathis and a water-cooled substrate
block. Ca and Ag, being more reactive, were deposited in a
custom built cryo-pumped vacuum thermal evaporation sys-
tem equipped with a Radak II source furnace from Luxel
Corp. and a water-cooled substrate block. Etched silicon
shadow masks were clipped to the samples to define the area
of contact deposition. Thickness during the deposition was
monitored in situ via a QCM from Inficon. The key-
operating parameters of the deposition process were chamber
pressure (Au and Pt: 2 ⫻ 10−6 and 5 ⫻ 10−6 Torr at the start
and end of deposition, respectively, Ca and Ag: 1 ⫻ 10−7 and
5 ⫻ 10−7 Torr at start and end of deposition, respectively)
and substrate temperature 共25 ° C兲. For Au, Ag, and Ca, the
deposition rate was 0.1 Å / s for the first 10 Å, then ramped
 7314 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
FIG. 1. (a) Schematic cross section of inverted-staggered (top contact) de-
vice geometry. Also shown are the potential probe positions at 1 / 3 L and
2 / 3 L. (b) Optical micrograph of the completed OTFT device structure
showing the dielectric, patterned film, source and drain electrodes, and chan-
nel potential probes. (c) Circuit schematic for the gated four-probe TFT
measurement configuration. Channel dimensions are W = 1000 ␮m, L
= 100 ␮m, LV1 = 33 ␮m, and LV2 = 66 ␮m. During ID-VG sweeps, the source
electrode is held at ground and VD is held constant as VG is swept. Current
into the source and out of the drain electrodes is monitored. The channel
potential is measured via high-impedance 共⬎1014 ⍀兲 electrometers. Also
shown is the close alignment of the film to the potential probes which
ensures that the potential monitored at V1 and V2 is only that of the channel
region.
to 0.4 Å / s for 50– 400 Å. For Pt, the deposition rate was
held at approximately 0.05 Å / s during the entire deposition
to minimize heating effects on the pentacene film due to the
high source temperature. For Pt, Ca, and Ag, all metals were
capped with a layer of Au. The thicknesses used in each case
were Au 共400 Å兲, Pt:Au 共50: 350 Å兲, Ca:Au 共200: 200 Å兲,
and Ag:Au 共200: 200 Å兲. Ca and Ag were capped with Au to
prevent oxidation, whereas Pt was capped with Au to create
a mechanically robust contact because of difficulties in
evaporating greater thicknesses of Pt. Figure 1(a) depicts the
final bottom gate, inverted-staggered (top contact) TFT con-
figuration with the in-channel probes used to measure the
channel potential of the operating TFT. Figure 1(b) shows a
top view optical microscope image of the completed device
(width and length of the device active area are 1000 and
100 ␮m, respectively). Figure 1(c) illustrates how the chan-
nel probe contacts were aligned with the edge of the masked
pentacene film. Here, the potential probes only contact the
film directly in and near to the channel area. If the probes
were allowed to be in electrical contact with the film in areas
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Pesavento et al.
other than in or near the channel, the potential sensed by the
electrometers would include fringing field effects because
the potential sensed is an average of every portion of the film
with which the probes were in contact. Proper positioning of
the channel probes ensures only the channel potential is
reported.
B. Film characterization
Characterization of the pentacene thin films was carried
out by AFM and X-ray diffraction (XRD) under ambient
conditions. AFM imaging of film morphology was accom-
plished with a Digital Instruments Dimension 3100. Topog-
raphy and amplitude images were acquired while imaging in
Tapping Mode with scan sizes of 10– 20 ␮m and a scan rate
of 2 Hz using NSC12 “B” cantilever tips purchased from
MikroMasch. The “B” cantilever typically tuned at a reso-
nant frequency near 350 kHz.
XRD was used to determine the film d-spacing and
phase composition using a Siemens D500 X-ray diffracto-
meter with a Cu K␣ 共1.54 Å兲 X-ray source. The samples
were approximately 1 ⫻ 1 cm2 in size with a pentacene film
deposited across the entire surface. The line source X-ray
beam struck the sample with an approximate beam of size
1 cm⫻ 1 mm. Standard ␪-2␪ scans were acquired from 3° to
31° 2␪ at a step size of 0.05° 2␪ and a dwell time of 4 s / step.
The number of counts at the maximum of the thin-film phase
peak was typically within the range of 1 ⫻ 104 – 3 ⫻ 104
counts for a 4 s dwell time. All the XRD data analysis was
performed in the software package JADE from Materials
Data, Inc.
C. Electrical measurements
1. Current-voltage characterization
Electrical characterization was carried out by sweeping
the drain voltage 共VD兲 at a constant gate voltage 共VG兲 or
sweeping VG at a constant VD while monitoring the drain
current 共ID兲 and probe potentials 共V1 , V2兲. Figure 1(c) illus-
trates the electrical connections for the completed gated four-
probe structure. Keithley 236 source-measure units were
used to apply VD and to measure the source 共IS兲 and drain
currents. Keithley 6517A high-impedance 共⬎1014 ⍀兲 elec-
trometers were used to monitor V1 and V2 via channel probes
and to source VG. All leads except the gate used guarded-
shielded triaxial cables instead of shielded coaxial cables to
minimize electrical noise and leakage currents. A computer
connected to all instrumentation via a general purpose inter-
face bus running custom National Instruments LabView code
was used to control the operation of all units. The data were
exported to and analyzed in custom MATLAB code. Typical
ID – VG parameters used are as follows: for Al2O3 dielectric,
VD = −4 or −5 V, VG = + 10– −40 V or 0 – −50 V, voltage
step= 0.5 V, sweep rate ⬃1 s / step when ID ⬍ 10−9 A and
⬃0.25 s / step when ID ⬎ 10−9 A, COX = 40 nF/ cm2; for SiO2
dielectric, VD = −10 V, VG = + 25– −75 V or 0 – −100 V, volt-
age step= 2 V, and COX = 10 nF/ cm2, all other parameters
were the same as for Al2O3.
 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004 Pesavento et al. 7315

2. Variable-temperature transport measurements

All variable-temperature characterization was carried out
in a turbo-pumped Desert Cryogenics vacuum probe station
in ambient light with a chamber base vacuum in the
10−6 – 10−7 Torr range. No noticeable differences were ob-
served upon operating the devices in the dark. The devices
were left in vacuum overnight before characterization began.
Beginning at room temperature 共295 K兲, the temperature was
decreased to 280 K, then down to 10 K in steps of 10°, fi-
nally reaching 4.2 K. After the completion of characteriza-
tion at 4.2 K, the temperature was increased back to 295 K,
checking the devices at several temperature intervals to en-
sure that their performance was not affected by the tempera-
ture cycling. Data from the devices that underwent signifi-
cant degradation were excluded from the study.

III. RESULTS
A. Structural characterization: AFM and XRD
Figure 2 shows AFM topographs of pentacene thin films
deposited on (a) dry, thermal SiO2 and (b) PECVD Al2O3 at
a substrate temperature of 80 ° C. There are several distinct
differences in the film morphology on the two different sub-
strate dielectrics. On Al2O3, the grain size is larger than on
SiO2, the grains appear more angular, the width-to-height
aspect ratio (W:H) is greater by approximately a factor of 8
共W : H = silica− 10 ␮m : 40 nm; alumina− 40 ␮m : 20 nm兲,
and cracking is evident to a greater degree. Close examina-
tion of individual grains reveals a distinct layered structure.
Terrace heights of each layer 共17.5± 4 Å兲 examined by AFM
agree within experimental error with XRD measurements
given afterwards.
Figure 3 shows the diffraction spectrum of a
340-Å-thick pentacene film on Al2O3 and SiO2. The two FIG. 2. AFM topographs of pentacene thin films deposited at a substrate
commonly listed “thin-film” phases were present at 2␪ val- temperature of 80 ° C on (a) SiO2 and (b) Al2O3. Films grown on (b) Al2O3
ues of 5.72° and 6.12° with corresponding d-spacings of 15.4 substrates (that have not seen any processing) show large grains which have
a larger width-to-height aspect ratio and show sharper facets than films
and 14.4 Å, respectively (the bulk structure of pentacene23 grown on (a) SiO2 (that has been exposed to photoresist). Both show evi-
has a d-spacing of 14.1 Å). The areas of the individual dif- dence of cracking due to thermal-expansion differences between the film
fraction peaks indicated that the film was largely composed and the substrate when cooling from 80 ° C to room temperature after film
of the 15.4 Å phase (74.8% on Al2O3 and 85.8% on SiO2). deposition. Maximum grain sizes observed on (a) SiO2 and (b) Al2O3 are
approximately 10 and 40 ␮m, respectively.

B. Electrical measurements
1. Current-voltage characterization
In order to examine the effects of metal work function
on contact resistance in pentacene OTFTs, we studied the
current-voltage characteristics using Au, Pt, Ag, and Ca top-
contacted devices. The metals were found to fall in two cat-
egories: those that produced low-resistance contacts (Au, Pt,
and Ag) and high-resistance contacts (Ca). In Figs. 4–9, Au-
and Ca-contacted devices have been chosen to illustrate ex-
amples of low- and high-resistance contacts, respectively.
Figure 4 shows the output characteristics 共ID – VD兲 and trans-
fer characteristics 共ID – VG兲 of OTFTs consisting of a penta-
cene thin film deposited on SiO2 and Al2O3 dielectrics with
Au and Ca top contacts. In Figs. 4(a) and 4(b), there are two
major differences between Au and Ca top-contacted devices
on SiO2 and Al2O3. First, the magnitude of the current at
high VG produced by the devices with Ca contacts is signifi-
cantly less than the devices with Au contacts [ID for Ca con-
tacts is scaled by a factor of 5 ⫻ 共SiO2兲 and 10⫻ 共Al2O3兲 for
visibility]. Second, the Ca-contacted devices exhibit greater
current hysteresis between forward and reverse drain voltage
sweeps, indicating increased charge-carrier trapping.
Devices fabricated on SiO2 obey a nearly ideal square-
law behavior in saturation (i.e., IDSAT ⬀ VG2), as shown in
Fig. 4(a), whereas devices fabricated on Al2O3 show devia-
tions at high VG, as evident in Fig. 4(b). Linear field-effect
mobilities for Au-contacted and Ca-contacted devices on
Al2O3 are 1.75 and 0.6 cm2 / V s, whereas for the devices on
SiO2, mobilities are 0.5 and 0.25 cm2 / V s, respectively.
Thus, part of the differences in the maximum currents can be
ascribed to variations in film mobility. Although pentacene
films for all of our devices were deposited in the same man-
ner, we typically observed run-to-run variations in mobility
in the range of 0.2– 1.75 cm2 / V s on bare Al2O3 and SiO2.

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 7316 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004 Pesavento et al.

verse traces. Note that in the “on” region 共VG ⬎ V0兲, the for-
ward trace current is greater than the reverse trace current,
but in the “off” regime 共VG ⬍ V0兲, the opposite is true, i.e.,
the reverse trace current is greater than the forward trace
current. This behavior is indicative of carrier trapping in the
films.

2. Potential measurements

During the standard three-terminal current-voltage mea-

FIG. 3. Thin-film XRD (Log Counts vs 2␪) of pentacene thin films depos-
ited on SiO2 and Al2O3 dielectrics. The traces are displaced vertically for
clarity. Both thin-film phases are visible. Good film ordering is indicated by
the four additional higher-order peaks observed.
Figures 4(c) and 4(d) show that there are significant dif-
ferences in the onset voltages (V0, the gate voltage at which
free carriers are first present at the pentacene-insulator inter-
face) for the Au- and Ca-contacted devices. The V0 values
surements, the channel potential was monitored in situ at two
points in the channel via the potential probes. At a constant
VD, VG was swept and the channel potential was measured at
each VG step. Knowing the channel potential at two points,
V1 and V2, a linear extrapolation of the potential profile to
each contact was performed. From the difference between
the applied potential at each contact (VD = −4 V for Al2O3
and VD = −10 V for SiO2) and the extrapolated potential val-
ues for the contacts, the potential drops at the source and
drain, ⌬VS and ⌬VD, were calculated according to the fol-
lowing equations:

冋 册
for Au-, Ag-, and Pt-contacted devices were approximately
the same on both substrate dielectrics. It can also be seen that 共V2 − V1兲
⌬VS = V1 − L1 − VS , 共1兲
there is a large current hysteresis between forward and re- 共L2 − L1兲

FIG. 4. Current vs voltage plots for pentacene thin films with Au and Ca top contacts. (a) and (b) Drain current 共ID兲 as a function of drain voltage 共VD兲 at
different gate voltages 共VG兲. Note that for the Ca top contact devices, ID has been scaled by a factor of 5 ⫻ 共SiO2兲 and 10⫻ 共Al2O3兲 for visibility. Forward and
reverse sweep directions are indicated by the arrows for all plots. Each forward and reverse sweep was acquired in approximately 1 – 2 min for a total of
5 – 10 min per ID-VD set (at all VG). (c) and (d) Drain current 共ID兲 as a function of gate voltage 共VG兲. Forward and reverse sweeps were acquired in
approximately 1 – 2 min each.

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 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004 Pesavento et al. 7317

FIG. 5. Potential data and surface plots for devices with Au and Ca top contacts fabricated on Al2O3. (a) and (b) Potential data acquired via the channel
potential probes as a function of VG. Shown are the probe data, V1 and V2, along with the extrapolated contact potential differences at the contacts ⌬VS and
⌬VD. The positions of V0 and VT (forward sweep) are also indicated. (c) and (d) Surface plots of the channel potential as a function of gate voltage and position
within the channel (d). The continuous surface shows the values of the applied source and drain potential and the channel potentials V1 and V2. The solid and
dashed lines, VD,extrap and VS,extrap, on the left-front and right-rear faces of each plot represent the estimated film potential just after the source and drain
contacts. The differences between these values and the respective applied contact potential, VD and VS, represent the potential drops due to contact resistance
(valid at VG Ⰷ VD only).

⌬VD = VD − V2 + 冋 共V2 − V1兲

共L2 − L1兲
共L − L2兲 , 册
where VS, VD, V1, and V2 are the voltages at the source,
drain, and potential probes, respectively. L1, L2, and L are the
distances from the source electrode to the first potential
probe, the second potential probe, and the drain electrode,
respectively. Since we are also interested in examining the
potential drop across the film, we define
共V2 − V1兲
⌬VFilm = L,
共L2 − L1兲
where ⌬VFilm is the actual drain bias across the film (i.e., the
applied drain bias less the drops at the contacts).
Figures 5(a) and 5(b) represent plots of measured chan-
nel potentials V1 and V2 and calculated ⌬VS and ⌬VD as a
function of VG for Au and Ca top-contacted devices. Here,
the potential data are truncated just after V0, where the de-
vice initially begins to conduct. Before this point, the voltage
probes measure potentials (e.g., +100 V) that are outside the
共2兲
range of the applied source or drain biases. We believe that
these results from static charge buildup on the pentacene film
surface and in the cables of the measurement system while
the film is relatively nonconductive. As soon as an apprecia-
bly conducting channel is established, the probes report po-
tentials characteristic of the channel. Data on both SiO2 and
Al2O3 dielectrics show the same trends and, for brevity, only
plots for devices fabricated on Al2O3 are shown. The values
of V0 and VT for the same device are indicated on each fig-
ure. The top scales of the plots in Figs. 5(a) and 5(b) show
共3兲 the VG-induced carrier density for VG ⬎ V0. It is clear that at
all carrier densities, the voltage drops at the Ca contacts are
greater than the voltage drops at the Au contacts.
These data are visualized differently in Figs. 5(c) and
5(d), which show surface plots of channel potential as a
function of both channel position and gate voltage. In these
plots, a channel position of 0 and 100 ␮m corresponds to the
source and drain electrodes, respectively. The source elec-
trode is held at a potential of 0 V and the drain electrode is
held at −10 V for SiO2 and −4 V for Al2O3. Potential probes

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 7318 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004 Pesavento et al.

TABLE I. (a) Film resistance 共RFilm兲 and (b) total contact resistance 共RS
+ RD兲 in extrinsic and intrinsic units (in parentheses) for all contact metals
and substrate dielectrics examined. Extrinsic units for all values are in ohms
共⍀兲. Intrinsic units are given as (a) film sheet resistance 关RFilm共W / L兲
= ⍀ / 䊐兴 and (b) contact resistivity 关共RS + RD兲W = ⍀ - cm兴. Resistance values
were acquired at sample biases of: VG = −40 V and VD = −4 V for Al2O3,
VG = −75 V and VD = −10 V for SiO2.

(a)
Film resistance 共RFilm兲

Substrate Ca Ag Au Pt
共⍀兲 共⍀兲 共⍀兲 共⍀兲
共⍀ / 䊐兲 共⍀ / 䊐兲 共⍀ / 䊐兲 共⍀ / 䊐兲
Al2O3 2.50⫻ 105 (…) 6.00⫻ 104 1.00⫻ 105
共2.50⫻ 106兲 (…) 共6.00⫻ 105兲 共1.00⫻ 106兲
SiO2 5.00⫻ 105 2.00⫻ 105 3.00⫻ 105 1.50⫻ 105
共5.00⫻ 106兲 共2.00⫻ 106兲 共3.00⫻ 106兲 共1.50⫻ 106兲

(b)
Total contact resistance 共RS + RD兲

Substrate Ca Ag Au Pt
共⍀兲 共⍀兲 共⍀兲 共⍀兲
共⍀ - cm兲 共⍀ - cm兲 共⍀ - cm兲 共⍀ - cm兲
Al2O3 3.75⫻ 105 (…) 1.30⫻ 104 4.00⫻ 104
共3.75⫻ 104兲 (…) 共1.30⫻ 103兲 共4.00⫻ 103兲
SiO2 8.50⫻ 105 5.50⫻ 104 2.25⫻ 104 6.50⫻ 104
共8.50⫻ 104兲 共5.50⫻ 103兲 共2.25⫻ 103兲 共6.50⫻ 103兲

where i is S, D, and Film. Figures 6(a) and 6(b) for Au and

FIG. 6. Film resistance and source and drain contact resistances as a func-
tion of VG for devices with (a) Au and (b) Ca top contacts. For Au top
contacts, the contact resistance (at high VG) is approximately an order of
magnitude less than that for Ca top contacts.
1 and 2 were at 32 and 69 ␮m for the Au-contacted device
on Al2O3 and at 30 and 66 ␮m for the Ca-contacted device
on Al2O3. Each probe is approximately 5 ␮m in width. At a
given VG, the straight lines connecting the source, potential
probe 1, potential probe 2, and the drain give a qualitative
estimate of the channel potential profile. Also included is the
outline of a surface generated by extrapolating the potential
between potential probes 1 and 2 to the source and drain
positions. It is the difference between the extrapolated values
(VS,extrap and VD,extrap) and the applied potential at each con-
tact that gives us the values of ⌬VS and ⌬VD. From the
surface plots, it is easy to see that the Ca contacts induce a
much greater potential drop than do the Au contacts. Thus,
the contact effects in the pentacene OTFTs are significant,
being much larger for the reactive metal Ca than for the
noble-metal Au. Note also that ⌬VD ⬎ ⌬VS, contrary to what
has been observed in bottom-contacted polythiophene
TFTs.11
Ca top-contacted devices, respectively, show plots of resis-
tance as a function of gate voltage. Initially, at low VG, the
film resistance 共RFilm兲 and contact resistances (RD and RS) all
begin at large values of resistance with RD much larger than
RS. As VG is increased, the resistance of both the film and
contacts decrease rapidly and finally saturate. Note that the
data at low VG (less than VT) could be misleading because
when 兩VG − VT兩 ⬍ 兩VD兩, the device is in saturation and pinchoff
occurs. The depletion region associated with pinchoff intro-
duces a high-resistance region near the drain electrode, and
the potential profile across the film is not linear. The gated
four-probe technique presented here does not decouple the
resistance due to the saturation-induced depletion region
from the contact resistance. At low VG, RD is effectively a
combination of the two. The lowest observed contact resis-
tance was approximately 0.7 k⍀ - cm for Au top contacts and
Al2O3 dielectric. Table I summarizes the calculated room
temperature values of RFilm and the sum of the contact resis-
tances 共RS + RD兲 for devices on Al2O3 and SiO2 and with
contact metals Au, Pt, Ag, and Ca. Values are given in ex-
trinsic units and intrinsic units. Devices with Ag top contacts
on Al2O3 dielectrics consistently did not yield reliable de-
vices and were omitted.
4. Variable-temperature measurements

a. Current-voltage behavior. Figure 7(a) shows ID-VG

3. Contact resistance
With the knowledge of the total current flowing through
the device and the potential drops across the film and con-
tacts, the resistance of the source contact, drain contact, and
the film can be calculated using Ohm’s Law, Ri = ⌬Vi / ID,
plots at different temperatures for Au top-contacted devices
on Al2O3. All other devices yielded the same trend as the Au
top-contacted pentacene device fabricated on Al2O3 and, for
brevity, are not shown. As temperature was decreased from
295 to 4.2 K, several important changes were noticed in the

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 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
FIG. 7. (a) The temperature evolution of ID – VG curves from 295 to 4.2 K
for a device with Au top contacts fabricated on Al2O3. (b) V0 and VT as a
function of temperature for devices with Au and Ca top contacts fabricated
on Al2O3. Both V0 and VT remain fairly constant as the temperature de-
creases until approximately 100– 150 K, where they begin to increase
rapidly.
current-voltage characteristics. First, the on current in-
creased, peaked at approximately 270 K, and then decreased
by approximately four orders of magnitude by 4.2 K. Next,
noticeable shifts in V0 are also seen between the
ID-VG traces at different temperatures. Plots of V0 and VT as
a function of temperature for pentacene devices with Au and
Ca top contacts and Al2O3 substrate dielectric show these
changes in more detail in Fig. 7(b). It was observed that V0
and VT were nearly temperature independent until approxi-
mately 150 K and then increased rapidly as the temperature
decreased.
b. Mobility as a function of temperature. We examined the
contact-corrected film mobility as a function of temperature.
Figure 8(a) shows the linear field-effect hole mobility (cor-
rected and uncorrected for contact resistance) for a Au-
contacted pentacene TFT on Al2O3. As temperature is de-
creased, the most dramatic feature of the data is that both
traces remain constant (or increase slightly) and then drasti-
cally decrease below 200 K. Figure 8(b) and its inset show
Arrhenius plots of the same corrected mobility data shown in
Fig. 8(a). The slope in the 50⬍ T ⬍ 200 K regime (see inset)
yields activation energies in the range of EA ⬇ 15– 25 meV
for pentacene films on Al2O3 and 20– 30 meV on SiO2. Fig-
ure 8(b) also shows a third region of transport below ap-
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Pesavento et al. 7319
FIG. 8. (a) Uncorrected and contact-corrected linear mobilities as a function
of temperature for an Au top-contacted device on Al2O3 dielectric. (b) Ac-
tivation plot showing log linear mobility as a function of 1 / T. At very low
temperatures 共⬍40 K兲, the mobility appears to be nearly temperature inde-
pendent. The inset shows a close-up of the activated region from
50 to 295 K.
proximately 50 K where the mobility becomes nearly tem-
perature independent. All other contact metal and substrate
combinations yield the same trends.
c. Contact resistance as a function of temperature. Figure
9(a) shows RFilm, RS, and RD as a function of temperature for
a pentacene device with Au top contacts. The data in Fig.
9(a) reflect the resistance values found at the maximum VG
value at each temperature (i.e., in the linear region of device
operation). We observed for all devices that RFilm, RS, and RD
increase with decreasing temperature. For Au-, Ag-, and Pt-
contacted devices, the contact resistances were approxi-
mately an order of magnitude less than the film resistance
throughout the entire temperature range. For Ca-contacted
devices, the contact resistance is comparable to the film re-
sistance at all temperatures.
Figure 9(b) shows an Arrhenius plot of RD at varying VG
for the same Au-contacted device as in Fig. 9(a). Between
approximately 180 and 50 K, the resistance is activated and
then it saturates below 50 K (not shown). As VG is increased,
RD drops and the slope of the activated region decreases.
Data for RS and RFilm yield the same trend. If we now look at
how the activated region slope varies with applied gate volt-
age in Fig. 9(b), we can construct a plot of activation energy
 7320 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
FIG. 9. (a) Plot of RFilm, RS, and RD as a function of temperature for a device
with Au top contacts on pentacene thin films on an Al2O3 dielectric. (b)
Activation plot of log RD vs 1 / T at varying VG. Plots for all contact metal
and substrate dielectric combinations yielded similar behavior. (c) EA for the
film, source resistance, and drain resistance as a function of VG for Ca and
Au top-contacted devices fabricated on Al2O3.
as a function of gate voltage, as given in Fig. 9(c). We ob-
served that at moderate gate voltages, the activation energy
for Ca contacts was slightly larger than that for Au. For both
Ca and Au top contacts, the activation energy decreased with
increasing gate voltage. The value for Ca contacts decreased
faster than for Au such that, at the maximum gate voltage,
activation energy values for the film and contact resistance
were all within the range of 15– 25 meV on Al2O3. This is
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Pesavento et al.
somewhat different from the results obtained by Yagi et al.,
where an increased contact activation energy was observed.20
Remarkably, measurements performed with all contact met-
als yielded similar values. On SiO2, the activation energies
of the film and contact resistance at large VG were slightly
higher, 20– 40 meV, for all contact metals. Data gleaned
from an analysis of Au, Pt, Ag, and Ca top-contacted devices
fabricated on SiO2 is nearly identical and is not shown.
IV. DISCUSSION
A. Structural characterization: AFM and XRD
Before pentacene deposition, each substrate type was ex-
amined via AFM. It was observed that the adventitious par-
ticle density was approximately 1 per 5 ⫻ 5 ␮m area for
SiO2, whereas it was approximately 1 per 10⫻ 10 ␮m area
on Al2O3. An increased particle density increases the avail-
able sites for grain nucleation and can account for the differ-
ence in grain size if not the different appearance of the indi-
vidual grains. The grain shape and topography differences
are effects of processing that occurs during substrate prepa-
ration (i.e., the SiO2 film growth surface is exposed to pho-
toresist and solvent-cleaning procedures, whereas the Al2O3
surface is not). This was confirmed by growing films on
pristine SiO2 substrates (before the backside gate fabrication
step). Pentacene film growth on these SiO2 substrates was
nearly identical in grain size and shape to that on Al2O3.
Thus, surface cleanliness after processing is an important
factor in the resulting film morphology. Cracking is most
likely caused by the large thermal-expansion differences due
to the elevated substrate temperature and the subsequent
cooling to room temperature upon completion of the penta-
cene film deposition.
The thin-film phases visible with d-spacings of 15.4 and
14.4 Å are consistent with measurements performed by Buu-
choms et al.24 and Knipp et al.25 on films deposited at el-
evated substrate temperature. The integrated peak areas indi-
cated that the films consisted mainly of the 15.4 Å phase.
The smaller 14.4 Å peak in the XRD spectrum was typically
but not always accompanied by needle- or pyramid-like for-
mations (not shown) observed in AFM images. A high level
of structural ordering was present within the film, as is evi-
dent by the large number of higher-order reflections.
B. Bias stress and contact effects at room
temperature
The transport data in Fig. 4 shows ample evidence of
both bias stress and contact resistance effects in our penta-
cene TFTs. For example, the ID-VG traces in Figs. 4(c) and
4(d) display significant hysteresis ascribed to gate-induced
bias stress. Bias stress effects involve charge-carrier trapping
on a time scale faster than the total sweep time (approxi-
mately 1 – 2 min). As the forward sweep progresses, carriers
are captured in trapping sites simultaneously screening the
gate electric field, reducing the overall free-carrier concen-
tration, and creating scattering centers. This results in a shift
of V0 to larger VG as the sweep progresses which, in turn,
gives rise to a reduced ID upon reversing the VG sweep (be-
cause the difference VG − V0 is smaller in the reverse trace at
 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004 Pesavento et al. 7321

the same values of VG). It is evident that for our slow

sweeps, we observe V0 shifts of approximately 5 V for both
Au- and Ca-contacted devices. Pt and Ag devices showed
similar effects. Bias stress effects are well documented in
a-Si TFTs and have been reported by Knipp et al.,25 Matters
et al.,26 Yuan et al.,27 and Zilker et al.28 for pentacene TFTs.
Thus, there is significant trapping in pentacene films though
the nature of these traps is currently not known. We note also
that the larger off currents on the reverse VG sweeps is in-
dicative of slow extraction of trapped carriers.
In Figs. 4(c) and 4(d), there is also a noticeable differ-
ence in V0 between the two different metal contact types, Au
and Ca. The negative shift of V0, when comparing Ca- to
Au-contacted devices, is consistent with a larger barrier to
inject holes at the Ca-pentacene interface. However, a simple
energy level alignment at metal-pentacene contacts, as
shown in Fig. 10(a), is not accurate. Interface dipoles and
interface states have been found to exist at pentacene-metal
contact interfaces that strongly affect the metal and semicon-
ductor energy-level alignments.29–31 The role that these fac-
tors may play in charge-carrier injection and transport will be
discussed later.
Measurable contact resistance is present to varying de-
grees in all of our top-contact pentacene TFTs depending on
the contact metal type. The potential data in Figs. 5(a) and
5(b) show that finite potential drops (⌬VS and ⌬VD) exist at
the contacts for both Au- and Ca-contacted devices even at
high VG. In the case of Au top-contacted devices [Fig. 5(a)],
the final values reached at high gate voltages
(⌬VS = 0.35 V, ⌬VD = 0.38 V; at VG = −40 V) are relatively
small. However, for Ca top-contacted devices [Fig. 5(b)], the
deviation is greater (⌬VS = 0.93 V, ⌬VD = 1.32 V; at VG =
−40 V). The larger contact potential drops are more easily
seen in the surface-potential plots in Figs. 5(c) and 5(d). It is
noteworthy that for both devices, the drop at the drain is
greater than the drop at the source (only slightly for Au),
indicating it is more difficult to extract carriers from the film FIG. 10. Schematic of metal and pentacene energy-level alignments (a)
than to inject them. before contact,(b)–(e) after contact. (b) and (c) Ohmic and barrier contacts
The extracted resistance data shown in Figs. 6(a) and formed by the Au- and Ca-pentacene contact interfaces as constructed by
Mott-Schottky theory. (d) and (e) Au-pentacene and Ca-pentacene interfaces
6(b) illustrate that at large VG 共兩VG − VT兩 Ⰷ 兩VD兩兲, the transistor as modified by interface dipoles and interface in-gap states. If no interface
enters the linear regime where it obeys the gradual channel states were present, holes would be injected via path 1 into pentacene. In the
approximation, and RD approaches the same value as RS (but presence of interface states, holes may be able to travel through the barrier
remains slightly larger). Au-contacted devices were observed via path 2.
to have a contact resistance that is less by approximately an
order of magnitude than that of Ca-contacted devices at high in charge-carrier injection and transport will be discussed
VG. This was also the case when comparing Pt and Ag to Ca later. However, our essential finding is that the magnitude of
top-contacted devices. For Au- and Ca-contacted devices, the the contact resistance in organic semiconductor-based de-
RFilm difference is well within the device-to-device variabil- vices is a function of the contact metal and can be significant
ity with identical film growth conditions employed during enough, in the case of low work-function metals, to dominate
device fabrication. Comparing the observed source and drain device performance.
contact resistance with the total device resistance, it was
found that at high VG, the contacts account for approximately
C. Variable-temperature measurements
55% of the total device resistance for Ca-contacted devices
and 15% of the total device resistance for Au-contacted de- From Fig. 7(a), it is apparent that at large VG, ID first
vices. Possible origins for significant contact resistance seen increases then decreases with temperature. This is a feature
in these devices may include an injection barrier presented often seen in our variable-temperature measurements of or-
by nonohmic contacts, interface states, or a contribution due ganic semiconductors, suggesting at least two regimes with
to the series resistance of the ungated semiconductor layer differing transport mechanisms. The ID decrease with tem-
underneath the contacts. The role that these factors may play perature below approximately 270 K is indicative of an ac-

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 7322 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
tivated mechanism. Correspondingly, Fig. 7(b) shows a rapid
increase of V0 and VT as temperature decreased below
100 K. The decrease in drain current and shift in V0 and VT is
consistent with the trapping of gate-induced hole carriers.
Additional evidence for trap-limited transport is seen in the
variable-temperature mobility data.
In Figs. 8(a) and 8(b), the variable-temperature, contact-
corrected mobility data reveal three different regimes of
transport behavior, (1) below approximately 50 K, the mo-
bility is nearly temperature independent, (2) between ap-
proximately 50 and 200 K [see inset of Fig. 8(b)], the trans-
port is activated, and (3) from approximately 200 K up to
room temperature (see inset), the mobility is again relatively
temperature independent. In region 1, 4.2 K ⬍ T ⬍ 50 K, the
thermal energy of the system is very low
共0.36 meV⬍ kBT ⬍ 4.3 meV兲. At these extremely low tem-
peratures, most holes no longer have the necessary thermal
energy to escape from the traps in which they are localized.
Traps in pentacene TFTs have been modeled as distributions
of gap states with depths of several tens to hundreds of
meV.32 The most probable transport mechanism in this case
is no longer hopping out of the traps into a conducting band,
but rather a tunneling mechanism.33,34 At 4.2 K, the magni-
tude of the mobility is still quite high
共⬃0.005 cm2 / V s兲. The temperature dependence and the
high mobility suggest a large density of trap states. Region 2
illustrates a regime of activated transport extending from ap-
proximately 50 to 200 K. The activation energies observed
are consistent with the trapping and release of carriers from
an extremely shallow distribution of trapping states. The
slight difference in EA seen in the devices fabricated on the
two different dielectrics is most likely due to an altered trap
energy distribution caused by surface chemistry or surface
cleanliness differences. In region 3, as seen in Fig. 8(a) and
in the inset of Fig. 8(b), the mobility plateaus as the tempera-
ture is increased above approximately 200 K. The flattening
of the temperature dependence suggests that the thermal en-
ergy (approximately 17 meV at 200 K) has become compa-
rable to the trap energies in the film and that, consequently,
the fraction of trapped carriers is decreasing rapidly.
A central observation of this study is that while the ab-
solute value of contact resistance does depend on metal type
(e.g., Ca contacts are worse than Au contacts), the contact
resistance activation energies are nearly equal at large VG,
regardless of the metal type, and are essentially identical to
the activation energy of the film (see Figs. 8 and 9). Given
this, the activated behavior observed in Fig. 9 does not de-
rive from the potential barriers existing at the metal-
pentacene interface. The close correspondence of the activa-
tion energies for the film and contact resistances suggests
that the contact resistance arises from thermally activated
transport in the film near the contacts. We conclude that the
different contact resistances observed for dissimilar metals
arise from differences in the detailed structure of the various
metal-pentacene contacts. We elaborate on these issues fur-
ther, beginning with a consideration of how large the poten-
tial barriers are at metal-pentacene interfaces.
Figures 10(a)–10(c) show the energy-level alignments
and band-bending processes for the semiconductor pentacene
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Pesavento et al.
and the top contact metals, Au and Ca, before and after the
metal-semiconductor contact is formed; in drawing the dia-
grams, we have simply aligned the metal and semiconductor
Fermi levels. In Fig. 10(a), assuming pentacene is a hole
conductor, it is apparent that Au and Ca should form ohmic
and blocking contacts, respectively. In the case of Ca, one
expects the injected holes must surmount a large barrier
共⬃2.2 eV兲, as given in Fig. 10(c), and that the observed ac-
tivated behavior of the contact resistance would reflect this
large barrier. Given that the contact resistance activation en-
ergies extracted from our variable-temperature measure-
ments in Fig. 9 yielded barriers of 15– 40 meV, and that the
energies do not depend on the top contact metal utilized, this
simple electronic structure model is contradictory.
We believe that our data are better explained by a non-
idealized metal-pentacene contact interface. In detailed pho-
toemission studies, several major differences from the ideal
have been found to be present in real metal-organic inter-
faces. First, interface dipoles have been found to exist be-
tween the metal and organic layers, the magnitude and direc-
tion of which depend upon the metal utilized and the order of
the organic/metal deposition.29,30,35,36 For example, deposit-
ing Au on pentacene yields a −0.3 eV dipole, whereas depos-
iting Ca on pentacene gives a +0.35 eV dipole, as shown in
Figs. 10(d) and 10(e). The dipoles shift the energy-level
alignments of the metal-semiconductor interface and may in-
crease or decrease the existing injection barriers depending
on the dipole’s direction. The interface dipoles derive at least
in part from the interaction of the organic semiconductor and
the electron cloud tail present at the surface of a metal.37
Second, it was also found that the work function of very thin,
noncontinuous metal films deposited on pentacene can be
significantly less than that of the bulk metal.30 A 30 Å film of
Au on pentacene has a work function of 4.2 eV, whereas the
work function of bulk Au is 5.1 eV. Similarly, a 30 Å film of
Ag on pentacene has a work function of 3.8 eV compared
with 4.5 eV in the bulk. Thin films of the reactive metal Ca
deposited on pentacene, on the other hand, have work func-
tions that match the bulk metal (presumably because the Ca-
pentacene interface is abrupt). These differences also con-
tribute to additional energy-level misalignments from the
ideal case. Energy-level diagrams that take into account the
recent ultraviolet photoemission spectroscopy results are
shown in Figs. 10(d) and 10(e), which show that both Au and
Ca contacts to pentacene should be blocking with hole injec-
tion barriers of 1.0 and 1.7 eV, respectively.30 These large
barriers are not observed in our temperature-dependent mea-
surements, so the charge injection at the metal-pentacene in-
terface cannot be the limiting bottleneck. Thus, the devices
are not injection limited. This conclusion is also consistent
with the fact that the source and drain contact resistances are
comparable.
Another important consideration is the fact that the
metal-pentacene interfaces may not be sharp. Figure 11 [con-
tact (a)] shows an idealized metal-pentacene contact as is
often drawn in device schematics. However, the deposition
of metal at high temperatures on organic films may not result
in an abrupt interface, but rather, the metal may penetrate the
organic surface and create clusters of metallic and nonmetal-
 J. Appl. Phys., Vol. 96, No. 12, 15 December 2004
FIG. 11. (a) Illustration of the idealized metal-organic top contact with an
abrupt interface. (b) Metal-organic top contact with metal clusters inter-
mixed in the film thickness. (c) Top contact where the electrically continu-
ous metal contact reaches the semiconductor-dielectric interface and directly
contacts the conducting channel.
lic metal atoms (depending on size and geometry), as shown
in Fig. 11 [contact (b)]. This has been shown to be true in
studies of metals deposited on a small molecule38,39 and
polymer films,40 where noble metals tend to diffuse into the
film and form clusters, whereas lower work-function metals
chemically react with the organic layer and form a more
abrupt interface. Clusters, along with any chemical reactions
that might occur due to a highly reactive metal (such as Ca),
could form in-gap interface states, as indicated in Figs. 10(d)
and 10(e). If the distribution of interface states spanned the
width of the barrier, carriers which would ordinarily need to
be thermalized over the metal-pentacene barrier via path 1 in
Figs. 10(d) and 10(e) may be able to bypass the barrier by
tunneling or hopping through the in-gap states31 by path 2 in
Figs. 10(d) and 10(e). This effectively removes the barrier
from the hole injection process. Alternatively, path 1 could
still occur, but hopping in the film near the contact is the
rate-limiting step. Another possibility is that, during the
metal contact deposition, the incoming metal atoms may
penetrate the film completely to the dielectric surface, as
suggested in Fig. 11 [contact (c)]. If there exists a continuous
metal contact that reaches completely to the semiconductor-
insulator interface, the semiconductor-metal interface will be
in direct contact with the conducting channel and the width
of any injection barriers (and the rate of tunneling through
them) at the metal-pentacene interface could then be directly
modulated by the varying hole concentration yielding a
strongly VG-dependent contact resistance. Such a picture is
consistent with our observation that both the source and
drain contact resistances are strongly gate voltage dependent
(see Fig. 6). However, further investigation into what influ-
ence the extent of metal-organic intermixing has on contact
resistance properties is needed.
V. CONCLUSIONS
In conclusion, we have studied pentacene TFTs via gated
four-probe measurements as a function of contact metallurgy,
substrate chemistry, gate bias, and temperature. AFM and
XRD have shown the growth of highly crystalline films on
both Al2O3 and SiO2 dielectrics. We have demonstrated that
the source and drain contact resistances can be more than
half of the total device resistance for devices with a 10:1
W/L ratio, depending on the contact metal. For a low work-
function metal (Ca), the observed contact resistances can
cause the measured field-effect mobility to differ by up to a
factor of 2 from the contact-corrected film mobility. Even for
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Pesavento et al. 7323
Au contacts in a top contact configuration, the contact metal
and device geometry most often employed for high perfor-
mance pentacene TFTs, the contact resistance can reduce the
apparent linear field-effect mobility by 10%–15% for 300 Å
thick pentacene films. Specific contact resistances were
found to be in the range of 1.3– 85 k⍀ - cm at high gate bias.
Bias stress effects are strongly evident in ID-VG curves ac-
quired over 1 – 2 min. Variable-temperature measurements
over the range of 4.2– 295 K show that transport activation
energies for the contacts and film are essentially identical
and are small, on the order of 15– 40 meV, indicating that
the contact resistance is determined by transport in the film
in the vicinity of the contacts. Though the contact activation
energies do not depend substantially on metal type, the con-
tact resistances do depend on the metal. We suggest that this
is due to the details of the metal-pentacene interfacial micro-
structure, but more work is needed to determine the precise
connection between the structure of metal-pentacene inter-
faces and their transport properties.
ACKNOWLEDGMENTS
The authors would like to thank T. W. Kelley (3M) and
A. Kahn (Princeton) for helpful discussions and J. A. Merlo,
S. E. Fritz, and K. P. Puntambekar for equipment support.
This work was supported by the 3M Company and the NSF
Materials Research Science and Engineering Center Program
(DMR# 0212302).
1
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