©

R.Lauwereins
Imec 2001
Course contents

Digital
• Digital design
design
• Combinatorial circuits: without status
Combina-
torial
• Sequential circuits: with status
circuits

FSMD design: hardwired processors
Sequential
circuits
• Language based HW design: VHDL
FSMD
design

VHDL

4/1
©
R.Lauwereins
Imec 2001
FSMD design

Digital

FSMDs
design
• Models
Combina-
torial
• Synthesis techniques
circuits

Sequential
circuits

FSMD
design

VHDL

4/2
©
R.Lauwereins
Imec 2001
FSMD

Digital
• FSMD: Finite State Machine with Datapath
design
• FSMD = hardcoded processor
Combina-  Consists of a datapath that performs the
torial
circuits computations
 and a controller which indicates to the
Sequential
circuits datapath which operations have to be carried
out on which data
FSMD
design  The controller always executes the same
algorithm: hardcoded
VHDL
• A traditional ASIC consists of multiple
interconnected FSMDs

4/3
©
R.Lauwereins
Imec 2001
FSMD

Digital
design

Combina-
Data Data
torial inputs outputs
circuits
Datapath
Sequential
circuits

FSMD Control Status

design
signals signals
VHDL
Control Control
inputs outputs
Controller

4/4
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
 Datapath design
Combina-  Controller design
torial
circuits • Models
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/5
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
 Datapath design
Combina-  Controller design
torial
circuits • Models
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/6
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• Datapath
design
 Temporary storage: registers, register files,
Combina-
FIFO’s, …
torial
circuits
 Functional units: arithmetic and logic units,
shifters
Sequential
circuits
 Connections: busses, multiplexors, tri-state bus
drivers
FSMD
design

VHDL

4/7
©
R.Lauwereins
Imec 2001
Datapath design
2
Digital
design
Task: sum = ∑ xi
i =1
Combina-
torial
circuits
Algorithm: Processing
sum = 0
Sequential
circuits
FOR i = 1 TO 2
sum = sum + xi Control
FSMD ENDFOR
design y = sum

VHDL
Datapath construction rules:
•each variable and constant corresponds to a register
•each operator corresponds to a functional unit
•connect outputs of registers to input of functional
units; when multiple outputs connect to the same input:
MUX or bus with tristate drivers
•connect output of functional units to input
of registers; when multiple outputs connect to the same
4/8 input: MUX or bus with tristate drivers
©
R.Lauwereins
Imec 2001
Datapath design
Variables: sum Algorithm:
Output order: sum = 0
Digital
Operators: add ‘Reset’,’Load’, FOR i = 1 TO 2
design sum = sum + xi
Connections ’Out’
210 ENDFOR
Combina-
torial xi y = sum
circuits

Sequential
circuits Start 0 2
Wait Reset
Register
100 Load
FSMD
1 SUM
design Start=1 Clk
Add1
VHDL 010

Add2
010 Add

Output
001 0

4/9 y
©
R.Lauwereins
Imec 2001
Datapath design
Task: count the number of ‘1’s in a word
Digital
design
Algorithm:
Combina- Data = Inport || OCnt = 0 || Mask = 1
torial
circuits
WHILE Data <> 0 DO
Temp = Data AND Mask
Sequential OCnt = OCnt + Temp || Data = Data >> 1
circuits ENDWHILE
Outport = OCnt
FSMD
design

All instructions on a single line are executed concurrently:

VHDL
maximum speed, but highest cost

Trading-off speed for area is explained in the section on

‘Synthesis techniques’

All hardware components work in parallel. Implementing

hardware is hence not writing a sequential software
program and implementing this directly in hardware. Above
4/10 algorithm is a ‘concurrent’ description!
©
R.Lauwereins
Imec 2001
Datapath design
Data = Inport; OCnt = 0; Mask = 1
WHILE Data <> 0 DO
Temp = Data AND Mask Output order:
OCnt = OCnt + Temp; Data = Data >> 1
Digital
543210
ENDWHILE
design Outport = OCnt

Combina-
torial
s=0 Inport
circuits
s Wait
x01x00
Sequential s=1
circuits
1 0
Load
5
FSMD 111x00
design
3R
Comp Data OCnt Mask Temp
VHDL 4 2 1
x00000
z=0 z=1

Temp Out
x00010 x00001
<>0 AND Add >>1 0
Update zero
010100
Outport
4/11
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• Possible optimisations:
design
 When the life time of 2 variables is non-
overlapping, both can be stored in the same
Combina-
torial register: register sharing
circuits
 When two operations are not executed
concurrently, they can be assigned to the same
Sequential
circuits functional unit: functional unit sharing
 When two connections are not used
FSMD concurrently, they can be shared: connection
design
sharing
VHDL  When two registers are not concurrently read
from resp. writen to, they can be combined into
a single register file: register port sharing
 Operations that could be executed
concurrently, may also be executed
sequentially, facilitating the four previous
optimisations

4/12
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• Generic structure of the datapath:
design
External input
Combina-
torial
circuits

Sequential
circuits
Temporary storage
FSMD
design

Operand switching network

VHDL

Functional units

Result switching network

External output
4/13
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• Typical datapath:
design
Inport

Combina- S 1 0
torial
circuits
WA
WE
Sequential RA1 Register
circuits RE1 File
R R
23
L Counter RA2 Register
FSMD C RE2 L
design
COE RFOE1 RFOE2 ROE

VHDL

Comparator F ALU Sh Barrel

D shifter
> = <
AOE SOE

OOE

Outport
4/14
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• In the datapath of previous slide a few
design
decisions have been taken:
Combina-  Only 1 i.o. 2 result busses ⇒ ALU and Barrel
torial
circuits
shifter cannot be used concurrently
 Only 2 i.o. 4 operand busses ⇒ e.g. Compare
Sequential
circuits
and ALU work on the same set of data
 9 registers with only 2 write ports and 3 read
FSMD ports
design
 Inport can only feed the register file
VHDL

4/15
©
R.Lauwereins
Imec 2001
Datapath design
Instruction format
Digital
design
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RF
Combina- RA2RA1RA0RE2 R L ROE F2 F1 F0 AOESH2SH1SH0 D SOEOOE
OE2
torial
circuits

Register File Barrel

Sequential Register ALU
circuits Read Port 2 shifter

FSMD 31 30 29 28 27 26 25 24 23 22 21 20 19 18
design RF
R L C COE S WA2WA1WA0 WE RA2RA1RA0RE1
OE1
VHDL
Register
Register File
Counter File
Read Port 1
Write Port
32-bit instruction word
For reasons of simplicity, clarity and correctness, it is
possible to assign a mnemonic to a certain bit pattern
(e.g. ADD): assembly instruction
4/16
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• The size of the instruction word may be
design reduced, since several operations cannot
be executed concurrently
Combina-
torial  Either Register File Read Port 2, either Register
circuits
Read Port connects to the 1st Operand Bus (-1)
Sequential  Either Register File Read Port 1, either Counter
circuits Read Port connects to the 2nd Operand Bus (-1)
 ALU & Shift cannot occur concurrently: 1 bit
FSMD
design needed to select the operator and 4 bits control
the operator (-2)
VHDL  When the ALU operator is active, its output
may immediately be placed on the result bus;
idem for the Barrel shifter (-2)
 For the counter the ‘Count’ and ‘Load’
operations are exclusive (-1)
• Additional limitations to concurrency may
be introduced at the cost of increased
4/17
execution time
©
R.Lauwereins
Imec 2001
Datapath design

Digital
• Design freedom
design Type Fixed To be designed speed cost design
time
Combina-
custom fixed - - custom custom ↑↑ ⇔ ↓↓ ↑↑
torial
circuits proc. algo DP Ctrl
soft IP fixed DP - DP custom ↑ ↔ ↓ ↑
Sequential algo ext. Ctrl
circuits ASIP algo DP Ctrl DP Ctrl ↓ ↔ ↑ ↓
class ext. ext.
FSMD µProc any DP Ctrl - - ↓↓ - ↑↑ ↓↓
design
algo

VHDL

A compiler performs the same tasks as synthesis tools

(e.g. assign variables without overlapping life time to
the same register) but with less degrees of freedom,
since the hardware is fixed

4/18
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
 Datapath design
Combina-  Controller design
torial
circuits • Models
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/19
©
R.Lauwereins
Imec 2001
Controller design

Digital
• The controller has been designed each
design
time using the design method for FSMs as
Combina- discussed before
torial
circuits • For a large number of states this is a
Sequential
tedious job
circuits
• Next slides present alternative design
FSMD methods, that lead to a faster design
design
process in several cases
VHDL

4/20
©
R.Lauwereins
Imec 2001
Controller design
Standard FSM
Digital
design

D Q
Combina-
torial Clk
circuits

Sequential
circuits S*=F(S,I)
D Q O=H(S,I)
FSMD Next Clk
design
Output
State
Combi-
Combi-
VHDL nato-
nato-
rial
rial
Logic
Logic
D Q
Clk

4/21
©
R.Lauwereins
Imec 2001
Controller design
Redrawn Control Status
Digital Signals (CS) Signals (SS)
design

Next CI SS
Combina- State
torial
circuits

Next
Sequential
circuits state
logic
FSMD Control Control
design Input (CI) Output (CO)
State
VHDL Reg
Size State Reg: CS
log2n for n states Out-
for straightforward put
Current logic
and State
CO
minimum-bit-change;
n for n states for
CI SS
one-hot
4/22
©
R.Lauwereins
Imec 2001
Controller design
Critical path delay:
Digital
Find the longest combinatorial path from clock
design to clock
Clk→OutStateReg + OutputLogic + AddressToOutRegFile +
Combina-
torial BusDriver + BarrelShifter +BusDriver +Mux +
circuits SetupInPortRegFile

Sequential
circuits Next
S1 0
CI SS
State
WA
FSMD
WE
Register
design Next RA1 File
R RE1 R
state
logic L Counter 23 Register
RA2 L
VHDL C RE2
COE RFOE1 RFOE2 ROE
State
Reg

Comparator ALU Sh Barrel

Out- CS F
put D shifter
> = <
Current logic
CO AOE SOE
State

CI SS OOE
Outport
4/23
©
R.Lauwereins
Imec 2001
Controller design
Modification 1 CS SS
Digital
design

One-hot CI Next CI SS
Combina- State
torial State
circuits reg
Next
Sequential
circuits state
Properties: logic
FSMD
* simple
design design and small log2n CO
State
next state and →n
Reg
VHDL output logic of dec.
one-hot CS
* small number of Out-
flip-flops of put
Current logic
straightforward State
CO
and minimum-
bit-change
CI SS

4/24
©
R.Lauwereins
Imec 2001
Controller design

Digital
• Modification 2
design
 Often the state diagram shows an
Combina-
unconditional sequence of states, but for a few
torial exceptions
circuits
 E.g.
Sequential
circuits
0
FSMD Wait
design 100
Start=1
VHDL
Add1
010

Add2
010

Output
001
4/25
©
R.Lauwereins
Imec 2001
Controller design
Modification 2
CS SS
Digital
design

Next CI SS
Combina- State
torial Next
circuits
State
Logic Next
Sequential
circuits state
logic
FSMD
design CI CO
MUX State
VHDL Reg

INC Out- CS
put
logic CO
Current
State
CI SS

4/26
©
R.Lauwereins
Imec 2001
Controller design

Digital
• Advantage of modification 2:
design
 The next state logic is very simple:
Combina- for unconditional next state: select
torial
circuits the INC
Sequential only for conditional next state the
circuits
hardware should generate the next
FSMD state
design
• Implementation of the INC:
VHDL
 ripple carry chain of Half Adders
 INC and State Reg together form a synchronous
counter

4/27
©
R.Lauwereins
Imec 2001
Controller design

Digital
• Modification 3
design
 Often the state diagram contains a part that is
Combina-
repeated several times ⇒ subroutine
torial
circuits

s0 s0
Sequential
circuits
s1
FSMD
s3
design s2
s4 5 states
VHDL s3
Only at run-time
s4 s1 it is known
which will be
s5 the next
state following
s6 the end of a
s2 subroutine
7 states ⇒ stack
4/28
©
R.Lauwereins
Imec 2001
Controller design
Modification 3 CS SS
Digital
design

Combina-
Next CI SS
torial State
circuits
Logic Next
State
Next
Sequential Push/ state
circuits
Pop’ logic
FSMD
design CI CO
Stack MUX State
VHDL Reg

Return Out- CS
State put
Current
State logic CO

CI SS

4/29
©
R.Lauwereins
Imec 2001
Controller design
Combination
CS SS
Digital
design
CI SS

Combina-
torial Next
circuits Push/ State
Next
Pop’ state
Sequential
circuits logic
Stack
FSMD Log2n
State
design MUX →n
CI Reg CO
Dec
VHDL
Out- CS
INC
put
Current
State logic CO

CI SS

4/30 Assumption: Return state = Jump state + 1

©
R.Lauwereins
Imec 2001
Controller design

Digital
• Implementation of the next state logic
design
and the output logic
Combina-  Either construct via Karnaugh a minimal AND-
torial
circuits
OR implementation
 Either put the truth table in a ROM-table (this
Sequential
circuits
method is called microprogrammed control)

FSMD
design

VHDL

4/31
©
R.Lauwereins
Imec 2001
Controller design
ROM table
CS SS
Digital
design
CI SS

Combina-
torial Next
circuits Push/ State
Pop’
Sequential
circuits

Stack
FSMD
State ROM
design MUX
CI Reg table CO
VHDL
CS
INC

CO
Current
State

4/32
©
R.Lauwereins
Imec 2001
Controller design
Be careful about timing!
Digital
design
Example: Each iteration of the
Combina-
ReadFromExternal(A); WHILE loop (body, test
torial || sum := 0; and decision) should be
circuits WHILE A <> 1 executed in just one
sum := sum + A; clock cycle!!
Sequential
circuits || ReadFromExternal(A);
Comp
FSMD A
design
LA LS
VHDL A sum
RS

C
Comp Add No 3-state
drivers: each
C=1 when A<>1 bus only has
one source
4/33
©
R.Lauwereins
Imec 2001
Controller design
Can the controller be state based?
Digital
design
Example: Animate sequence
ReadFromExternal(A); A=5,2,1 ⇒ sum=7
Combina-
torial || sum := 0; Reset is asynchronous
circuits WHILE A <> 1
sum := sum + A; One count too much
Sequential
circuits || ReadFromExternal(A); sum=8 i.o. 7

FSMD
design 5
2
1
? 5
7
8
?
s0 LA LS
VHDL LA=1 A=5
A=2
A=1
A=?
A Sum=0
Sum=5
Sum=7
Sum=8
Sum=?
sum
RS=1 RS
LS=0
C=1
s1
LA=1 Comp Add
RS=0
LS=1
C=0 5
7
8
?
C=1 when
C=1
C=0
C=? A<>1
4/34
©
R.Lauwereins
Imec 2001
Controller design
Can the controller be input based?
Digital
design
Example: Animate sequence
ReadFromExternal(A); A=5,2,1 ⇒ sum=7
Combina-
torial || sum := 0; Reset is asynchronous
circuits WHILE A <> 1
sum := sum + A;
Sequential Result is correct.
circuits || ReadFromExternal(A);
Always check timing!
FSMD
design 5
2
1
? 5
7
8
?
LA
LA LS
LS
s0
VHDL LA=1 A=5
A=2
A=1
A=?
A Sum=0
Sum=5
Sum=7
Sum=?
sum
RS=1 RS
LS=0
C=1
LA=1
LS=1
s1 Comp Add
RS=0
C=0
LA=0 5
7
8
?
LS=0 C=1 when
C=1
C=0
C=? A<>1
4/35
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-  State-action table
torial
circuits  Algorithmic-state-machine chart
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/36
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-  State-action table
torial
circuits  Algorithmic-state-machine chart
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/37
©
R.Lauwereins
Imec 2001
State-action table

Digital
• The specification of an FSMD could be
design
done using the traditional next state &
Combina- output table
torial
circuits • However, for large designs, this becomes
Sequential
not so practical
circuits
• Next slide shows the next state & output
FSMD table for the one counting application
design

VHDL

Data = Inport; OCnt = 0; Mask = 1

WHILE Data <> 0 DO
Temp = Data AND Mask
OCnt = OCnt + Temp; Data = Data >> 1
ENDWHILE
Outport = OCnt

4/38
©
R.Lauwereins
Imec 2001
State-action table

Digital
• Next state and output table
design

Present Next state Data Data path variables

Combina-
torial state (Start, Status) path
circuits
output
00 01 10 11 Outport Data OCount Temp Mask
Sequential
circuits S 0 S0 S0 S1 S1 Z X X X X
S1 S2 S2 S2 S2 Z Inport X X X
FSMD S2 S3 S3 S3 S3 Z Data 0 X X
design
S3 S4 S4 S4 S4 Z Data OCount X 1
VHDL S4 S5 S5 S5 S5 Z Data OCount Data Mask
AND
Mask
S5 S6 S6 S6 S6 Z Data OCount X Mask
+Temp
S6 S4 S7 S4 S7 Z Data >> OCount X Mask
1
S7 S0 S0 S0 S0 Ocount Data Ocount X X

4/39
©
R.Lauwereins
Imec 2001
State-action table

Digital
• The next state and output table do not
design
offer a good overview
Combina-  often the next state is only dependent on a few
torial
circuits
of the inputs
 often, the data path variables do not change
Sequential
circuits • Hence, the same information as in the
FSMD
next state and output table is presented
design in a more condensed form: the state
VHDL
action table (See next slide)

4/40
©
R.Lauwereins
Imec 2001
State-action table

Digital
design Present Next state Control and data path
state actions
Combina- Condition State Condition Actions
torial
circuits S0 Start=0 S0 Output=Z
Start=1 S1
Sequential S1 S2 Data=Inport
circuits
S2 S3 Ocount=0
FSMD S3 S4 Mask=1
design S4 S5 Temp=Data
AND Mask
VHDL
S5 S6 Ocount=
Ocount+
Temp
S6 Data <> 0 S4 Data >> 1
Data = 0 S7
S7 S0 Output=
OCount

4/41
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-  State-action table
torial
circuits  Algorithmic-state-machine chart
Sequential • Synthesis techniques
circuits

FSMD
design

VHDL

4/42
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital
• An algorithmic-state-machine chart (ASM
design
chart) is an alternative visualization
Combina- method for the state action table
torial
circuits • It shows loops, conditions and next
Sequential
states in a way which is easier to
circuits understand for a human being
FSMD • Each row in the state action table
design
translates to an ASM block
VHDL
• ASM blocks are constructed out of three
types of elements: state boxes, decision
boxes and condition boxes

4/43
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital
design State name State encoding

Combina- Unconditional
torial
circuits State box variable
assignment
Sequential
circuits

FSMD
design
1 0
Decision box Condition
VHDL

Conditional
Condition box variable
assignment
4/44
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital Example of an ASM block

design

Combina-
torial s0
circuits

Sequential Done = 0
circuits

FSMD
design
0 1
Start = 0
VHDL

Data = Inport

4/45
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital
• An ASM block has to obey following rule:
design
 each input combination should lead to exactly
Combina-
one next state
torial
circuits • Example 1 of an invalid ASM block:
Sequential s0
circuits When Cond2=1
there are two
FSMD next states
design

VHDL
1 0 0 1
Cond1 Cond2

s1 s2
4/46
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital
• Example 2 of an invalid ASM block:
design

Combina-
torial
circuits
When Cond1=0
s0 and Cond2=0
Sequential there is no
circuits next state

FSMD 1 0
design
Cond1

VHDL
0 1
Cond2

s1 s2

4/47
©
R.Lauwereins
Imec 2001
Algorithmic-state-machine chart

Digital
• An ASM chart representing a state-based
design
or Moore type FSMD has no condition
Combina- boxes, since all outputs only depend on
torial
circuits the state; all assignments to variables are
done in state boxes
Sequential
circuits • An ASM chart representing an input-based
FSMD or Mealy type FSMD has state boxes as
design
well as condition boxes; variable
VHDL assignments that only depend on the
state are done within the state boxes;
variable assignments that depend on
input conditions are done in condition
boxes

4/48
©
R.Lauwereins
s0
Imec 2001
Algorithmic-
1 Start=1
0 state-machine
Digital
design
chart
Data=Inport
s1
Combina- OCount=0
torial
circuits
s2
Sequential State based (Moore)
circuits

0 DataLSB
1
FSMD
design

VHDL
s3 Ocount=Ocount+1

Data=Data>>1 s4

1 Data<>0 0

s5
4/49
Output=OCount
©
R.Lauwereins
s0
Imec 2001
Algorithmic-
1 Start=1
0 state-machine
Digital
design
chart
Data=Inport
s1
Combina- OCount=0
torial
circuits
s2
Sequential Input based (Mealy)
circuits

0 DataLSB
1
FSMD Only 4 states instead
design
of the 6 for a state
VHDL
based approach
Ocount=Ocount+1

1 Data<>0 0

Data=Date>>1

s3
4/50
Output=OCount
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-
torial
• Synthesis techniques
circuits
 Basic principles
Sequential  Merging
circuits
Register sharing (variable merging)
FSMD
design Functional-unit sharing (operator
merging)
VHDL
Bus sharing (connection merging)
Register port sharing (register
merging)

4/51
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-
torial
• Synthesis techniques
circuits
 Basic principles
Sequential  Merging
circuits
Register sharing (variable merging)
FSMD
design Functional-unit sharing (operator
merging)
VHDL
Bus sharing (connection merging)
Register port sharing (register
merging)

4/52
©
R.Lauwereins
Imec 2001
Basic synthesis principles

Digital
• An FSMD represented by an action state
design
table or an ASM chart could be
Combina- implemented using the methodology we
torial
circuits used:
 every variable corresponds to a register
Sequential
circuits  every operation corresponds to a functional
unit
FSMD
design  every reading of a variable correponds to a
connection from register to functional unit
VHDL
 every writing of a variable corresponds to a
connection from a functional unit to a register
 every row of the state action table or every
ASM block of the ASM chart corresponds to a
state of the controller
• This method however leads to expensive
4/53
realisations
©
R.Lauwereins
Imec 2001
Basic synthesis principles

Digital
• Minimization requires two steps:
design
 First, the controller can be minimized by
Combina- minimizing the number of states via
torial
circuits combining equivalent states
Sequential choosing the best state encoding
circuits
scheme
FSMD
design
selecting the appropriate flip-flop
type
VHDL
minimizing the next state and output
logic
 Second, the data path should be minimized
according to the principles already mentioned:
When the life time of 2 variables is
non-overlapping, both can be stored
in the same register: register sharing
4/54
When two operations are not
©
R.Lauwereins
Imec 2001
Basic synthesis principles

Digital
• We are going to show the data path
design
minimizations using an approximation for
Combina- a square root calculation (SRA: Square
torial
circuits Root Approximation):

a 2 + b 2 ≈ max ((0.875 x + 0.5 y ), x )

Sequential
circuits

FSMD
design
with x = max ( a , b ) and y = min ( a , b )

VHDL This approximation could for example be used to

compute the power level on a QAM based
communication line, in order to detect the start of a
packet
used for CATV communication (cf. Telenet)
a is then the real part and b the imaginary part of
the signal

4/55
©
R.Lauwereins
Imec 2001
Basic synthesis principles

Digital
design a2 + b2 ≈
Combina-
a=In1
b=In2
max ((0.875 x + 0.5 y ), x )
with x = max ( a , b )
torial
circuits

and y = min ( a , b )
0
Start Out=t7
Sequential
circuits
1
t1=|a|
FSMD t7=max(t6,x)
design t2=|b|

VHDL x=max(t1,t2)
t6=t4+t5
y=min(t1,t2)

t3=x>>3
t5=x-t3
t4=y>>1

t3=0.125x t5=0.875x
t4=0.5y
4/56
©
R.Lauwereins
Imec 2001
Basic synthesis principles
Liveliness of variables:
a variable is alive in first
Digital
design
state following active
clock edge which assigns
a=In1
Combina- b=In2 its new value
torial and in all states between
circuits
0 this first state and the
Sequential
Start Out=t7 last state which uses it.
circuits
1
S1 S2 S3 S4 S5 S6 S7
t1=|a|
FSMD t7=max(t6,x) A X
design t2=|b|
B X
T1 X
VHDL x=max(t1,t2)
t6=t4+t5 T2 X
y=min(t1,t2) X X X X X
Y X
t3=x>>3 T3 X
t5=x-t3
t4=y>>1 T4 X X
T5 X
T6 X
T7 X
# 2 2 2 3 3 2 1
4/57
©
R.Lauwereins
Imec 2001
Basic synthesis principles
S1 S2 S3 S4 S5 S6 S7
Digital A X
design B X
T1 X
Combina-
T2 X
torial
circuits X X X X X
Y X
Sequential T3 X
circuits T4 X X
T5 X
FSMD
T6 X
design
T7 X
# 2 2 2 3 3 2 1
VHDL

• We see that at most 3 variables are life at the same time

• We hence should try to map all variables to three
registers in such a way that their lifetimes do not overlap
• In a further section, the algorithm is presented to
accomplish this: register/memory sharing

4/58
©
R.Lauwereins
Imec 2001
Basic synthesis principles

Digital
design
Operation usage:
a=In1
Combina- b=In2
torial
circuits S1 S2 S3 S4 S5 S6 S7 #
0 abs 2 2
Start Out=t7
Sequential min 1 1
circuits
1 max 1 1 2
>> 2 2
t1=|a|
FSMD t7=max(t6,x) - 1 1
design t2=|b|
+ 1 1
# 2 2 2 1 1 1
VHDL x=max(t1,t2)
t6=t4+t5
y=min(t1,t2)

t3=x>>3
t5=x-t3
t4=y>>1

4/59
©
R.Lauwereins
Imec 2001
Basic synthesis principles
S1 S2 S3 S4 S5 S6 S7 #
Digital abs 2 2
design
min 1 1
max 1 1 2
Combina-
torial >> 2 2
circuits - 1 1
+ 1 1
Sequential # 2 2 2 1 1 1
circuits

• The straightforward approach would allocate 2

FSMD
design abs, 1 min, 2 max, 2 shift, 1 subtractor and 1
adder components, i.e. 9 components
VHDL
• However, at most 2 are active at the same time
• We should hence try to merge multiple functions
into one component: e.g. the subtractor and adder
together
• In a further section, the algorithm is presented to
accomplish this: functional unit sharing

4/60
©
R.Lauwereins
Imec 2001 a=In1
Basic synthesis
b=In2 principles
Digital 0 Start Out=t7
design
1
Combina-
t1=|a|
torial t7=max(t6,x)
circuits t2=|b|

Sequential x=max(t1,t2)
circuits t6=t4+t5
y=min(t1,t2)
FSMD
design t3=x>>3 Connectivity table:
t5=x-t3
t4=y>>1
VHDL

a b t1 t2 x y t3 t4 t5 t6 t7
abs1 I O
abs2 I O
min I I O
max I I O/I I O
>>3 I O
>>1 I O
- I I O
4/61 + I I O
© S1 S2 S3 S4 S5 S6 S7 #
R.Lauwereins
Imec 2001 abs 2 2 Basic synthesis
min
max
1
1 1
1
2
principles
>> 2 2
Digital - 1 1
design
+ 1 1
# 2 2 2 1 1 1
Combina-
torial a b t1 t2 x y t3 t4 t5 t6 t7
circuits abs1 I O
abs2 I O
Sequential min I I O
circuits
max I I O/I I O
>>3 I O
FSMD >>1 I O
design
- I I O
+ I I O
VHDL
• The straightforward approach would allocate 20
connections (11 register outputs and 9 FU outputs)
• In state S2, the largest number of connections is
needed: 4 inputs and 2 outputs.
• We should hence try to merge multiple connections into
one bus
• In a further section, the algorithm is presented to
accomplish this: connection merging
4/62
©
R.Lauwereins
Imec 2001
FSMD design

Digital
• FSMDs
design
• Models
Combina-
torial
• Synthesis techniques
circuits
 Basic principles
Sequential  Merging
circuits

Register sharing (variable merging)
FSMD
design Functional-unit sharing (operator
merging)
VHDL
Bus sharing (connection merging)
Register port sharing (register
merging)

4/63
©
R.Lauwereins
Imec 2001
Register sharing
• Definition of the lifetime of a variable:
Digital
design  The set of states in which the variable is alive
Combina-
 starting at the state following the state in
torial which it is assigned a new value (write state)
circuits
 ending at every state in which its value is used
Sequential (read state)
circuits
 and all the states on each path between the
FSMD write state and a read state.
design
 Note that a variable may be written more than
VHDL once (multiple assignments)
 and that a single written value may be read
multiple times.
• After determining the lifetime of the variables, we
have to group variables with non-overlapping
lifetimes and assign each group to a single
variable. We should hence find the smallest
number of groups.
4/64
©
R.Lauwereins
Imec 2001 Determine variable Register sharing
lifetimes

Digital
design Sort by write state
& life length
Combina-
torial
circuits Allocate new Left-edge algorithm
register
Sequential
circuits

Assign to reg. all

FSMD
design non-overlapping
variables top down
VHDL

Remove all
assigned variables
from list

no yes
Empty?

4/65
©
R.Lauwereins
Imec 2001
Register sharing

Digital
Determine variable lifetimes
design
S1 S2 S3 S4 S5 S6 S7
Combina- A X
torial
B X
circuits
T1 X
T2 X
Sequential
circuits X X X X X
Y X
FSMD T3 X
design T4 X X
T5 X
VHDL T6 X
T7 X

4/66
©
R.Lauwereins
Imec 2001
Register sharing

Digital
Sort variables by write state and lifetime
design
S1 S2 S3 S4 S5 S6 S7
Combina- A X
torial B X
circuits
T1 X
T2 X
Sequential
circuits X X X X X
Y X
FSMD T3
T4 X X T4 has longer lifetime
design T4
T3 X X than T3
T5 X
VHDL T6 X
T7 X

4/67
©
R.Lauwereins
Imec 2001
Register sharing

Digital
Allocate new register and assign non-overlapping variables
design
S1 S2 S3 S4 S5 S6 S7

Combina-
A X
torial B X
circuits T1 X
T2 X
Sequential X X X X X
circuits
Y X
T4 X X
FSMD
design T3 X
T5 X
VHDL T6 X
T7 X

R1: A T1 X T7

R2: B T2 Y T4 T6
R3: T3 T5

4/68
©
R.Lauwereins
Imec 2001
Register sharing
In1 In2

Digital
design

Combina-
torial
circuits MUX MUX MUX

Sequential
circuits
R2: b,t2,y
R1: a,t1,x,t7 R3: t3,t5
FSMD t4,t6
design

VHDL

|a| |b| min max max + - >>1 >>3

Out
4/69
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• The left-edge algorithm finds an
design
assignment with the smallest number of
Combina- registers
torial
circuits • There exist however multiple possible
Sequential
variable-to-register assignments with the
circuits smallest number of registers
FSMD • We hence can use a second cost criterion
design
to find the best assignment
VHDL  First criterion: smallest number of registers
 Second criterion: minimize the number of ports
of the MUX and DEMUX circuits
preferably map two variables to the
same register that are the same (e.g.
left) input of the same functional unit
4/70 preferably map two variables to the
same register that are the same
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• Why does this register sharing reduces
design
the cost of MUX and DEMUX?
Combina-
torial
circuits
R1: t1 R2: t2
Sequential
circuits
MUX R1: t1,t2
FSMD
design

VHDL
FU FU

DEMUX R2: t3,t4

R3: t3 R4: t4

4/71
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• We should hence determine which
design
variables are the same input of the same
Combina- functional unit and which variables are
torial
circuits the same output of the same FU
Sequential
• However, at this stage of the design,
circuits before operator merging, each operator is
FSMD implemented in a different FU such that
design
no variables share the same input or
VHDL output

4/72
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• Does this mean that we should do
design
operator merging before register sharing?
Combina-  Register sharing: (1) minimize registers and (2)
torial
circuits
minimize size of MUX/DEMUX
The latter is only known after
Sequential
circuits operator merging
FSMD
 Operator merging: merge operators where the
design combined cost of MUX/DEMUX/CombinedFU is
smaller than the cost of two FUs
VHDL
The cost of the MUX/DEMUX is only
known after register merging
 This deadlock situation is typical for all
optimization steps in hardware synthesis (and
software compilation)!! Solution:
First optimize those things that give
4/73 the largest cost improvement; use
quick-and-dirty estimates for the
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• What gives the biggest cost influence:
design
register sharing or operator merging
Combina-  In most cases, register sharing has a higher
torial
circuits
cost impact:
there are more variables than FUs
Sequential
circuits
merging two registers in one does
FSMD not increase the cost of the register;
design
merging two different FUs in one
VHDL makes this single FU more expensive
than each of the original FUs
separately
it is easier to quickly estimate which
operators will be merged, than to see
which variables will be merged
4/74
 We hence mostly do register sharing first
For some applications (e.g. when
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• We choose to do register sharing first
design
• We hence have to estimate operator
Combina- merging
torial
circuits
S1 S2 S3 S4 S5 S6 S7 #
abs 2 2
Sequential
circuits min 1 1
max 1 1 2
FSMD >> 2 2
design - 1 1
+ 1 1
VHDL # 2 2 2 1 1 1

We assume that the 2 max-operators used in

different states, will be combined into one max-
operator
We assume that the subtraction and the addition
used in different states, will be combined into one
adder-subtractor
4/75
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• Method for register sharing, combined
design
with MUX/DEMUX cost reduction:
Combina-  Build a compatibility graph
torial
circuits  Perform a max-cut graph partitioning

Sequential
circuits

FSMD
design

VHDL

4/76
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• Build a compatibility graph
design
 Nodes are variables
Combina- Hint: sort the nodes graphically
torial
circuits according to the left-edge merging
Sequential
since this will already separate
circuits incompatible variables with
FSMD overlapping lifetime
design
 Incompatibility edges are drawn between two
VHDL
variables with overlapping lifetime: they cannot
be merged
 Priority edges are drawn between two variables
that are the same input of the same FU or the
same output of the same FU. A weight on this
edge indicates how many times the two
variables drive the same input of the same FU
plus how many times they are the same output
4/77 of the same FU.
©
R.Lauwereins
Imec 2001 Register sharing
a t1 x t7
Digital
design

Combina- b t2 y t4 t6
torial
circuits

Sequential
circuits t3 t5

FSMD
design

VHDL

Nodes are variables

Result of left-edge algorithm:

R1: a, t1, x, t7
R2: b, t2, y, t4, t6
R3: t3, t5
4/78
©
R.Lauwereins
Imec 2001
Register sharing
a t1 x t7
Digital
design

Combina- b t2 y t4 t6
torial
circuits

Sequential
circuits t3 t5

FSMD S1 S2 S3 S4 S5 S6 S7
design
A X Incompatibility edges:
B X variables with
VHDL
T1 X overlapping lifetimes
T2 X
X X X X X
Y X
T4 X X
T3 X
T5 X
T6 X
T7 X
4/79
©
R.Lauwereins
Imec 2001
Register sharing
1 1
a t1 x t7
Digital
design

Combina- b t2 y t4 1 t6
torial
circuits

1
Sequential
circuits t3 t5
1
FSMD x and t4 however have overlapping lifetimes:
design
no priority edge
VHDL
a
a b
b t1
t1 t2
t2 x
x
x yyy t3
t3
t3 t4
t4 t5
t4 t5 t6
t5 t6 t7
t6 t7
t7
abs1 II OO Priority edges:
abs2
abs2 III O
O
O variables with
min
min III III O
O
O
O same input to
max
max III III O/I
O/I
O/I IIII O
O
OO FU or same
I O/I I O
>>3
>>3 II O
O output from FU
II O
O
>>1 I O
>>1
>>1 III O
OO
- I I O
-- III III O
OO
+ I I O
++ III III O
OO
4/80
©
R.Lauwereins
Imec 2001
Register sharing

Digital
• Perform a max-cut graph partitioning
design
 Divide the graph in the minimum number of
Combina-
clusters of compatible nodes, such that the
torial total weight is maximized.
circuits
 Total weight is computed by summing all
Sequential weights of priority edges within a cluster (a
circuits
priority edge crossing cluster boundaries is not
FSMD counted)
design
• We are going to do this optimization
VHDL visually
• See course on optimization techniques for
max-cut graph partitioning optimization
algorithm

4/81
©
R.Lauwereins
Imec 2001
Register sharing
1 1
a t1 x t7
Digital
design

Combina- b t2 y t4 1 t6
torial
circuits

1
Sequential
circuits t3 t5
1
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