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ELECTRONIC ENGINEERING
Candidates may complete the front cover of their answer book and sign their desk card but
must NOT write anything else until the start of the examination period is announced
Only silent, self contained calculators with a Single-Line Display or Dual-Line Display are
permitted in this examination.
Dictionaries are not allowed with one exception. Those whose first language is not English
may use a standard translation dictionary to translate between that language and English
provided that neither language is the subject of this examination. Subject specific translation
dictionaries are not permitted.
No electronic devices capable of storing and retrieving text, including electronic dictionaries,
may be used.
1. (a) Show the states of the transistors for different inputs shown in Figure Q1.
Give the function of the CMOS circuit.
[5 marks]
Vdd
A
Q1
B Q5
Q2
Q3 Q4
Q6
Figure Q1
(b) Explain how static hazards occur in a digital circuit and how it can be eliminated in
the design by giving a suitable circuit as an example.
[5 marks]
2. (a) A simple logic circuit is required to light an LED (via an active low logic signal) if a
driver attempts to start a car whilst in the seat with the seat-belt undone.
Sensors connected to the seat and belt give a logical high if the seat is occupied
and the belt fastened.
Write out the appropriate truth table and draw the circuit implementing this truth
table using only NAND gates.
[5 marks]
(b) A combinational circuit response is as shown in figure Q2. Describe the function of
this circuit in the form of a Boolean equation, a truth table and a circuit diagram.
[5 marks]
Figure Q2
3. (a) Write a complete VHDL program to implement the following logic expression:
AB + AC + AB
[5 marks]
(b) A toggle (T) flip flop has a single control input (T). When T=0, the flip flop is in
the no change state, similar to a JK flip flop with J=K=0. When T=1, the flip flop
is in the toggle mode, similar to a JK flip flop with J=K=1. Write a VHDL program
which will implement the above logic.
[5 marks]
4. (a) Explain the logic operations of the following basic cell structure of SRAM shown in
the figure Q4a below.
[5 marks]
Vdd
T1 T2
T5
T6
A
T3 T4
Row
_ ____________
Column Column
Figure Q4a
(b) Explain the operations of the basic DRAM structure shown in Figure Q4b below.
[5 marks]
Figure Q4b
5. There are two inputs to a sequential circuit and one output. Let X1 and X2 be two bit
streams and let Z be the output.
Let the two bit binary number at the nth clock cycle Yn be represented by
Yn = X1X2
Design a circuit so that if the decimal number represented by Yn is greater than its
value at the previous clock cycle, then the output =1, otherwise the output = 0.
X1 : 0 1 1 1 1 0 0
X2 : 0 1 0 0 1 0 0
During the first clock cycle, Y1 = X1X2 = 00 representing decimal 0; by default we will
let the output be Z=0. During the second clock cycle, Y2 = X1X2 =11 representing
decimal 3; this is an increase from the previous decimal value hence the output Z = 1.
During the third clock cycle, Y3 = 10 representing decimal 2; this is a decrease from
the previous decimal value, hence the output is 0. Use Mealy or Moore design to
implement the above algorithm.
[10 marks]
___________________
( A + B).(C + D)
(a) Implement the above logic function using NOR, NAND and NOT gates.
[4 marks]
(b) Draw a CMOS transistor circuit to implement the above logic function.
[6 marks]
7. (a) Referring to Figure Q7a, identify three problems pertaining to the comparator.
Troubleshoot and enunciate the possible causes corresponding to the problems.
[3 marks]
Figure Q7a
(b) A comparator with a variable reference circuit is shown in Figure Q7b. What
could be the problem in the circuit referring to the waveform shown?
[3 marks]
Figure Q7b
8. (a) The open-loop comparator circuit in Figure Q8a may exhibit the “chatter effect”
in response to noise in the system in which vn is considered to be a noise source
in series with the signal source v1. With a neat circuit diagram, show how this
chatter effect can be eliminated. [Note: Figures Q8b&c illustrate input signal and
output signal showing the chatter effect].
[3 marks]
Figure Q8
(b) Explain the operation of the circuit you proposed in question 8(a).
[2 marks]
Figure Q8c
i) The switching occurs at I- = I+. Find the switching voltages for capacitor,
Vc max and Vc min.
[2 marks]
ii) Sketch the waveform for the voltage across the capacitor, Vc.
[3 marks]
Figure Q9
(a) What are the conditions for the Wien bridge oscillator to sustain oscillation? What
is the start-up condition for the Wien bridge oscillator?
[4 marks]
(b) Design a Wien-bridge circuit to oscillate at a frequency fo= 1 kHz. Note that only
resistors 1 kΩ and 2 kΩ are available and there is no restriction on capacitor
value.
[3 marks]
(c) Modify the Wien bridge circuit in question 9(a) in order for the oscillation to self-
start. Draw the circuit diagram.
[3 marks]
10. A MOSFET amplifier is depicted in figure Q10. The gm and rd of the MOSFET are 5 mS
and 40 kΩ respectively.
(a) Draw the small signal ac equivalent circuits of the MOSFET amplifier for low
frequencies. Derive the voltage gain in term of frequency, ω=2πf.
[4 marks]
(b) The high frequency characteristics of the MOSFET are determined by the gate-
drain capacitance Cgd, the gate-source capacitance Cgs, the drain-source
capacitance Cds. Draw the equivalent circuit for high frequencies.
[3 marks]
Figure Q10
11. (a) Why should not the gate-source junction of a JFET be forward biased?
[1 mark]
(b) What is the primary advantage that FETs have over BJT?
[2 marks]
(c) A JFET is a voltage-controlled device. Since the JFET has no gate current, there
is no beta rating for the device. Hence, the output current (ID) can be defined in
terms of the circuit input voltage as follows:
2
V
I D = I DSS 1 − GS
V
GS ( off )
Where I DSS = the shorted gate drain current rating of the device
VGS = the gate-source voltage
VGS (off ) = the gate-source cut-off voltage.
The above equation is valid when VGS ≤ VGS (off ) . Explain what will happen if
this condition is not fulfilled.
[3 marks]
(d) Determine the value of drain current for the circuit shown in Figure 11d.
[4 marks]
Figure Q11d
12. (a) Distinguish between metals and semiconductors at 0 K on the basis of band
theory of solids.
[2 marks]
(c) The lattice constant of silicon is 0.54 nm. Calculate the number of silicon atoms
in a cubic centimetre.
[2 marks]
(d) A sample of intrinsic is silicon having 1 cm long by (1 mm) x (1 mm) area has
an electron mobility is 0.1 m2V-1s-1. Prove that at room temperature and/or at
any reasonable temperature, silicon would conduct electricity very poorly.
[3 marks]
(f) Find the probability of an electron state being occupied at a temperature of 300
K if its energy is
(h) Given that the current through a diode under reverse bias of 0.3 V at 20o C is 1
µA, calculate the current when there is a
13. (a) An ingot of germanium is formed from a melt containing 100 g of germanium and
5.0 µg of indium (relative atomic mass 114.76). The volume of the ingot is 1.83 x
10-5 m3. A specimen with dimensions, 2 cm x 1 mm x 1 mm is cut from the ingot;
calculate its resistance before and after exposure to a flash of light containing 1.8 x
1013 photons, assuming that each photon produces an electron-hole pair. The hole
2 -1 -1 2 -1 -1
and electron mobilities are 0.19 m V s and 0.39 m V s respectively.
[7 marks]
(b) In a p-type GaAs sample, electrons are injected from a contact. If the minority
carrier mobility is 0.4 m2V-1s-1 at 300 K, calculate the diffusion length for the
electrons. The recombination time is 0.6 ns.
[5 marks]
(c) A silicon crystal is made n-type by introducing ND donor levels per m3. The donor
energy level and the Fermi level, EF coincide at 0.1 eV below the bottom of the
conduction band, EC.
i) Calculate the electron, hole and donor densities for the crystal. Sufficient
acceptors, NA m-3, are now added to make EF drop to 0.2 eV below EC.
[6 marks]
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For silicon:
Band Gap = 1.1 eV
Intrinsic carrier concentration at 300K, ni = 1.6x1016 m-3
Electron mobility, µn = 0.14 m2V-1s-1
Hole mobility, µp = 0.05 m2V-1s-1
Effective mass of electron, mn = 0.3m0
Effective mass of hole, mp = 0.5m0
The relative permittivity of Silicon, ε r = 11.8
Density = 2400 kg m-3
For hydrogen:
− 13.6
Energy level at level n, E n = eV
n2
Useful Equations:
qD p p no qDn p po qV
J= + exp − 1
L p Ln kT 1
F (E) =
1 + e ( E − E F ) / kT
− ( E F − EV ) − ( EC − E F )
p = N V exp and n = N C exp
kT kT
dp( x) dn( x)
J P ( x) = qµ P p ( x) E − qD P and J n ( x) = qµ n n( x) E + qDn
dx dx
3 3
2πm n kT 2
E − Ec 2πm p kT 2
E − EF
n=2 2 exp F , p=2 2 exp v
h kT h kT
H62ELD-E1