Aishwarya. B et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES

Vol No. 6, Issue No. 1, 133 - 140

IMPROVEMENT OF PSRR IN COMMON SOURCE AMPLIFIERS

Aishwarya. B1 , Bharani. K2, Kommidi Sravanti2 , Jagannadha Naidu. K3

M. Tech -VLSI Design , SENSE, VIT University , Vellore, Tamil Nadu, India

Email: aish_krsna@yahoo.com , jagannadhanaidu.k@vit.ac.in

ABSTRACT - Common source amplifiers find
wide application i n o pamps. And t hese
opamps i n t urn have b een widely us ed i n
sampled-analog s ignal pr ocessing a pplications
over t he pa st s everal years. H owever, t he
popular two-stage op amp suffers from poor
AC pow er s upply r ejection to one o f the
power rails. Four techniques are presented
here t o overcome t he p ower-supply
rejection r atio ( PSRR) problems of t he
common s ource amplifiers: ( 1) Using
cascoded common source amplifier employing
current mirror t hat i ncreases t he gain of t he
circuit t o improve PSRR (2) Using a common
source a mplifier with a ne gative f eedback
which gives low value of gain from power
supply t o output node thereby i ncreasing
PSRR ( 3) U sing a n a dditional c ircuitry to
nullify the effect of supply voltage changes on
the o utput (4) Using gain b oosting t echnique
in order t o overcome certain disadvantages in
the above three methods.
KEYWORDS – PSRR ; Common source ;
Cascode ; Negative Feedback ; Additional
circuitry ; Gain boosting
the d evice’s noise p erformance. Power
supply r ejection r atio is a measure o f how
well a c ircuit r ejects r ipple c oming from
the input po wer s upply a t v arious
frequencies and is very critical in many RF
and w ireless ap plications. I f t he s upply o f
an o pamp c hanges, its o utput s hould not ,
but it typically does. The ratio of gain from
output to i nput t o the r atio of c hange in
output to the change i n s upply vo ltage
gives the value of PSRR.
PSRR = Av/ Avdd …………(1)
Where A v=gain f rom input to o utput a nd
Avdd=gain from power supply to output
II. TECHNIQUES TO IMPROVE
PSRR:
To t otally improve po wer s upply
rejection r atio it is necessary t o h ave an
high v alue f or the gain f rom i nput to
output i deally infinite value a nd a low
value for t he ga in from po wer s upply t o
output ideally zero.

I. INTRODUCTION: Here four d ifferent techniques h ave

been a ddressed w hich i nclude 1)
Any s ignal or noise on t he s upply Cascoding t echnique 2) Negative
lines w ill couple into t he act ive c ircuitry Feedback t echnique 3) Additional c ircuit
through the stray capacitances a nd gain o f technique 4) Gain boosting technique.
the b ias network an d b e a mplified b y t he
active circuitry on the die. These unwanted
signals are noise and, therefore, degrade

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Aishwarya. B et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 6, Issue No. 1, 133 - 140

Fig 1 .2 s hows t he s mall signal model o f

III. CASCODING TECHNIQUE:
A. Objective:
The ca scoding t echnique increases t he
output r esistance o f t he circuit t hereby
increasing t he g ain o f t he a mplifier c ircuit
[3] i.e t he ga in from input to o utput
increases. Thus P SRR increases. The
circuit is shown in the figure 1.1.
the co mmon s ource transistor M 4 a nd t he
common g ate transistor M 7. From fi gure
1.2 it can be clearly said that the gain from
input to output that is
Av = Vout /Vin =gm4((gm7.r07.r04)||r02)……(2)
(Neglecting t he body e ffect current source
gmb7V2)

Figure:1.3

The gain from supply to output is

Vout/VDD= 1

+ gm2(1+gm8r08)2(1+gm5r05)2

Figure: 1.1(ref1) [(1+gm5r05)r08+(1+gm8r08)r07]2

B. Small-signal Analysis: - (1+gm5r05)(1+gm8r08)

[(1+gm5r05)r06+(1+gm8r08)r07]

- gm2r06(1+gm8r08)(1+gm5r05)

(1+gm6r06)[r08(1+gm5r05)+r05(1+gm8r08)]

……………(3)

Figure: 1.2

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Aishwarya. B et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 6, Issue No. 1, 133 - 140

C. Design Procedure: of t he co mmon s ource s tage ( M4 ) at th e

output s ide a nd R out is t he o utput
The a spect r atio values o f M1, M2 are resistance o f t he cas code s tage.
24/0.35, and 40/0.35 respectively. M3, M4, Considering both M 4 and M 7 operate i n
M6, M7 are 12/ 0.35 a nd M 5, M8 are saturation region G m =gm4 and R out=[(( gm7
6.5/0.35. The supply voltage used is 3.5V. + gmb7 ). r04 . r07 ) || r 02], yielding A v = gm4
The current source used in the circuit is of [(( gm7 + gmb7 ). r04. r07 ) || r 02]. T hus t he
0.5mA and the s upply vo ltage is 3. 5V.
maximum voltage gain is roughly equal to
Theoretically c alculating t he P SRR us ing the s quare o f t he intrinsic g ain o f t he
equations 1, 2 and 3 would l ead to transistors.
33.49dB. The h igh impedance at the
output s ide o f th e c ircuit c omes from th e IV. NEGATIVE FEEDBACK
fact t hat i f t he o utput n ode v oltage is TECHNIQUE:
changed by a small value ∆V , t he
resulting c hange a t t he source o f the A. Objective:
cascode d evice is much less. I n a sense , The o utput v oltage is fedback t o
the cas code t ransistor “ shields” t he input the input t hrough a N MOS transistor t o
device f rom v oltage v ariations at the ensure t hat output f ollows t he input a nd
output. T he t ransistor M 4 works a s a there is stability of gain. Fluctuations from
common source stage and the transistor M7 power s upply do es n ot a ffect m uch t he
works as a common gate stage. M4 and M 7 output va lue a nd hence t he g ain from
transistors carry equal currents. supply t o o utput is very small r esulting in
higher PSRR[1].
For M 4 to o perate in saturation
region t he voltage at t he drain t erminal o f
M4 , VD4 ≥ Vin - Vthn. If both M 4 and
M7 are in s aturation , then V D4 is
determined primarily by the bias voltage of
the transistor M7 (VG7). VD4 = VG7 - VGS7.
Thus VG7 - VGS7 ≥ Vin – Vthn . Fo r M 2 to
be saturated Vout ≥ VG7 - Vthn that is Vout ≥
Vin – Vthn + VGS7 - Vthn if V G7 is chosen to
place M4 at the ed ge o f s aturation.
Consequently t he minimum o utput l evel
for w hich both t he t ransistors operate i n
saturation r egion is equal t o the o verdrive
voltage of M4 plus that of M7. Thus output
voltage s wing r educes d ue t o the cas cade
stage b y at least t he o verdrive voltage o f
M7. A lso s ince o utput cap acitance
Figure: 2.1(ref1)
increases t he p ole at o utput n ode s hifts
towards left giving a low 3-dB frequency. B. Small-signal Analysis:
The gain of a cascode stage is given as The small s ignal m odel f or
Gm.Rout where G m is the transconductance calculating t he ga in from supply t o o utput

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is shown in figure 2.2. The gain from input
to output i s c alculated by gr ounding t he
gate of transistor M6 to ground and finding
the ga in from input to output w hich g ives
the value o f open loop voltage gain which
is g iven a s A0= gm1.( r 01 || r 03 ). T he l oop
gain is found by giving a test voltage to the
gate of t ransistor M 6 and g rounding t he
input to zero.
βA0=[(gm7.R0).[gm1(r01||r03)]]/[1+gm7R0]…
……………………………………….(4)
Hence the closed loop gain of the voltage-
voltage feedback is given as
Av = [ gm1.( r 01||r03 ).(1+gm7.R0)] / [( 1 +
gm7.R0 ) + g m7.R0.(gm1.( r01||r03 )]……(5)
Figure: 2.2
Avdd=1–r03.gm2+gm2.r04.r03
( 1+gm3 r03)
- gm4.r04.gm2(1+gm3.r03)-gm2(1+gm3.r03)
( 1+gm3 r03)
………………………………(6)
C. Design Procedure:
The cu rrent v alue u sed is 3 mA a nd
supply is 3.5V. The value of R 0 is 1kohm.
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Vol No. 6, Issue No. 1, 133 - 140
The as pect r atio v alues o f M 1, M2 are
24/0.35 and 308. 57/0.18 respectively, M 4,
M5 are 8/0.35 and 17/0.35 respectively, M3
is 6/ 0.35 a nd M 6 is 12/ 0.35. The o utput
voltage is sampled and is given to the gate
of transistor M 6. The cu rrent f lowing
through M6 is mixed with the input current
which is t hen c onverted to v oltage us ing
the r esistor R 0 and g iven a s input t o the
gate o f M5. Here cu rrent mirror technique
is u sed t o pr ovide t he bias for t he P MOS
load at the o utput s ide. T he v alue o f
resistance R0 is very c ritical in t he d esign
as t he o utput i s fedback t o the i nput
through i t. S mall value of r esistor w ould
be more suitable for the design.
V. ADDITIONAL CIRCUIT
TECHNIQUE:
A. Objective:
A negative ga in p ath from s upply
VDD to t he o utput no de would nullify t he
effect o f V DD o n o utput. T his c oncept is
used in t his t echnique t o r educe t he gain
from supply to o utput t hereby increasing
the PSRR.
Figure: 3.1 (ref1)
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Vol No. 6, Issue No. 1, 133 - 140

B. Design Procedure: be easily adopted without losing the speed

advantages o ffered b y t he ad vanced
The a spect ratio v alue of t ransistors technology.
M1 is 48/ 0.35, M2 is 550/ 0.35, M 3 is
40/0.35, M4 is 8/0.35, M7 is 24/0.35 and
M5, M10, M8 is 6/0.35 a nd M6, M9 is
12/0.35. The I1 and I 2 currents are of 3mA.
Using a co mmon s ource a mplifier
operating in linear r egion p ower
fluctuations from V dd to output no de c an
be nullified. T he p ositive V dd fluctuations
passed by t he t ransistor M 2 on t he o utput
node ar e ad versely impacted by t he V dd
fluctuations a fter a mplification by M 6 as
M6 operates as a common source amplifier
giving an i nverted o utput. The i nput
transistor M 4 works i n s aturation r egion
with high r 0 and G m. Though the transistor
M6 operates i n linear r egion due t o hi gh
Figure: 4.1(ref 3)
gate v oltage ( Vdd) , it is driven in to
saturation to increase its r o and G m. The 3-
dB frequency o f t his c ircuit i s l ess than Multistage amplifier t opologies
that of negative feedback technique [1] as (cascading ap proach) would pr ovide a
an extra MOS tr ansistor at th e o utput o f possible r emedy. The minimum s upply
additional c ircuit a dds t o the load requirements are preserved a nd v oltage
capacitance thereby shifting the pole to the gain is in creased by using s imple l ow
left and decreasing the 3-dB frequency. voltage g ain s tages. A n a mplifier w ith
more t han t wo g ain s tages r equires
VI. GAIN BOOSTING TECHNIQUE invariantly s ome kind of m iller f requency
(PROPOSED TECHNIQUE): compensation t echnique t hat limits t he
A. Introduction and Objective: maximum achievable bandwidth [2].

As PSRR is directly proportional to the Several low-voltage approaches have

gain f rom input t o output o f th e c ircuit,
PSRR can b e i ncreased b y i ncreasing the
gain o f t he circuit [2]. In a simple s ingle-
stage a mplifier implemented in d eep sub-
micron CMOS technologies, the maximum
achievable voltage g ain is b ecoming
unsatisfactorily low b ecause o f t he
progressive r eduction in t he t ransistor
small-signal output resistance. This cannot
be e liminated by increasing c hannel
lengths as g reater ch annel lengths c annot
been de vised as the s imple c ascading
scheme c annot be t olerated i n a low
voltage co ntext. I n ad dition , t o i ncrease
the g ain o f a s ingle-stage a mplifier e ven
further ga in b oosting(up t o three or f our
equivalent s imple g ain stages) c an also be
employed. I n a g ain boosted a mplifier,
since miller co mpensation is a voided , we
do no t i ncur in t he frequency limitations
exhibited by t he cascading approach. The

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Aishwarya. B et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
gain bo osting circuit i s shown b elow i n
[3].
B. Small-signal Analysis:
The s mall signal model t o f ind Avdd is
shown b elow in figure 4. 2. The v oltage
gain o f t he c ircuit in figure 4. 1 w ould b e
Av = gm3.(gm1 r01 r03)(gm2 r02 )………..(7)
Figure:4.2
Avdd = Vout / VDD =
[1+gm4r04].[r01(gm3(1-gm1)+gm2gm1r02)+1]
[r03.gm2(1-gm1)+gm2gm1r02+gm3r04+1]
………………………………………(8)
C. Design Procedure:
The as pect r atio values chosen for M 1,
M2, M3, M4 and M5 are 18/0.35 , 12/0.35
, 8/0.35 , 40/0.18 , 6/0.35 respectively. The
idea b ehind ga in boosting t echnique in
common s ource a mplifiers is t o f urther
increase t he o utput i mpedance w ithout
adding more cas code d evices. In t he
cascaded c ircuit in [1] the bo ttom
transistor i n t he common s ource s tage
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Vol No. 6, Issue No. 1, 133 - 140
works as a d egeneration r esistor sensing
the o utput c urrent a nd converting it into a
voltage . It can be said t hat t he voltage
drop acr oss the d egeneration r esistor can
be subtracted from t he gate voltage o f t he
above t ransistor w hich is in co mmon g ate
stage t o p lace it in cu rrent-voltage
feedback [3] , t hereby increasing the
output impedance.
In t his c ase t he idea is t o d rive
the common gate transistor by an amplifier
that forces t he drop voltage to be equal t o
the g ate v oltage of t he co mmon g ate
transistor. Thus voltage v ariations at t he
output s ide w ill affect t he d rop v oltage
only t o a lesser e xtent. W ith s mall
variations a t t he d rain t erminal o f M1 the
current t hrough r 03 and t he o utput c urrent
remains mo re c onstant t han t hat in [ 1]
yielding a higher o utput i mpedance. Thus
gain is increased.
VII. RESULTS :
Simulation done i n Mentor gr aphics
using 0. 35µm t echnology a nd s upply
voltage o f 3. 5 volts yielded t he following
results. Here P denotes Practical values got
by s imulation and T d enotes theoretical
values go t by manually s olving t he
equations for P SRR u sing s mall-signal
models. The 3-dB cut-off fr equency values
of a ll t he t echniques are more w hen
compared to [1].
The value o f P SRR t echnique us ing ga in
boosting i s more than t he first three
techniques in [1].
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Vol No. 6, Issue No. 1, 133 - 140

PARAMETERS CASCODING PARAMETER CASCODING NEGATIVE

TECHNIQUE TECHNIQUE FEEDBACK
P(dB) T(dB) 3-dB freq TECHNIQUE
Av 31.03 33.49 hz 3-dB freq
hz
9
Avdd 0 0.2 PSRR 2.46290×10 27.48810×109

PSRR 31.03 33.29

PARAMETER ADDITIONAL GAIN

CIRCUIT BOOSTING
3-dB freq 3-dB freq
hz hz
9
PARAMETERS NEGATIVE PSRR 1×10 465.3322×106
FEEDBACK
TECHNIQUE
P(dB) T(dB)
Av 35.92 34.58

Avdd 0.0041 0.24

PSRR 35.92 34.34

VIII. CONCLUSION:

PARAMETERS ADDITIONAL Thus we see t hat both t he g ain a nd

CIRCUIT PSRR g et i mproved in c ascading
TECHNIQUE technique but w ith cer tain d rawbacks as
P(dB) T(dB) low output swing and low 3-dB frequency
Av 36.67 - .So it i s suitable f or only l ow f requency
Avdd 0.25 - applications. Negative F eedback n ullifies
the ef fect o f fluctuations at the s upply
PSRR 36.42 - node o n t he o utput a nd s tabilizes t he g ain
giving hi gher P SRR. H owever the ga in is
reduced by a f actor of ( 1+Aβ ) ,
PARAMETERS GAIN BOOSTING designing the loop parameters β
TECHNIQUE appropriately can g ive higher ga ins. T his
P(dB) T(dB) method can be e mployed i n h igh
Av 39.6 54.8 frequencies al so. Additional c ircuit
technique c an g ive high P SRR values but
Avdd 0.0049 16 at the co st of very low g ain. H owever , it
PSRR 39.6 38.8 has t he d isadvantage o f r educing t he 3 -db
frequency o f t he c ircuit o wing t o the
additional capacitance incurred at t he
output no de . H ence s uch c ircuit c an be
useful in d esigning c ascade a mplifiers
which have ca scading s tages t o i ncrease
the g ain along w ith a n a dditional c ircuitry

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Aishwarya. B et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 6, Issue No. 1, 133 - 140

to provide stabilization from power supply

fluctuations. Our pr oposed t echnique
which is ga in boosting g ives high ga in
without u sing c ascode s tages a nd he nce
miller co mpensation is a lso not r equired.
Therefore it can be used in high frequency
operations also.

IX. REFERENCES:

1. Vivek Gupta , A nu G upta , Nitin

Chaturvedi A nd A bhijit A sati “ A
Novel technique f or i mprovement
of p ower s upply r ejection r atio in
amplifier circuits”.

2. Gulati.K a nd H .S L ee “A ±2.5V –
Swing C MOS T elescopic
operational amplifier”.

3. Behzad Razavi, “Design of Analog

CMOS Integrated circuits”.

4. Loikkanen . M , R ostamovaara . J
“PSRR i mprovement technique f or
amplifiers w ith M iller cap acitor,”
Circuits a ns s ystems, 2006. ISCAS
2006.Proceedings . 2006 I EEE
International symposium o n , vo l.,
no., pp.4 pp.-1397.

5. Pietro M onsurro, S alvatore P ennisi,

Giuseppe S cotti, A lessandro
Trifiletti “0.9V C MOS cas code
amplifier w ith b ody d riven g ain
boosting”.Int.J.circ.Theor.Appl.200
9;37:193-202.

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