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FFT architectures obtained from radix 2 and mixed radix
Cooley-Tukey algorithms are discussed in this paper. Thus the
aim here is to compare the FFT architectures used for
implementing the UWB receiver with minimum resource
utilization.
I. INTRODUCTION
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The FFT (Fast Fourier Transform) processor is
widely used in DSP applications and now being used in
communication protocols. Recently, both high data processing
and high power efficiency assumes more and more importance in
wireless systems. UWB has its part in wireless personnel area
network utilizes efficient FFT architectures for its design.
P-OFDM is an improved version of Multiband
Figure 1: Signal flow graph for 8 point FFT
OFDM, which is one of the techniques in implementing
The signal flow graph for 8 point FFT is
UWB transceiver. This is destined to reduce power
consumption as well as hardware resources utilized. shown in figure 1.Similar butterfly structure is obtained for
FFT/IFFT is one of the key components and the most the 128 point FFT and it includes number of Radix 2
complex block in OFDM (orthogonal frequency division butterfly elements. This makes the design easier but it does
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multiplexing) based designs. This paper explores the FFT not provide good performance.
architectures using radix 2 as well as mixed radix
concepts. In the mixed radix concept, both multipath delay III. MIXED RADIX FFT ARCHITECTURES
commutator as well as multipath delay feedback is also Mixed radix algorithm, another modified
dealt with. The synthesis part of the job is accomplished version of Cooley – Tuckey algorithm handle composite
by downloading the verilog hardware description language sizes. It behaves like FFT for any series that can be
factored in factors 2, 3, 4, 5, 8 and 10. When there are
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architecture has high-radix arithmetic units with two main In this architecture, the first 64 pieces of
memories for input storage, intermediate commutators, complex data are stored in one register file, so that when
delays and output buffer for rescheduling purposes. The the next 64 sequences arrive both are applied to FFT
block architecture is shown in Figure .2. calculations. In order to minimize the memory
requirement and to ensure the correction of the FFT
output data, 64 point FFT is calculated using radix 8 and
radix 2 algorithms. The architecture for mixed radix
single path delay feedback is shown in figure.4. The
approach of using four complex multipliers as in the case
of multipath delay commutator is modified by reducing
the number to two. In the beginning, the datas are
reordered and separated into 32 groups. Each group has
four sequences in this design supporting multiple paths.
The data of each path are fed to appropriate constant
Figure.2: Mixed Radix Multipath Delay Architecture multipliers according to the scheduling of the twiddle
factors. The data of the first 32 groups are stored in the
Here the 128 point FFT suited for UWB memory. When the data of the next 32 groups enter the
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applications are calculated using four parallel 32 point FFT module the eight input data are loaded into four radix 2,
[2]. The architecture shows the FFT computation for the four from the memory and four from the input,
32 point FFT, which is decomposed into radix 4 FFT and respectively. Two of these four output data are multiplied
radix 2 FFT. The switches are more complex and it is by the appropriate twiddle factors first before they are
implemented using multiplexers. All these operations are stored in the memory; the other two are multiplied by the
controlled by the control unit and the twiddle ROM is twiddle factors before they are fed to the module. Hence
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implemented using shift-add method of twiddle factor
computation. The twiddle ROM computation is made by
observing the unique twiddle factors and then mapping the
values according to the mapping table. The radix 4
architecture shown in figure.3. is implemented using Carry
Save Adder. It is found that Carry Save Adder, which is a
fast adder, is having less delay compared to other adders
the complexity, power consumption, and resources
required are further reduced. The radix 8 FFT is
computed by decomposing into radix 2 FFTs and by
applying suitable delays.
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Figure.5: Combined delay and feedback architecture
IV. CONCLUSIONS
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The FFT architectures, satisfying
UWB specifications suited for its applications have been
designed, simulated and the simulation results are
compared. It is found that ,even though all the mixed radix
architectures is having better performance, the Mixed radix
combined multiple path feedback commutator has the best
performance in terms of reduced gate count and power
consumption..
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REFERENCES
[1] A. Batra et al., “Multi-Band OFDM Physical Layer
Proposal for IEEE 802.15 Task Group 3a,” IEEE
P802.15- 03/268r3, Mar. 2004.
[2] D.M.W.Leenaerts,” Transceiver design of Multiband
OFDM UWB”, philps Research, EURASIP journal on
Wireless communication and networking, Jan.2006.
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