Lecture05 1

2008/12/8
Ken Takeuchi
Toshiba, NAND Flash Circuit Designer: ‘93-’07
University of Tokyo, Associate Professor: ‘07-
Developed 6 world’s highest density NAND (0.7μm 16Mb, 0.4μm
Solid-state drive (SSD) and memory 64Mb, 0.25μm 256Mb, 0.16μm 1Gb, 0.13μm 2Gb, 56nm 8Gb)
150 Patents Worldwide (88 U.S.Patents)
system innovation ISSCC Takuo Sugano Outstanding Paper Award: ’07
ISSCC Program Committee (Memory): ‘07-
07
Dec.11, 2008 Stanford Univ. MBA: ‘03
Ken Takeuchi
Dept. of Electrical Engineering and Information Systems,
University of Tokyo
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
http://www.lsi.t.u-tokyo.ac.jp ISSCC 1999 IEDM 2000 ISSCC 2002 ISSCC 2006
250nm 256M Flash 160nm 1G Flash 130nm 2G Flash 56nm 8G Flash
Ken Takeuchi Advanced Flash Memory Devices 1 Ken Takeuchi Advanced Flash Memory Devices 2
Outline Outline
SSD, Memory System Innovation SSD, Memory System Innovation

NAND Overview NAND Overview
NAND Circuit Design NAND Circuit Design
SSD Overview SSD Overview
NAND Controller Design NAND Controller Design
Operating System for SSD Operating System for SSD
Green IT with SSD Green IT with SSD
Summary Summary
Definition of SSD NAND Flash Memory and SSD Market
SSD : Solid- State Drive PC expected as an emerging application

Mass storage to replace HDD of PC/Enterprise Server.
Small, robust, low-power and high performance.
SSD consists of NAND Flash Memory and NAND
controller(+RAM)
Gartner Dataquest
J. Elliott, WinHEC 2007, SS-S499b_WH07.
I. Cohen, Flash Memory Summit 2007.
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Memory System Bottleneck SLC NAND as Cache of HDD

CPU registers (<1ns)
CPU registers (<1ns)
SRAM (<1ns)
SRAM (<1ns)
DRAM (10ns)
(10 )
DRAM (10ns)
Big Gap SLC NAND (20us)
HDD (10ms)
HDD (10ms)
Future Memory System Future Direction: Vertical Integration

CPU registers (<1ns) History of NAND Flash Memory System
Future Block
Application Software Abstracted SSD
S/DRAM (<1ns)
File System (OS)
MP3 Player Go vertical
DRAM (10ns) SD Card
NAND Controller integration to
Bad Block Management USB Memory improve system-
DRAM (10ns) Wear-leveling level performance.
NAND Controller ECC
1bit/cell NAND (20us)
Smart Media
NAND Flash Memory
2-4bit/cell NAND (1~10ms) SSD
K. Takeuchi, ISSCC 2008 Tutorial T-7.
Key Challenge of SSD Outline
SSD, Memory System Innovation

Need to improve device reliability such as
NAND Overview
endurance, data retention, and disturb.
NAND Circuit Design
Require co-design of NAND and NAND controller SSD Overview
circuits to best optimize both NAND and NAND
controllers. NAND Controller Design
Operating System for SSD
OS/Computer architecture innovation essential.
Green IT with SSD
Summary
K. Takeuchi, ISSCC 2008 Tutorial T-7.
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NAND Flash Memory Page & Block of NAND Flash Memory

Page : program/read unit Block : Erase unit
Bitline
Bitline
Bitline
43nm 16Gb NAND

K. Kanda, ISSCC, 2008.
2 Select-gate 2 Select-gate
32 Word-lines Source-line 32 Word-lines
NAND flash Memory cell :
memory chip Memory circuit Floating Gate-FET Memory cells are sandwiched by select gates.
Contactless structure : ideal 4F2 cell size
F.Masuoka, IEDM 1987, pp.552-555.
Top View of NAND Flash Cell Array MLC vs. SLC

Source-line
Bitline (second metal) (first metal)
SLC : Single-level cell or 1bit/cell
MLC : Multi-level cell or >2bit/cell
2bit/cell : Long production record since 2001
3bit/cell or 4bit/cell : Will be commercialized this year.
Most existing SSD uses SLC. MLC based SSD is
commercialized this year.
STI
Active area
SGD SGD SGS SGS

SLC (Single-level cell) MLC (Multi-level cell)
Contact to bitline Word-lines Contact to source-line
Number of memory cells Number of memory cells
“0” “1” “0” “1” “2” “3”
Simple structure : High scalability, High yield Vth Vth

K. Imamiya, ISSCC 1999, pp.112-113.
NAND Operation Principle NAND Operation Principle (Cont’)

Read Program : Electron injection
Number of memory cells
Bit-line (0.8VÆ0V) “0” “1” 18V
Vread (4.5V)
0V 0V
Selected word-line Vth
(Read voltage : 0V)
9 Channel-FN tunneling
Read voltage
Bit-line voltage 9 High reliability
Vread (4.5V) 0V
“1” 9 Low
L currentt consumption
ti
“0” Erase : Electron ejection (~pA/cell)
Vread (4.5V) Time
0V 0V 9 Page based parallel program
9 After precharging, bit-lines are discharged through the memory cell. 20V 20V
Typical page size : 2-4kB
9 Unselected cells are biased to the pass voltage, Vread.

9 Small cell read current (~1uA) Æ Slow random access (~50us)
20V
9 Serial access : 30-50ns Æ Fast read = 20-30MB/sec S. Aritome, IEDM 1990, pp.111-114.
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NAND Operation Principle (Cont’) Outline

Page based parallel programming
Bit-line
NAND Overview
Row decoder
Page Page : 2-4KBytes
・・・
NAND Circuit Design
Page
P buffer
b ff
SSD Overview
Page buffer
Memory cell array T.Tanaka, Symp. on VLSI
Circuits 1990, pp.105-106.
NAND Controller Design
All memory cells in a page are
programmed at the same time. Operating System for SSD
Program speed = Page size / Programming time
Green IT with SSD
= 8KByte / 800us Summary
= 10MByte/sec (56nm MLC) K. Takeuchi, ISSCC 2006,pp.144-145.
NAND Circuit Design Random Access : High Speed Programming
Bit-by-bit Program Verify Scheme

Program pulse
Program Algorithm 18V
Random Access Data load

0V 0V
High Speed Programming Program pulse 0V

FN tunneling
High Speed Read No Verify‐read
Bit-line
Page
All cells
Sequential Access programmed ?
・・・
Yes
High Speed Programming End
Page buffer
High Speed Read
During the verify-read, the program data in the page buffer
is updated so that the program pulse is applied ONLY to
insufficiently programmed cells. T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.
Random Access : High Speed Programming (Cont’) Random Access : High Speed Programming (Cont’)
Incremental Program Voltage Scheme Problems of MLC programming
Word-line waveform
Program pulse Program voltage, Vpgm
increases by ⊿Vpgm. “0” “1” “2” “3”
⊿Vpgm
Verify read Constant electric field

across the tunnel oxide.
Vth
Tpulse Tvfy
Constant tunnel current. Y1 Y2 Y1 Y2
1 cycle MLC SLC 2‐level cell 4‐level cell
# off program pulses:
l N
Npulse
l cycles
l
Vth shift is constant at ⊿Vpgm. “1”-program “1”-program
Programming time, Tprog = (Tpulse+Tvfy)×Npulse & ”1”verify & ”1”verify Two bits in a cell are assigned
Program characteristics to two column addresses.
Npulse = ⊿Vth0/⊿Vpgm
Vth
Fastest cell
“2”-program 3 operations (“1”-, “2”- and
Achieve both fast Slowest cell & ”2”verify
Verify
voltage
“3”-program) required.
⊿Vth0
programming and Npulse
(Time) Long programming.
precise Vth control. “3”-program
(⊿Vth0/⊿Vpgm) cycles & ”3”verify
G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.

K. D. Suh, ISSCC 1995, pp.128-129.
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Solution : Multi-page Cell Architecture Program Voltage Optimization
1st page program

X1
X1
“0” “1” X2
X2
Vth
1st page data : “1” “0”
2-level cell 4-level cell
2nd page program

Two bits in a cell are
“0” “1” “2” “3” assigned to two row
addresses.
Vth
1st page data : “1” “0” “0” “1”
In average, 1.5 operations.
2nd page data : “1” “0” Twice faster than WL0, 31 : Higher capacitive coupling with word-lines.
conventional scheme. Initial program voltage is set lower.
Optimized program voltage accelerates the programming.
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68. T. Hara, ISSCC 2005, pp. 44-45.
Problems : FG-FG interference Solution : FG-FG Coupling Compensation

[3-step programming] [Programming order]
Step 1
Step2
Step3
p
Step 1. The memory cell is ROUGHLY programmed.

FG-FG coupling shifts the Vth of a memory cell as the
Cells are programmed BELOW the target Vth.
neighboring cell are programmed. Step 2. Neighboring cells are programmed.
To tighten the Vth distribution, ⊿Vpgm is decreased, Step 3. The memory cell is PRECISELY programmed.
causing a slow programming. FG-FG coupling is suppressed by 90%.
The Vth modulation becomes significant as the memory Large ⊿Vpgm enables a fast programming.
cell is scaled down. J.D. Lee, EDL 2002, pp. 264-266.
M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90. N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.
Random Access : High Speed Read Random Access : High Speed Read (Cont’)
Problems of MLC read Solution : Multi-page Cell Architecture
Number of memory cells Number of memory cells
“0” “1” “2” “3” “0” “1” “2” “3”
X1
X1
X2
Vth Vth X2
Y1 Y2 Y1 Y2 1st page data : “1” “0” “0” “1”
① ② ③ 2nd page data
d t : “1” “0”
MLC SLC
Two bits in a cell are
Two bits in a cell are assigned ② ① ③
“1”-read “1”-read
assigned to two row
to two column addresses.
1st page read : ②, ③ Æ EXOR addresses.
3 operations (“1”-, “2”- and
In average, 1.5 operations.
“2”-read “3”-read) required. 2nd page read : ①
Twice faster than
Long random read.
conventional scheme.
“3”-read
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

S. Lee, ISSCC 2004, pp.52-53.
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Sequential Access : High Speed Programming Parallel Operation : Increase Page Size
Page size trend
Parallel Operation By increasing the word-line length, the page size has been
extended to increase the write and read throughput.
Increase page size 9000
Bit-line
Multi-page operation 8000
7000
Page
Multi-chip operation (Interleaving)
e (Byte)
6000
5000 ・・・
T be
To b discussed
di d in
i “NAND C
Controller
t ll Circuit
Ci it Design”
D i ” section
ti
Page size
4000
Pipeline Operation 3000
2000
Page buffer
Write/Read Cache 1000
Cache Page Copy

0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Design rule
But, the large page size also causes problems.

Noise issue due to the large RC delay of a word-line
Parallel Operation : Increase Page Size (Cont’) Parallel Operation : Increase Page Size (Cont’)
Problems : SG-WL noise Solution : Raise neighboring SG BEFORE bit-line discharge
[Conventional read/verify-read]
Bit-line
SG-WL capacitive
SGD coupling
Selected 1.5V
WL31
WL bounce
WL0
SGS Read failure
Bit-line Bit-line
precharge discharge
K. Takeuchi, ISSCC 2006,pp.144-145. K. Takeuchi, ISSCC 2006,pp.144-145.
Parallel Operation : Increase Page Size (Cont’) Parallel Operation : Increase Page Size (Cont’)
Problems : WL-WL noise Solution
K. Takeuchi, ISSCC 2006,pp.144-145. K. Takeuchi, ISSCC 2006,pp.144-145.
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Parallel Operation : Multi-page Operation Pipeline Operation : Write/Read Cache

Multi-page operation Pipelining of data-in/out & cell read/write
Operate multi-page simultaneously to increase the write/read Implement data cache in NAND
throughput. Input /output data to the data cache during cell read/program
[Write Cache Example : 0.13um 1Gbit NAND]

[Multi-page operation] 0.25um 256Mb NAND
K. Imamiya, ISSCC 1999, pp.112-113.

Data Cache H. Nakamura, ISSCC 2002, pp.106-107.
Outline SSD Performance
SSD, Memory System Innovation Random access

[Data transfer size in PC application]
OS changes such as
NAND Overview directory entry and file
system metadata
NAND Circuit Design Application S/W change
SSD Overview 50% of data is < 4KB.

R d
Random access mainly
i l
NAND Controller Design decides the performance
of PC. K.Grimsrud, IDF2006, MEMS004.

Sequential access
Green IT with SSD Boot
Summary Hibernation
SSD Performance (Cont’) SSD Performance (Cont’)

Sequential access
Random access
NAND : Single chip operation NAND : 4 chip interleaving
Read Write Erase Read Write Read Write

NAND (SLC) 25MB/sec 20MB/sec 100MB/sec 80MB/sec
NAND (SLC) 25us 300us 1ms
NAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/sec
NAND (MLC) 50us 800us 1ms
HDD 80MB/sec 80MB/sec ‐ ‐
HDD 3ms 3ms N.A.
[Block diagram of SSD w
w. interleaving function]
Erase are hidden by operating the erase during the idle period.
SSD (SLC) : Comparable read and
write performance with HDD.
Read : SSD with SLC and MLD has a great advantage over HDD. SSD (MLC) : Comparable read
Write : SSD still has a performance advantage. Write performance performance. By introducing 8chip
can be an issue in the future if the NAND performance degrades by interleaving, the write performance
scaling the memory cell or increasing the number of bits per cell. can be comparable with HDD.
C. Park, NVSMW 2006, pp.17-20.
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SSD Performance (Cont’) Garbage Collection & Slow Random Write

Slow random write problem System performance degradation of a large block
Page : program/read unit Block : Erase unit [Frequent block copy]
70nm 8G MLC 56nm 8G MLC
(ISSCC2005) (This work)
(ISSCC2006)
Bitline
Old block
Bitline 32WLs 32WLs

① Cell read
New block
Bitline ③ Cell program
4KB page (max) 8KB page (max)
512KB block 1MB block Page buffer
② Data-out,
ECC, Data-in NAND
2 Select-gate 2 Select-gate System performance controller
32 Word-lines Source-line 32 Word-lines degradation
Block copy time
In case a part of the block is over-written, a block copy = (T_Cell read+T_Data_out+TECC+T_Cell program)
operation is performed. Fast block copy required ×(# of pages per block)
= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Pipeline Operation : Cache Page Copy Smaller Block Size: All Bit-line Architecture
Solution : Fast block copy All bit-line architecture
Step1 Step2 Step3 Step4 # of pages in a block is half.
Old block Old block
Old block
Page i
Old block
Block copy time is also half.
Page i+1
56nm NAND 43nm NAND
Cell Read Cell read (Alternate bit-line architecture) (All bit-line architecture)
New block New block New block New block
Cell program
Page buffer Page buffer Page buffer

Page buffer
Data-out Data-out
NAND ECC NAND NAND ECC NAND
controller controller controller controller
Step 4 : Pipelining of programming Page i

and data out / ECC of Page i+1.
Fast block copy K. Takeuchi, ISSCC 2006, R. Cernea, ISSCC 2008,pp.420-421.

K. Takeuchi, ISSCC 2006,pp.144-145. pp.144-145. K. Kanda, ISSCC 2008, pp.430-431.
Solution for Slow Random Write SSD Power Consumption

Fast pipeline block copy operation Power consumption
Smaller block size (All bit-line architecture) NAND : Single chip operation NAND : 4 chip interleaving
Page based data allocation Read Write Read Write
NAND (SLC) 20mA 20mA 80mA 80mA
Not to overwrite an old page but write data to
NAND (MLC) 20mA 20mA 80mA 80mA
an empty page. HDD >300mA >300mA ‐ ‐
Change the logical-physical address table
table.
In SSD, additional current (~100mA) are consumed in the
NAND controller, RAM and IO.
Actual Power Consumption

Old page New page In all modes, the power consumption of SSD is smaller
D. Barnetson, Electonic Journal 192th Technical Symposium, 2008, pp.91-102. than HDD.
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SSD Reliability SSD Reliability (Cont’)

SSD is robust. Failure mechanism of NAND
No mechanical parts. Program disturb
Need to be careful in PC/server application During programming, electrons are injected to
Portable consumer electronics application unselected memory cells.
(Digital still cameras, MP3 players, Camcorders) Read disturb
Effective data retention time << 10years During read,
read electrons are injected to unselected
Data quickly transferred to PC or DVD memory cells.
through USB drive and memory cards. Write/Erase endurance & Data retention
Most probably data backup in PC As the Write/Erase cycles increase, damage of
PC/Enterprise server application the tunnel oxide causes a leakage of stored
Higher reliability required w.o. backup charge.
Need longer data retention time : 5-10 years
SSD Reliability (Cont’) SSD Reliability (Cont’)

“Classic” program disturb “Modern” program disturb
Program inhibit Program
Bitline (Vcc) Bitline (0V)
Vcc
Vpgm
(18V)
Vpass
(10V)
Vpass disturb cell
Vpgm disturb cell 10V
18V J. D. Lee, NVSMW 2006, pp. 31-33.
Vpass K.T.Park, SSDM 2006, pp.298-299.
(10V) D S
0V
0V
D ～8V S
Hot carriers generated at the select gate edge inject
Vcc
into the memory cell causing a Vth shift.
The Vth shift can be reduced by increasing SG-WL
Both selected and unselected cells suffer from the disturb. space.
K. D. Suh, ISSCC 1995, pp.128-129.

“Modern” program disturb (Cont’)
Read disturb
Bitline (0.8VÆ0V)
Vread (4.5V)
4.5V
Selected word-line
(0V)
D 0V S
Vread (4.5V)
Weak program bias condition

Vread (4.5V)
Unselected word-lines suffer
Select Tr. Dummy Tr. WL0 0V
from the read disturb.
The Vth shift can be reduced by adding dummy WL.
K.T.Park, SSDM 2006, pp.298-299.
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Program disturb and read disturb summary Write/Erase Endurance & Data Retention
Program disturb and read Page assignment of MLC Endurance : how many times data are written
disturb is a “bit error” not a Data retention : how long the data remains valid
“burst error”. X1
Clear correlation between endurance and data
X1 retention
Two bits in MLC are assigned to X2
different pages. X2 Damages to the tunnel oxide during write and
Even if one MLC cell fails, one bit in erase cause the data retention problems.
two pages fails. 2-level cell 4-level cell Traps are generated during write and erase.
The unlucky cell with traps results in a leakage
ECC(Error correcting code) K. Takeuchi, Symp. on VLSI Circuits
1997, pp. 67-68.
path, causing the charge transfer.
effectively corrects the bit error. The leakage current is called SILC (Stress
Existing ECC corrects 4-12bit errors Induced Leakage Current).
per 512Byte sector. To guarantee data retention, Write/Erase cycles
K. Prall, NVSMW 2007, pp. 5-10.
are limited to 100K (SLC) or 10K (MLC).
SSD Reliability (Cont’) Outline

100K (SLC) or 10K(MLC) W/E cycles acceptable?
W/E cycles estimation for PC
32GB SSD NAND Overview
Usage scenario : 2~5GB/day (#)
Service for 5years
NAND Circuit Design
100% efficient wear levelingg SSD Overview
(365 days/year) x 5years / (32GB / 2~5GB/day)
= 114~285 W/E cycles
NAND Controller Design
114~285 cycles are far below the NAND limitation Operating System for SSD
of 100K for SLC or 10K for MLC.
Actual W/E cycles are higher for the file
Green IT with SSD
management such as garbage collection. Summary
(#) W.Akin, IDF 2007_4, MEMS003.
Y.Kim, Flash Memory Summit 2007.
SSD SW Architecture HW Architecture

OS
File system Block diagram (Single channel)
Low level driver
ATA I/F
SSD
NAND Controller
Host I/F
Flash Translation Layer (FTL)
Bad block management Wear-leveling

Address translation from Interleaving
logical address to physical
address of NAND ECC
NAND I/F
HDD-like architecture : DRAM buffer to hide NAND random access
High power consumption
NAND Flash Memory High cost
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HW Architecture (Cont’) High Speed Technology

Block diagram (Multi-channel) Interleaving : Sequential Parallel Write
DRAM eliminated :
Random access of NAND
is faster than HDD.
Low p power consumption
p
Low cost
Multi-channel
Parallel operation
High bandwidth
2-channel 4-way interleaving

Max write throughput : 80MB/sec for MLC.
HW driven automatic operation.
C. Park, NVSMW 2006, pp.17-20. C. Park, NVSMW 2006, pp.17-20.
High Reliability Technology High Reliability Technology (Cont’)

Wear-leveling Example of wear-leveling
Problem If the block is occupied with old data, data is programmed
Write/Erase cycle of NAND is limited to 100K for SLC and 10K to a new block.
for MLC. If there is no free block, the invalid block are erased.
Solution
Write data to be evenly distributed over the entire storage. Block 1 Block 1
Count # of Write/Erase cycles of each NAND block. Block 2 Block 2
Bl k 3
Block Bl k 3
Block
Based on the Write/Erase count, NAND controller re-map
Old file Block 4 Block 4 Block 4 Æ Invalid
the logical address to the different physical address. Block 5 Block 5
Block 6 Block 6
Wear-leveling is done by the NAND controller (FTL), not by Block 7 Block 7
Rewrite
the host system. Block : Erase unit
Block 8
old file
Block 8
Block 9 Block 9
Bitline
Bitline
Empty block New File Write new file to

Bitline an empty block
High Reliability Technology (Cont’) High Reliability Technology (Cont’)

Dynamic wear-leveling
Static data
Data that does not change such as system data Write/Erase count
Red : Static data such as system data.
Blue : Dynamic data such as user data
(OS, application SW).

Dynamic data
Data that are rewritten often such as user data.
Dynamic wear-leveling
Wear-level only over empty and dynamic data. Physical block address
Static wear-leveling Block with static data is NOT used for wear-leveling.
Wear-level over all data including static data. Write and erase concentrate on the dynamic data block.
N.Balan, MEMCON2007.
SiliconSystems, SSWP02.
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High Reliability Technology (Cont’) High Reliability Technology (Cont’)

Static wear-leveling Bad Block Management
Write/Erase count Red : Static data such as system data. Program/Erase characteristics vs. endurance
Blue : Dynamic data such as user data
Physical block address

Wear-level more effectively than dynamic wear-leveling.
Search for the least used physical block and write the data to
the location. If that location As the Write/Erase cycles increases, erase failure occurs,
Is empty, the write occurs normally. resulting in a bad block.
Contains static data, the static data moves to a heavily The NAND controller detects and isolates the bad block.
N.Balan, MEMCON2007.
used block and then the new data is written. SiliconSystems, SSWP02. Y.R. Kim, Flash Memory Summit 2007.
High Reliability Technology (Cont’) Outline

ECC (Error Correcting Code)
To overcome read disturb,
program disturb and data NAND Overview
retention failure, ECC have to
NAND Circuit Design
be applied.
Since failure pattern is SSD Overview
random, BCH is sufficient. NAND Controller Design
Existing NAND controller
can correct 4-12bit error
per 512Byte sector. Green IT with SSD
NAND with embedded ECC is Summary
also published. R. Micheloni, ISSCC2006, pp.142-143.
Why OS? New Memory System: NAND/HDD Combo

Motivation NAND as a cache Multi-drive of NAND/HDD
Intel Robson SanDisk Vaulter Disk
Microsoft Ready Boost NAND : OS data
Existing OS is optimized for magnetic drives.
HDD : User data
Current SSD based PC uses the conventional
OS and just replace HDD with SSD.
To achieve the best performance and reliability
of SSD, OS especially file system should be
optimized.
Windows 7 will treat SSD differently from HDD.
H. Pon, NVSMW 2007.
http://www.sandisk.com/Assets/File/pdf/
oem/Vaulter_brochure.pdf
Temporary solution until NAND cost becomes

comparable with HDD cost.
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MLC/SLC Hybrid SSD Performance Optimization

Future Direction : Hybrid SSD with SLC and MLC
Concept : Right device for the right use. Sector size optimization
Enjoy the Benefit of both SLC and MLC.
Minimum write/read unit of NAND is a page.
SLC : Fast and highly reliable but low capacity.
Typical page size is 4-8KByte.
Use SLC as a cache or system data storage.
A page is written only ONCE to avoid the
MLC : Large capacity but slow. Use MLC as user data storage. Page
program disturbance.
OS support essential: SSD does NOT know the contents of the file.
Toshiba LBA
LBA-NAND
NAND
With current OS having 512Byte sector,
Samsung Combo SSD J. Elliott, WinHEC2007.
SATA-III
http://www1.toshiba.com/taec/index.jsp
one sector write wastes >80% of data in a page.
MLC SATA-II 48/64/128/256/512GB
(Multi Level Cell) 32/48/64/128/256GB

SATA-II
16/32/48/64/96/128GB SATA-III
56/112/224/336/448GB
・・・
SATA-II
28/56/112/168/224GB 1 sector Remaining portion
SATA-III
SATA-II 32/64/128/192/256GB write becomes garbage.
Combo
14/28/56/84/112GB
Spansion MirroBit Eclipse
LBD(Long Block Data) sector standard (Windows Vista) :
SATA-II
http://www.spansion.com/products/MirrorBit_Eclipse.html
(SLC+MLC) 16/32/64/96/128GB
SATA-I
8/16/32/48/64GB
SATA-II
8/16/32/48/64GB
SLC 4KByte sector size fits better with SSD.
PATA
4/8/16/32GB (Single Level Cell)
R/W Speed: 57/32 64/45 100/80 160/160 800/800 1300/1300
2006 2007 2008 2009 2010
Frequent Garbage Collection Page Size Trend

System performance degradation of a large block As the page size increases as NAND is shrinking,
[Frequent block copy]
70nm 8G MLC 56nm 8G MLC larger sector size such as 64KByte or 128KByte
(ISSCC2005) (This work)
(ISSCC2006)
Old block
is required.
9000 1200
32WLs 32WLs
8000
① Cell read 1000
7000
yte)
New block
e)
800
Page size (Byte
6000
Block size (KBy

③ Cell program 5000
4KB page (max) 8KB page (max) 600
4000
512KB block 1MB block Page buffer
3000 400
② Data-out,
2000
ECC, Data-in NAND 200
System performance controller
1000
degradation 0 0
Block copy time 0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm 0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Design rule Design rule
= (T_Cell read+T_Data_out+TECC+T_Cell program)
Fast block copy required ×(# of pages per block)
= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Reliability Optimization Reliability Optimization (Cont’)

Enhanced Write Filter (Windows Embedded) SMART
Decrease write/erase cycles of NAND, extending the NAND (Self-Monitoring, Analysis and Reporting Technology)
lifetime.
Control the file allocation to store frequently rewritten file in
Monitor the storage and report/predict the failure.
DRAM and not to access NAND.
SMART for HDD is NOT smart because it is very difficult to
Enhanced Write Filter (EWF) is located between file system
predict the mechanical failure.
and low level driver interfacing with SSD.
(Google report,
report http://209.85.163.132/papers/disk_failures.pdf)
http://209 85 163 132/papers/disk failures pdf)
OS/Application SW support essential: Again, SSD does NOT
know the contents of the file. SMART for SSD can be really smart.
Enhance Product lifetime can be predicted because the failure rate is
Application
Write Filter highly correlated with the write/erase cycles.
SSD Predict the SSD lifetime by monitoring the write/erase
cycles and replace SSD before the fatal failure occurs.
File System Low-level Driver
http://msdn2.microsoft.com/en-us/library/ms912909.aspx http://www.tdk.co.jp/tefe02/ew_007.pdf
13
2008/12/8
Outline Green IT : Power Crisis of Data Center

Data through internet is increasing drastically.
SSD, Memory System Innovation In the U.S, power consumption at the data center
NAND Overview doubled during last 5 years. (5 nuclear power plants!)
In 2025, the data increases by 200 times and the power
NAND Circuit Design consumption increases by 12 times.
SSD Overview
NAND Controller Design Data Center

Green IT with SSD
Power increase
Summary of HDD
Replace HDD with SSD Problems of NAND Flash Memory

Reliability
Low write/erase cycles: Currently <10K cycles (MLC)
and decreasing as scaling down memory cells.
Æ >100K cycles required
Power Consumption
p
SSD Because of the scaling, the parasitic capacitance
(NAND Flash) increases and the power consumption doubles.
Æ Low power memory device required
HDD Capacity
Currently Gbyte Æ TByte required
Operation Current Trend of NAND Fe(Ferroelectric)-NAND Flash Memory

In the scaled VLSIs, most power is consumed to NAND Flash Memory w. Ferroelectric Transistor
charge and discharge signal-lines. Scalable below 20nm
Inter signal-line capacitance, Cwire-wire drastically Low voltage/power operation: 20VÆ5V
increases to keep the low signal-line resistance.
Write/Erase cycles: 10K cyclesÆ100M cycles
100
Æ Most suitable for data server application
A]
Operation current [mA
8080
6060
Cwire-wire Cwire-wire M Pt
4040 F SrBi2Ta2O9
2020 I Hf-Al-O MFIS Structure
n+ n+ (Metal-Ferroelectric-
00
10 20 30 40 50 60 70
10 20 Feature
30 40 size
50 [nm]
60 70 Cwire-wire Cwire-wire p-Si Insulator-Semiconductor)
S. Sakai, NVSMW 2008, pp.103-104.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
14
2008/12/8
Operation Principle of Fe-NAND Flash Scalable below 20nm

Low voltage operation Ferro electricity is maintained in 20nm size.
SrBi2Ta2O9 (SBT)
0V 5V
BL BL TEM Photograph
a = 0.5506 nm
M M SrBi2Ta2O9
SGD F F Sr b = 0.5534 nm ~ 400nm
FeFET I I c = 2.498 nm
WL0 n+ n+ n
n+ n+ Bi Hf-Al-O
~ 10nm
p-well Si p-well Si Ta IL
WL31 5V 0V O Si
SGS Erase Program c
Source Line IL: Interfacial layer
b major component – SiO2
S. Sakai, NVSMW 2008, pp.103-104. a S. Sakai, NVSMW 2008, pp.103-104.
10 Year Data Retention Excellent W/E Cycles up to 100M

1.1
Fe-NAND 1.0
0.9
Vth (V)
-4
10
On states 0.8 Erased
urrent, Id (A)
10
-6 M Pt Programmed
F SrBi2Ta2O9 0.7
-8 1st 37.0 days
10 2nd I Hf-Al-O 0.6
3rd
n+
n n+
Drain Cu
-10
10
10 4th 33 5 d
33.5 days 0.5
0 5
p-Si 10
3
10
4
10
5
10 10
6
10
7 8
-12
10 Number of Cycles S. Sakai, NVSMW 2008, pp.103-104.
10 years
-14 Off states
10
0 2 4 6 8
10 10 10
Time, t (s)
10 10
Buffer layer improves Si‐ NAND
interface characteristics.
Y.R. Kim, Flash Memory Summit 2007.
Co-design of NAND and Controller Circuits Co-design of NAND and Controller Circuits
By co-designing both NAND and NAND controller circuits,
the power consumption of SSD is reduced by 60%.
100
CE1, R/B1
• Low Power Circuit Technology
Operation current [mA]
CE2, R/B2 CE3, R/B3 23% reduction

CE4, R/B4 8080 系列1
Conventional
系列2
Selective BL precharge
系列3
NAND
NAND
Chip1
NAND
Chip2
NAND
Chip3
NAND
Chip4
6060
& Advanced SL program – Selective bit-line precharge scheme
48%
Controller
4040 reduction
– Advanced source-line program
NAND Flash Power Detect
((PD))
2020
O
Memory 00
ALE, CLE, RE, WE, WP, IO 10 20 30 40 50 60 70
10 20 Feature
30 40 size
50 [nm]
60 70
Current waveform
of NAND Chip1
• Low Noise Circuit Technology
Time
Current waveform
of NAND Chip2 – Intelligent interleaving
Time
Current waveform
of NAND Chip3
Time
Current waveform
of NAND Chip4
Time
NAND Controller K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
15
2008/12/8
SSD Write Performance NAND Bit-line Capacitance Trend

• Interleaving: write N NAND chips in parallel • Inter bit-line capacitance, CBL-BL drastically
Performance_SSD = N × Performance_NAND increases to keep the low bit-line resistance.
Channel 1
NAND NAND NAND NAND

Chip1 Chip2 Chip15 Chip16
NAND
CBL-BL CBL-BL CBL-BL CBL-BL
・・
Controller
Channel 4 10
Bit-line capacitance [a.u.]

NAND NAND NAND NAND 8
Chip1 Chip2 Chip15 Chip16
6
• Limitation of N 4
N × I_NAND < Icc_constraint 2
• Key NAND design issue: 0

10 20 30 40 50 60 70
10 20 30 40 size
Feature 50[nm]
60 70 43nm 16Gb NAND
Decrease I_NAND to maximize N K. Kanda, ISSCC, 2008.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Current & Performance Trend Multi-level Cell Program

NAND operation current SSD performance
Bit-by-bit Program Number of memory cells
SSD Perforrmance [MByte/sec]
100
100
100 Algorithm Erased state “A” “B” “C”
Operattion current [mA]
8080
8080 Data load
6060
6060 Vth
Program pulse VA VB VC
4040 4040 1st page program 2nd page program
2020 2020 No Verify‐read “A”-program “B”-program

& ”A”verify & ”B”verify
00 0 010 20 30 40 50 60 70
10 20 30 40 50 60 70
10 20 30 40 size
Feature 50 [nm]
60 70 10 20 30 40 size
Feature 50 [nm]
60 70 All cells
programmed ?
“C”-program
C_bit‐line↑ Æ I_NAND ↑ Æ N ↓ Æ Performance_SSD↓ Yes & ”C”verify
End
• Low power circuit of NAND required.
Conventional Verify Read Selective Bit-line Precharge Scheme

• All bit-lines are precharged irrespective of the program
data. • During verify, precharge bit-line based on the program
data in the page buffer.
• Page based program
• Skip unnecessary bit-line precharge and save current
Æ 8KByte(Page size) bit-lines are precharged.
during verify. Page Buffer Bit-line Bit-line
Æ Total bit-line capacitance > 200nF!
Number of memory cells • Area overhead < 1%
Bit-line
Bit line (0.8VÆ0V) “0” “1” * * *
N2 PRE2
Vread (4.5V) Additional * *
Selected word-line Vth
(Read voltage : 0V)
Transistor N3 N1 PRE1
N3
Read voltage N1
Bit-line voltage PRE1 PRE2 Latch1
N2 Latch2
Vread (4.5V)
“1” “A”-verify “High” “High”
“B”-verify “High” “Low”
“0”
IO CSL /IO
Vread (4.5V) Time
“C”-verify “Low” “High”
0V K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
16
2008/12/8
1st Page Program (“A”-verify) 2nd Page Program (“B”-verify)

Erased state “A” “B” “C”
Erased state “A” “B” “C”
Vth
Vth VA VB VC
VA VB VC
1st page program 2nd page program
1st page program 2nd page program
[Conventional] [Proposed] [Conventional] [Proposed]
“A”-program complete / incomplete “A”-program complete “B”-program complete / incomplete “B”-program complete
Program inhibit Program inhibit “A”-program incomplete “C”-program complete / incomplete “C”-program complete / incomplete
Program inhibit Program inhibit “B”-program incomplete
Bit-line Bit-line Bit-line Bit-line
Word-line Word-line Word-line Word-line
VA VA VB VB
Time Time Time
Bit-line Time Bit-line Bit-line
Bit-line Bit-line Bit-line discharge Bit-line Bit-line discharge
precharge discharge precharge discharge precharge precharge
2nd Page Program (“C”-verify) Result – Selective BL precharge

Erased state “A” “B” “C” • 23% current reduction.
• 50% performance improvement.
yte/sec]
Vth 100
23% reduction 100
Operation current [[mA]
VA VB VC 100
8080 系列1
Conventional
SSD Performance [MBy

1st page program 2nd page program Selective BL precharge
系列2
8080
6060
6060
[Conventional] [Proposed]
4040 4040
50%
“B”-program complete / incomplete “B”-program complete / incomplete improved
“C”-program complete / incomplete “C”-program complete Conventional
系列1
Program inhibit Program inhibit 2020 2020
“C”-program incomplete
系列2
Bit-line Bit-line 00 0 010
10 20 30 40 50 60 70 20 30 40 50 60 70
Word-line VC Word-line VC 10 20 Feature
30 40 size
50 [nm]
60 70 10 20 Feature
30 40 size
50 [nm]
60 70
Time Time
Bit-line Bit-line discharge Bit-line Bit-line discharge
precharge precharge
Source-line Program (VLSI’99) Capacitance Comparison

• Save current during program pulse. Bit-line
• Bias 2.5V from a low capacitance source-line. Bit-line

• Low voltage swing for a high capacitance bit-line
Bit-line
[Conventional] [Source-line program]
Bit-line (2.5V) Bit-line (1V)
2 SG, 64 CG 2 SG, 64 CG
SGD Source-line
SGD
(4.5V) (0VÆ0.7V)
Vpgm V
Vpgm Cbit-line = Cwire(bitline) + Cjunction
(18V) (18V)
Vpass
Csource-line = Cwire(source-line) + Cjunction
Vpass
(10V) (10V) Inhibit
Inhibit voltage
voltage
Cwire(bitline) >> Cjunction, Cwire(source-line)
Vpass Vpass Demonstrated in
(10V) (10V)
SGS
0.25um NAND
SGS
(0V) (4.5VÆ0V)
Source-line (2.5V)
Cbit-line >> Csource-line
Source-line (1V)
K. Takeuchi, Symposium on VLSI Circuits, pp.37-38, 1999. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
17
2008/12/8
Advanced Source-line Program Read Operation

• Total source-line capacitance in a chip exceeds 20nF for • All Source-line switch: ON
sub-50nm NAND.
• Minimize the source-line resistance.
• Hierarchical source-line structure
• Only metal layout change; No area overhead
• Suppress the source-line noise.
Sub-array Sub-array
Sub-array Sub-array
Bit-line
Bit-line
Bit-line
Bit-line
Bit-line
Bit-line
Row decoder Row decoder Row decoder Row decoder Row decoder
Local source-line
Local source-line Source-line Local source-line Source-line
Source-line Local source-line Source-line ON
Switch decoder decoder
decoder decoder
Global source-line
Global source-line ON
Program Operation Result – Advanced SL program
• Only one of 16 sub-arrays activated

• 60% current reduction.
• Source-line capacitance: 90% reduced
• 250% performance improvement.
Sub-array Sub-array
yte/sec]
Bit-line
100
23% reduction 100
100
Operation current [[mA]
8080 系列1
Conventional
SSD Performance [MBy

Bit line
Bit-line
系列2
Selective BL precharge 8080
系列3
Selective BL precharge 250%
Bit-line 6060 & Advanced SL program 6060 improved
48%
4040 reduction 4040
Conventional
系列1
Local source-line 2020 2020 Selective BL precharge
系列2
Source-line Local source-line Source-line Selective BL precharge
ON 系列3
& Advanced SL program
decoder decoder
00 00
10 20 30 40 50 60 70 10 20 30 40 50 60 70
Global source-line 10 20 Feature
30 40 size
50 [nm]
60 70 10 20 Feature
30 40 size
50 [nm]
60 70
OFF
Intelligent Interleaving Control Circuit

• Disperse the current peak and avoid the • Introduce Power Detect (PD) signal.
power supply noise. • When a NAND starts bit-line precharge &
Bit-line precharge & charge pump ramp-up charge pump ramp-up, PD becomes low.
cause >100mA current peak. • NAND controller issues a write command
when PD is high and NAND is ready.
CE1 R/B1
CE1,
CE2, R/B2 CE3, R/B3 PD Program_Enable1
NAND Chip1 CE4, R/B4 R/B1 (Chip1)
Time
NAND Chip2 PD Program_Enable3
NAND NAND NAND NAND (Chip3)
Time R/B3
NAND Chip1 Chip2 Chip3 Chip4
NAND Chip3 Controller PD Program_Enable2
Time R/B2 (Chip2)
NAND Chip4 Power Detect PD Program_Enable4

● Time (PD) R/B4 (Chip4)
●
●
● ●
ALE, CLE, RE, WE, WP, IO ●
[Current waveform during program and verify]

18
2008/12/8
Current Waveform Summary: Co-design of NAND and Controller Circuits
Current waveform • Co-design of NAND and NAND controller.

of NAND Chip1
Time – To improve SSD speed, decrease the NAND current
Current waveform
of NAND Chip2 and maximize # of NAND operated in parallel.
Time
Current waveform
of NAND Chip3
Current waveform
Time • Two low power circuit technologies proposed.
of NAND Chip4
●
– Selective bit-line precharge
g scheme
Time
●
● – Advanced source-line program
Power Detect
(PD)-signal – 60% current reduction.
R/B1 (chip1)
– 250% SSD performance improvement.
R/B2 (chip2)
R/B3 (chip3)
R/B4 (chip4)
• Intelligent interleaving realizes highly reliable
●
● and high-speed SSD.
●
3D-integrated SSD Summary

First demonstration of 3D-integrated SSD.
With smart Mix & Match, the power decreases by 70%. New Memory System
SLC/MLC Hybrid SSD solves the system bottleneck.
DRAM
MPU Core Logic Emerging Market: Power Crisis at data center
ROM Flash
SSD is expected to save power at data center.
Cache
Analog
3D SiP
3D-SiP Logic
SoC
ROM
Analog Flash Device, circuit and OS innovation required.
DRAM Cache Co-design of NAND and NAND controller circuits
MPU Core
OS optimization such as sector size optimization
Fe(Ferroelectric)-NAND flash memory device
To be presented at ISSCC in Feb. 2009@San Francisco.
3D-integrated SSD circuits
13.2. “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator
for 3D-Integrated NAND Flash SSD”
Thank you!
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
http://www.lsi.t.u-tokyo.ac.jp
Ken Takeuchi Advanced Flash Memory Devices 113
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2008/12/8

SSD, Memory System Innovation SSD, Memory System Innovation

Definition of SSD NAND Flash Memory and SSD Market

SSD : Solid- State Drive PC expected as an emerging application

I. Cohen, Flash Memory Summit 2007.

Memory System Bottleneck SLC NAND as Cache of HDD

Future Memory System Future Direction: Vertical Integration

Key Challenge of SSD Outline

SSD, Memory System Innovation

NAND Flash Memory Page & Block of NAND Flash Memory

43nm 16Gb NAND

Top View of NAND Flash Cell Array MLC vs. SLC

SGD SGD SGS SGS

Simple structure : High scalability, High yield Vth Vth

NAND Operation Principle NAND Operation Principle (Cont’)

9 Unselected cells are biased to the pass voltage, Vread.

NAND Operation Principle (Cont’) Outline

Page Page : 2-4KBytes

NAND Circuit Design Random Access : High Speed Programming

Bit-by-bit Program Verify Scheme

Random Access Data load

High Speed Programming Program pulse 0V

Verify read Constant electric field

G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.

Solution : Multi-page Cell Architecture Program Voltage Optimization

1st page program

Number of memory cells

Number of memory cells

Problems : FG-FG interference Solution : FG-FG Coupling Compensation

Step 1. The memory cell is ROUGHLY programmed.

K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

Pipeline Operation 3000

Write/Read Cache 1000

Cache Page Copy

But, the large page size also causes problems.

SGS Read failure

K. Takeuchi, ISSCC 2006,pp.144-145. K. Takeuchi, ISSCC 2006,pp.144-145.

Parallel Operation : Multi-page Operation Pipeline Operation : Write/Read Cache

[Write Cache Example : 0.13um 1Gbit NAND]

K. Imamiya, ISSCC 1999, pp.112-113.

Outline SSD Performance

SSD, Memory System Innovation Random access

SSD Overview 50% of data is < 4KB.

Operating System for SSD

SSD Performance (Cont’) SSD Performance (Cont’)

Read Write Erase Read Write Read Write

C. Park, NVSMW 2006, pp.17-20.

SSD Performance (Cont’) Garbage Collection & Slow Random Write

Bitline 32WLs 32WLs

Page buffer Page buffer Page buffer

Step 4 : Pipelining of programming Page i

Fast block copy K. Takeuchi, ISSCC 2006, R. Cernea, ISSCC 2008,pp.420-421.

Solution for Slow Random Write SSD Power Consumption

C. Park, NVSMW 2006, pp.17-20.

SSD Reliability SSD Reliability (Cont’)

SSD Reliability (Cont’) SSD Reliability (Cont’)

SSD Reliability (Cont’) SSD Reliability (Cont’)

Weak program bias condition

SSD Reliability (Cont’) SSD Reliability (Cont’)

SSD Reliability (Cont’) Outline

SSD SW Architecture HW Architecture

Flash Translation Layer (FTL)

Bad block management Wear-leveling