A Triangular Mesh Gcncratioii hlethod Suitable for the

Analysis of Complex MOS Device Structures

Shigetaka Kumashiro aad Ikuhiro Yokota

ULSI Device Development Laboratories, NEC Corporation
1120 Shimokuzawn, Sagamihara, Kanagawa 229, Japan

Abstract
A fully automatic triangular mesh generation method which can correctly handle the
MOS inversion current along any arbitrary shaped channel is proposed. The key idea
of this method is to introduce interface protection layer which consists of rectangular
mesh locally conformed to the material interface. The performance of this method is
verified through an oblique and a SLIT[l] transistors simulation.

1 Introduction
To handle any arbitrary shaped device, a number of grid generation methods have been
proposed so far. However, few of them can treat the current flow along the curved Si-Si02
interface correctly. Since the current in the MOS inversion layer flows in parallel with the
interface and the carrier density varies exponentially with the distance from the interface,
the mesh edges must be in parallel with the interface and the control volume thickness must
be uniform along the channel. From this view point, local rectangular mesh conformed to
the interface is preferable to random triangular mesh. Boundary-Fitted-Coordinate mesh
generation[2], [3] is a possibility to solve this problem, but it is very difficult for this method
to achieve fully automatic mesh generation. In this paper, a fully automatic triangular
mesh generation method which can correctly handle the MOS inversion current along any
arbitrary shaped channel is proposed and its performance is verified.

2 Mesh generation algorithm

Flow of the proposed mesh generation algorithm is shown in Fig.1. The key idea of this
method is to introduce interface protection layer which consists of rectangular mesh locally
conformed to the material interface. To avoid the destruction of the interface protection
layer during the Delaunay partitioning, critical geometric parameters ( E , 6,y, A) and repet-
itive Delauiiay partitioning have been introduced. It can be proved that this algorithm
never fails to converge for any arbitrary structure if the following conditions are satisfied:
E < 6 < dmin/2, y > 6 cot( &in /2), X 2 6[2n - 1 + ~ ' l +~0t(&;n/2)]/2n

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 where, E is the minimum distance between the mesh nodes, 6 is a total thickness of an
interface protection layer, &in is a minimum thickness of a domain, y is a minimum
distance between the initial bounda.ry nodes, i$min is a minimum angle formed by the
domain boundaries, X is a mesh node expelling length from the domain boundaries and n
is a number of interface protection layers. Experiment shows that the repetitive loop in
Fig.1 converges within four iterations for typical LOCOS or trench structures. To keep the
analysis accuracy under the automatic environment, mesh smoothing is introduced. The
static force balance equations are solved assuming that mesh edges are replaced by springs
whose spring constant is dependent both on the impurity gradient and the distance from
the interface.

Fig.1 Flow of the proposed mesh generation method.

Effect of the mesh smoothing is shown in Fig.2 in which MOS drain current in the weak
inversion region is compared. In the case of smoothed mesh, current converges quickly
and monotonously as the mesh number increases, while the uniform mesh shows slow and
oscillatory convergence. The Delaunay partitioning is performed so that the mesh node
whose circumferential angle is maximum is connected t o the chord to form a triangle.
CPU-time used for the mesh generation is shown in Fig.3. Most of the CPU time is spent
in the mesh smoothing step and the cost of the repetitive Delaunay partitioning stays small.

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3 Performance verification
To verify the advantage of the proposed method, Id-Vd characteristics of an oblique MOS-
FET shown in Fig.4 are compared between this mesh and the mesh without interface
protection layer. Figure 5 shows these two meshes around the Si-Si02 interface. As for the
no-protection-layer mesh, obtuse triangles at the interface are treated as Fig.13 (b) in [3].
The drain current is significantly underestimat#ed in the case of no-protection-layer mesh as
shown in Fig.6. This is due to the detour of the inversion current as shown in Fig.S(b) which
is caused by zero or very small current path widths at several surface mesh edges. Electrical
characteristics of SLIT transistor[4] was simulated using the proposed mesh. The device
structure was taken from the SEM photograph (Fig.7) and the generated mesh around
the trench corner is shown in Fig.8. Anisotropic mobility model for the inversion carrier
was developed based on the data in [ 5 ] and [6] to cope with arbitrary oriented Si-Si02
interface. Simulation result using this mobility shows large deviation from the measured
data as shown in Fig.S(a). By measuring the actual mobility along the trench wall, this
has been identified as mobility degradation introduced by dry-etching process as has been
reported in [7]. After re-extracting the surface scattering parameters in the mobility model,
simulation result showed good agreement as shown in Fig.S(b). It should be noted that the
no-protection-layer mesh produces current as half as that of the measurement in this case.

4 Summary
In this paper, a fully automatic mesh generation method which can correctly handle the
MOS inversion current along any arbitrary shaped channel has been proposed. The perfor-
mance of this method has been verified through an oblique and a SLIT transistors simula-
tion.

References
[I] M. Sakao et al., “A straight-line-trench isolation and trench-gate transistor (SLIT) cell for giga-bit
DRAMS,” Proc. 199.3 Symp. VLSI Tech. (Kyoto, Japan), May, 1993, pp.19-20.
[a] H. Matsuo et al., “Three-dimensional device simulation with arbitrary curved boundaries using the
Voronoi discretization method,” Proc. 4th SISDEP (Zrcrich, Switzerland), September, 1991. pp.157-
163.
[3] Z. M. V.-Kovacs et al., ‘%oundary fitted coordinate generation for device analysis on composite and
complicated geometries,” IEEE Tmns. Computer-Aided Design, vol.CAD-10, pp. 1242-1250, October
1991.
[4] N. Shigyo et al., “TRIMEDES: A triangular mesh device simulator linked with topography/process
simulation,” Tmns. of the IEICE, vol.E’I1, pp.992-999, October 1988.
[5] T. Sat0 et al., “Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces,” Phys.
Reu. B, vo1.4, pp.1950-1960, September 1971.
[GI S Takagi et al., “Effects of surface orientation on the universality of inversion-layer mobility in Si
MOSFETs,” Eztd. Abst. 22nd SSDM (Sendoi, Jopan), August, 1990, pp.275-278.
[7] C. J. Petti et al., “Characterization of surface mobility on the sidewalls of dry-etched trenches,” 1988
IEDM Tech. Dig. (San Francisco, CA), Dccember, 1988, pp.104-107.

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Fig.2 Effect of the mesh smoothing. Fig.3 CPU-time for the mesh generation.

Fig.4 Structure of an oblique Fig.5 Mesh of the oblique MOSFET by (a) the proposed mesh and (b)
MOSFET. no-protection-layer mesh. Bold lines show the main current paths.

(a) (b)
Fig.7 SEM Photograph of the Fig.6 Id-Vd characteristics of the oblique MOSFET by (a) the proposed
SLIT transistor. mesh and (b) no-protection-layer mesh

(4 (b)
Fig.9 Td-Vd curve of the SLIT transistor using (a) mobility for smooth
Fig.8 Mesh around the trench
surface and ( b ) degraded mobility for dry-etched surface. Larger cur-
corner of the SLIT transistor.
rents are obtained by simulation for both cases.

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