Manual de Transistores Mosfet de Potencia

DL135/D
Rev. 7, Apr-2001
Power MOSFETs
Power MOSFETs
DL135/D
Rev. 7, Apr–2001
 SCILLC, 2001
Previous Edition  1996
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Table of Contents
Power MOSFET Numeric Data Sheet

Listing and Selector Guide Chapter 1: Power MOSFETs
Page Page
Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ChipFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SO–8 MiniMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2: Abstracts
SO–8 FETKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application Note Abstracts . . . . . . . . . . . . . . . . . . . . . . . 1399
EZFET SO–8 Power MOSFETs . . . . . . . . . . . . . . . . 10
Micro8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 3: Case Outlines and Package
TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Dimensions
TSSOP–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SOT–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Case Outlines and Package Dimensions . . . . . . . . . . 1405
SC–70/SOT–323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SC–88/SOT–363 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 4: Index
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
TO–220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TO–247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TO–264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TO–92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IGBTs – Insulated Gate Bipolar Transistors . . . . . . . . 17
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Power MOSFET Numeric Data Sheet Listing
Chapter 1: Power MOSFET Data Sheets

Device Function Page
NGD15N41CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 410 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
NIB6404–5L . . . . . . . . . . . . . . . . . SMARTDISCRETESt 52 Amps, 40 Volts
Self Protected with Temperature Sense N–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . 23
NIMD6302R2 . . . . . . . . . . . . . . . . SMARTDISCRETESt 5 Amps, 30 Volts
Self Protected with Current Sense N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 27
NTD20N03L27 . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
NTD20N06 . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
NTD3055–094 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
NTD3055L104 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level N–Channel DPAK . . . . . . . . . . . . . . . . . 37
NTD32N06 . . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
NTD32N06L . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts, Logic Level N–Channel DPAK . . . . . . . . . . . . . . . . . 44
NTD4302 . . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
NTGS3433T1 . . . . . . . . . . . . . . . . MOSFET –3.3 Amps, –12 Volts P–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
NTGS3441T1 . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts P–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
NTGS3443T1 . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
NTGS3446 . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NTGS3455T1 . . . . . . . . . . . . . . . . MOSFET –3.5 Amps, –30 Volts P–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
NTHD5902T1 . . . . . . . . . . . . . . . . Dual N–Channel 30 V (D–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NTHD5903T1 . . . . . . . . . . . . . . . . Dual P–Channel 2.5 V (G–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NTHD5904T1 . . . . . . . . . . . . . . . . Dual N–Channel 2.5 V (G–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
NTHD5905T1 . . . . . . . . . . . . . . . . Dual P–Channel 1.8 V (G–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
NTHS5402T1 . . . . . . . . . . . . . . . . N–Channel 30 V (D–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
NTHS5404T1 . . . . . . . . . . . . . . . . N–Channel 2.5 V (G–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
NTHS5441T1 . . . . . . . . . . . . . . . . P–Channel 2.5 V (G–S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
NTMD3P03R2 . . . . . . . . . . . . . . . Power MOSFET –3.05 Amps, –30 Volts Dual P–Channel SO–8 . . . . . . . . . . . . . . . . . . . 120
NTMD6N02R2 . . . . . . . . . . . . . . . Power MOSFET 6.0 Amps, 20 Volts N–Channel Enhancement Mode
Dual SO–8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
NTMD6P02R2 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 20 Volts P–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 120
NTMD7C02 . . . . . . . . . . . . . . . . . . Power MOSFET 9.5 Amps, 20 Volts (N–Ch)
4 Amps, 20 Volts (P–Ch) Complementary SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
NTMS10P02R2 . . . . . . . . . . . . . . Power MOSFET –10 Amps, –20 Volts P–Channel Enhancement–Mode
Single SO–8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
NTMS3P03R2 . . . . . . . . . . . . . . . Power MOSFET –3.05 Amps, –30 Volts P–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . 150
NTMS4N01R2 . . . . . . . . . . . . . . . Power MOSFET 4.2 Amps, 20 Volts N–Channel Enhancement–Mode
NTMS4P01R2 . . . . . . . . . . . . . . . Power MOSFET –4.5 Amps, –12 Volts P–Channel Enhancement–Mode
NTMS5P02R2 . . . . . . . . . . . . . . . Power MOSFET –5.4 Amps, –20 Volts P–Channel Enhancement–Mode
NTMSD2P102LR2 . . . . . . . . . . . . FETKYt Power MOSFET and Schottky Diode Dual SO–8 Package . . . . . . . . . . . . . . . 178
NTMSD3P102R2 . . . . . . . . . . . . . FETKYt P–Channel Enhancement–Mode
Power MOSFET and Schottky Diode Dual SO–8 Package . . . . . . . . . . . . . . . . . . . . . . . . 188
NTMSD3P303R2 . . . . . . . . . . . . . FETKYt P–Channel Enhancement–Mode
Power MOSFET and Schottky Diode Dual SO–8 Package . . . . . . . . . . . . . . . . . . . . . . . . 198
NTP27N06 . . . . . . . . . . . . . . . . . . Power MOSFET 27 Amps, 60 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . . 208
NTP45N06 . . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . . 210
NTP45N06L . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts, Logic Level N–Channel TO–220 . . . . . . . . . . . . . . 215
NTP75N03–06 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N–Channel TO–220 and D2PAK . . . . . . . . . . . . . . 220
NTP75N03L09 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N–Channel TO–220 and D2PAK . . . . . . . . . . . . . . 225
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Power MOSFET Numeric Data Sheet Listing (continued)

NTQD6866 . . . . . . . . . . . . . . . . . . Power MOSFET 5.8 Amps, 20 Volts N–Channel TSSOP–8 . . . . . . . . . . . . . . . . . . . . . . . 230
NTTD1P02R2 . . . . . . . . . . . . . . . . Power MOSFET –1.45 Amps, –20 Volts P–Channel Enhancement Mode
Dual Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
NTTD2P02R2 . . . . . . . . . . . . . . . . Power MOSFET –2.4 Amps, –20 Volts Dual P–Channel Micro8t . . . . . . . . . . . . . . . . . 241
NTTS2P02R2 . . . . . . . . . . . . . . . . Power MOSFET –2.4 Amps, –20 Volts Single P–Channel Micro8t . . . . . . . . . . . . . . . . 248
NTTS2P03R2 . . . . . . . . . . . . . . . . Power MOSFET –2.48 Amps, –30 Volts P–Channel Enhancement Mode
Single Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
NTUD01N02 . . . . . . . . . . . . . . . . . Power MOSFET 100 mAmps, 20 Volts Dual N–Channel SC–88 . . . . . . . . . . . . . . . . . . . 262
2N7000 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . . . 264
2N7002LT1 . . . . . . . . . . . . . . . . . . Power MOSFET 115 mAmps, 60 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 267
BS107 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . . 271
BS108 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts, Logic Level N–Channel TO–92 . . . . . . 275
BS170 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 500 mAmps, 60 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . . . 277
BSS123LT1 . . . . . . . . . . . . . . . . . Power MOSFET 170 mAmps, 100 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . 280
BSS138LT1 . . . . . . . . . . . . . . . . . Power MOSFET 200 mAmps, 50 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 284
BSS84LT1 . . . . . . . . . . . . . . . . . . . Power MOSFET 130 mAmps, 50 Volts P–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 289
MGP15N35CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 350 Volts N–Channel TO–220 and D2PAK . . . . . . . . . . . . . . . . 293
MGSF1N02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 316
MGSF1N02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 320
MGSF1N03LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 30 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 324
MGSF1P02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts P–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 328
MGSF1P02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts P–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 332
MGSF2P02HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . 336
MGSF3442VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 20 Volts N–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . 344
MGSF3454VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 30 Volts N–Channel TSOP–6 . . . . . . . . . . . . . . . . . . . . . . . . . . 349
MLD1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level N–Channel DPAK . . . . . 354
MLP1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level N–Channel TO–220 . . . 360
MLP2N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 2 Amps, 62 Volts, Logic Level N–Channel TO–220 . . 366
MMBF0201NLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 372
MMBF0202PLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts P–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 377
MMBF1374T1 . . . . . . . . . . . . . . . Small Signal MOSFET 50 mAmps, 30 Volts N–Channel SC–70/SOT–323 . . . . . . . . . . 382
MMBF170LT1 . . . . . . . . . . . . . . . . Power MOSFET 500 mAmps, 60 Volts N–Channel SOT–23 . . . . . . . . . . . . . . . . . . . . . . 384
MMBF2201NT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts N–Channel SC–70/SOT–323 . . . . . . . . . . . . . . 388
MMBF2202PT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts P–Channel SC–70/SOT–323 . . . . . . . . . . . . . . . 392
MMDF1300 . . . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts Complementary SO–8, Dual . . . . . . . . . . . . . . . . . . . 396
MMDF1N05E . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 50 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 399
MMDF2C01HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts Complementary SO–8, Dual . . . . . . . . . . . . . . . . . . . 404
MMDF2C02E . . . . . . . . . . . . . . . . Power MOSFET 2.5 Amps, 25 Volts Complementary, SO–8, Dual . . . . . . . . . . . . . . . . . 416
MMDF2N02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 451
MMDF2N05ZR2 . . . . . . . . . . . . . . Power MOSFET 2 Amps, 50 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 459
MMDF2P01HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts P–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 468
MMDF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts P–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 477
MMDF3N02HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 503
MMDF3N06VL . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 60 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 540
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MMDF5N02Z . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 551
MMDF7N02Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 20 Volts N–Channel SO–8, Dual . . . . . . . . . . . . . . . . . . . . . . . 569
MMDFS2P102 . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P–Channel SO–8, FETKYt . . . . . . . . . . . . . . . . . . . 579
MMDFS6N303 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 30 Volts N–Channel SO–8, FETKYt . . . . . . . . . . . . . . . . . . . 589
MMFT2406T1 . . . . . . . . . . . . . . . . Power MOSFET 700 mAmps, 240 Volts N–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . 605
MMFT2955E . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts P–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . 610
MMFT2N02EL . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts N–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . 619
MMFT3055V . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts N–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . 628
MMFT3055VL . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts N–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . 637
MMFT5P03HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 30 Volts P–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . 646
MMFT960T1 . . . . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 60 Volts N–Channel SOT–223 . . . . . . . . . . . . . . . . . . . . . 656
MMSF10N02Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 20 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
MMSF10N03Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
MMSF1308 . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
MMSF1310 . . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
MMSF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
MMSF3300 . . . . . . . . . . . . . . . . . . Power MOSFET 11.5 Amps, 30 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . 705
MMSF3P02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts P–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
MMSF5N02HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
MMSF7N03Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts N–Channel SO–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
MPF930 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 2 Amps, 35, 60, 90 Volts N–Channel TO–92 . . . . . . . . . . . . . . . 761
MTB1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts, Logic Level N–Channel D2PAK . . . . . . . . . . . . . . . 765
MTB20N20E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 200 Volts N–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 772
MTB23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts P–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 781
MTB30N06VL . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts, Logic Level N–Channel D2PAK . . . . . . . . . . . . . . . 798
MTB30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts P–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 807
MTB36N06V . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts N–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 816
MTB50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level P–Channel D2PAK . . . . . . . . . . . . . . . 852
MTB55N06Z . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 60 Volts N–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 880
MTB60N05HDL . . . . . . . . . . . . . . Power MOSFET 60 Amps, 50 Volts, Logic Level N–Channel D2PAK . . . . . . . . . . . . . . . 885
MTB60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts N–Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 895
MTB75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level N–Channel D2PAK . . . . . . . . . . . . . . . 905
MTD1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
MTD15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
MTD15N06VL . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
MTD20N03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level N–Channel DPAK . . . . . . . . . . . . . . . . 960
MTD20N06HD . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
MTD20N06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level N–Channel DPAK . . . . . . . . . . . . . . . . 980
MTD20P03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level P–Channel DPAK . . . . . . . . . . . . . . . . 990
MTD20P06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level P–Channel DPAK . . . . . . . . . . . . . . . 1000
MTD2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts P–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
MTD3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
MTD3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
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MTD3302 . . . . . . . . . . . . . . . . . . . Power MOSFET 18 Amps, 30 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
MTD4N20E . . . . . . . . . . . . . . . . . . Power MOSFET 4 Amps, 200 Volts N–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
MTD5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts P–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
MTD6P10E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 100 Volts P–Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
MTDF1N02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts N–Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1093
MTDF1N03HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 30 Volts N–Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1104
MTDF2N06HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 60 Volts N–Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . 1115
MTP10N10E . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . 1123
MTP10N10EL . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts, Logic Level N–Channel TO–220 . . . . . . . . . . . . 1130
MTP12P10 . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 100 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . 1136
MTP1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 30 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1141
MTP1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1148
MTP15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1155
MTP15N06VL . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts, Logic Level N–Channel TO–220 . . . . . . . . . . . . . 1161
MTP23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1181
MTP2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1193
MTP3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1213
MTP3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level N–Channel TO–220 . . . . . . . . . . . . . 1219
MTP30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1231
MTP50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level P–Channel TO–220 . . . . . . . . . . . . . 1261
MTP5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . . 1280
MTP60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1286
MTP6P20E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 200 Volts P–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1293
MTP75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level N–Channel TO–220 . . . . . . . . . . . . . 1299
MTP7N20E . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 200 Volts N–Channel TO–220 . . . . . . . . . . . . . . . . . . . . . . . . 1320
MTSF1P02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts P–Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
MTSF3N02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts N–Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1337
MTSF3N03HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 30 Volts N–Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1348
MTW32N20E . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 200 Volts N–Channel TO–247 . . . . . . . . . . . . . . . . . . . . . . . 1359
MTY55N20E . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 200 Volts N–Channel TO–264 . . . . . . . . . . . . . . . . . . . . . . . 1383
VN0300L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . . 1389
VN2222LL . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 150 mAmps, 60 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . . 1391
VN2406L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . 1394
VN2410L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts N–Channel TO–92 . . . . . . . . . . . . . . . . 1396
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Power MOSFET Selector Guide
Table 1. ChipFET – Case 1206A

V(BR)DSS Max RDS(on) @ VGS ID (cont) PD
(Volts) 10 V 4.5 V 2.5 V 1.8 V Amps Device (Notes 1. & 2.) Page
Min (Ω) (Ω) (Ω) (Ω) (Note 8.) (Note 3.) (Watts) Max Configuration No.
30 0.035 0.055 – – 6.7 NTHS5402T1 1.3 Single N–Channel 95
0.085 0.143 – – 3.9 NTHD5902T1 1.1 Dual N–Channel 80
20 – 0.03 0.045 – 7.2 NTHS5404T1 1.3 Single N–Channel 106
– 0.075 0.0134 – 4.2 NTHD5904T1 1.1 Dual N–Channel 90
– 0.060 0.083 – 5.3 NTHS5441T1 1.3 Single P–Channel 109
(Note 7.)
– 0.065 0.110 – 4.7 NTHS5443T1 1.3 Single P–Channel 112
– 0.155 0.260 – 2.9 NTHD5903T1 1.1 Dual P–Channel 85
8 – 0.035 0.047 0.062 7.1 NTHS5445T1 1.3 Single P–Channel 114
0.09 0.13 0.18 4.1 NTHD5905T1 1.1 Dual P–Channel 95
Table 2. SO-8 (MiniMOS) – Case 751–06

V(BR)DSS Max RDS(on) @ VGS ID PD
(Volts) 10 V 4.5 V 2.7 V 2.5 V (cont) Device (Notes 1. & 2.) Configuration Page
Min (Ω) (Ω) (Ω) (Ω) Amps (Note 4.) (Watts) Max (Note 6.) No.
60 – 0.130 (Note 5.) – – 3.3 MMDF3N06VLR2 2.0 Dual N–Channel 540
0.100 0.200 – – 3.3 MMDF3N06HDR2 2.0 Dual N–Channel 531
50 0.300 0.500 – – 1.5 MMDF1N05ER2 2.0 Dual N–Channel 399
40 0.080 0.100 – – 3.4 MMDF3N04HDR2 2.0 Dual N–Channel 521
30 0.030 0.039 – – 7.0 MMSF1308R2 2.5 Single N–Channel 681
0.015 0.019 – – 10.0 MMSF1310R2 2.5 Single N–Channel 689
0.0125 0.020 – – 11.5 MMSF3300R2 2.5 Single N–Channel 705
0.040 0.050 – – 6.5 MMSF5N03HDR2 2.5 Single N–Channel 733
0.028 0.040 – – 8.2 MMSF7N03HDR2 2.5 Single N–Channel 742
0.085 0.115 – – 3.05 NTMS3P03R2 2.5 Single P–Channel 150
0.085 0.125 – – 3.05 NTMD3P03R2 2.0 Dual P–Channel 120
0.070/0.200 0.075/0.300 – – 4.1 MMDF2C03HDR2 2.0 Complementary 439
25 0.100/0.210 0.160/0.375 – – 3.0/2.0 MMDF1300R2 1.8 Complementary 396
20 0.025 0.040 – – 8.2 MMSF5N02HDR2 2.5 Single N–Channel 724
– 0.045 0.055 – 4.0 NTMS4N01R2 2.5 Single N–Channel 157
0.250 0.400 – – 2.5 MMSF2P02ER2 2.5 Single P–Channel 697
0.075 0.095 – – 5.6 MMSF3P02HDR2 2.5 Single P–Channel 715
– 0.033 – 0.048 5.4 NTMS5P02R2 2.5 Single P–Channel 171
– 0.014 – 0.020 10.0 NTMS10P02R2 2.5 Single P–Channel 143
1. TC = 25°C
2. See Data Sheet for Applicable Mounting Configuration.
3. Available in Tape and Reel only. T1 suffix = 3000 per reel.
4. Available in Tape and Reel only. R2 suffix = 2500 per reel.
5. VGS = 5.0 V
6. Data for all Complementary Devices listed as Nch/Pch.
7. VGS = 3.6 V
8. t ≤ 5 sec
Devices listed in bold, italic are ON Semiconductor preferred devices.
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Power MOSFET Selector Guide (continued)
Table 2. SO-8 (MiniMOS) – Case 751–06 (continued)

(Volts) 10 V 4.5 V 2.7 V 2.5 V (cont) Device (Notes 9. & 10.) Configuration Page
Min (Ω) (Ω) (Ω) (Ω) Amps (Note 11.) (Watts) Max (Note 12.) No.
20 0.100 0.200 – – 3.6 MMDF2N02ER2 2.0 Dual N–Channel 451
– 0.035 0.048 0.049 6.5 NTMD6N02R2 2.0 Dual N–Channel 127
0.250 0.400 – – 2.5 MMDF2P02ER2 2.0 Dual P–Channel 477
0.160 0.180 – – 3.3 MMDF2P02HDR2 2.0 Dual P–Channel 485
– 0.033 – 0.050 7.8 NTMD6P02R2 2.0 Dual P–Channel 120
0.100/0.250 0.200/0.400 – – 3.6 MMDF2C02ER2 2.0 Complementary 416
0.090/0.160 0.100/0.180 – – 3.8 MMDF2C02HDR2 2.0 Complementary 427
– 0.024/0.074 – – 7.0 NTMD7C02R2 2.0 Complementary 141
12 – 0.045 0.055 – 5.1 NTMS4P01R2 2.5 Single P–Channel 164
– 0.180 0.220 – 3.4 MMDF2P01HDR2 2.0 Dual P–Channel 468
– 0.045/0.180 – – 5.2 MMDF2C01HDR2 2.0 Complementary 404
Table 3. SO–8 FETKY –– Case 751–06

(Volts) 10 V 4.5 V 2.7 V 2.5 V (cont) Device (Notes 9. & 10.) Page
Min (Ω) (Ω) (Ω) (Ω) Amps (Note 11.) (Watts) Max Configuration No.
30 0.035 0.050 – – 6.0 MMDFS6N303R2 2.0 Dual N–Channel/ 589
Schottky
0.085 0.125 – – 3.05 NTMSD3P303R2 2.0 Dual P–Channel/ 198
Schottky
20 0.160 0.180 – – 3.3 MMDFS2P102R2 2.0 Dual P–Channel/ 579
Schottky
– 0.090 0.130 0.15 2.4 NTMSD2P102LR2 2.0 Dual P–Channel/ 178
Schottky
0.085 0.125 – – 3.0 NTMSD3P102R2 2.0 Dual P–Channel/ 188
Schottky
Table 4. EZFET – SO–8 Power MOSFETs with Zener Gate Protection – Case 751–06
50 0.3 – – – 2.0 MMDF2N05ZR2 2.0 Dual N–Channel 459
30 0.03 0.04 – – 7.5 MMSF7N03ZR2 2.5 Single N–Channel 751
0.013 0.018 – – 10 MMSF10N03ZR2 1.6 Single N–Channel 671
20 – 0.015 0.019 – 10 MMSF10N02ZR2 2.5 Single N–Channel 662
– 0.04 0.05 – 5.0 MMDF5N02ZR2 2.0 Dual N–Channel 551
– 0.027 – 0.035 7.0 MMDF7N02ZR2 2.0 Dual N–Channel 569
9. TC = 25°C
12. Data for all Complementary Devices listed as Nch/Pch.
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Table 5. Micro8 – Case 846A–02

60 0.22 0.26 – – 1.5 MTDF2N06HDR2 1.25 Dual N–Channel 1115
30 0.04 0.06 – – 5.7 MTSF3N03HDR2 1.79 Single N–Channel 1348
0.085 0.135 – – 2.5 NTTS2P03R2 1.79 Single P–Channel 255
0.12 0.16 – – 2.0 MTDF1N03HDR2 1.25 Dual N–Channel 1104
20 – 0.04 0.05 – 6.1 MTSF3N02HDR2 1.79 Single N–Channel 1337
– 0.16 0.19 – 1.8 MTSF1P02HDR2 1.8 Single P–Channel 1326
– 0.09 0.13 – 2.4 NTTS2P02R2R2 0.78 Single P–Channel 248
– 0.12 0.16 – 2.8 MTDF1N02HDR2 1.25 Dual N–Channel 1093
– 0.16 0.25 – 1.45 NTTD1P02R2 1.25 Dual P–Channel 234
– 0.090 0.130 – 2.4 NTTD2P02R2 1.25 Dual P–Channel 241
Table 6. SOT-223 – Case 318E–04

Min (Ω) (Ω) (Ω) (Ω) Amps (Note 16.) (Watts) Max No.
N–Channel
240 6.0 – – 10 0.7 MMFT2406T1/T3 1.5 605
200 14 – – – 0.25 MMFT107T1/T3 0.8 599
60 0.13 – – – 1.7 MMFT3055VT1/T3 2.0 628
– 0.14 – – 1.5 MMFT3055VLT1/T3 2.0 637
1.7 – – – 0.3 MMFT960T1 0.8 656
20 – 0.15 – – 1.6 MMFT2N02ELT1 0.8 619
P–Channel
60 0.3 – – – 1.2 MMFT2955ET1/T3 0.8 610
30 0.1 – – – 5.2 MMFT5P03HDT3 3.13 646
Table 7. TSOP–6 – Case 318G–02

Min (Ω) (Ω) (Ω) (Ω) Amps (Note 17.) (Watts) Max No.
N–Channel
30 0.065 0.095 – – 4.2 MGSF3454VT1 2.0 349
20 – 0.07 – 0.095 4.0 MGSF3442VT1 2.0 344
– 0.045 – 0.055 5.8 NTGS3446T1 1.6 73
P–Channel
30 0.100 0.170 – – 3.5 NTGS3455T1 2.0 76
20 – 0.09 – 0.135 3.3 NTGS3441T1 2.0 61
– 0.065 0.090 0.100 4.4 NTGS3443T1 2.0 67
0.175 0.28 – – 1.3 MGSF2P02HDT1 2.0 336
12 – .075 .095 – 3.3 NTGS3433T1 2.0 57
13. TC = 25°C
16. Available in Tape and Reel only. T1 suffix = 1000 per reel, T3 suffix = 4000 per reel.
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Table 8. TSSOP–8 – Case 318G–02

20 – 0.03 – 0.04 5.8 NTQD6866R2 1.6 Dual N–Channel 230
(Note 23.)
– 0.020 0.027 – 6.2 NTQS6463R2 1.05 Single P–Channel 232
Table 9. SOT–23 – Case 318–08

(Volts) 10 V 4.5 V 2.5 V (cont) Device (Notes 18. & 19.) Page
Min (Ω) (Ω) (Ω) Amps (Note 21.) (Watts) Max No.
N–Channel
100 6.0 – – 0.17 BSS123LT1/T3 0.225 280
60 5.0 – – 0.50 MMBF170LT1/T3 0.225 384
7.5 – – 0.115 2N7002LT1/T3 0.225 267
50 – 3.5 @ 5.0 V 7.0 @ 2.75 0.20 BSS138LT1/T3 0.225 284
30 0.1 0.145 – 0.75 MGSF1N03LT1 0.4 324
20 0.09 0.13 – 0.75 MGSF1N02LT1 0.4 320
1.0 1.4 – 0.3 MMBF0201NLT1 0.225 372
– 0.085 0.115 0.75 MGSF1N02ELT1 0.4 316
P–Channel
50 – 10 @ 5.0 V – 0.13 BSS84LT1 0.225 289
20 – 0.26 0.5 0.75 MGSF1P02ELT1 0.4 328
0.35 0.5 – 0.75 MGSF1P02LT1 0.4 332
1.4 3.5 – 0.3 MMBF0202PLT1 0.225 377
Table 10. SC–70 / SOT–323 – Case 419–02

(Volts) 10 V 4.5 V 2.7 V (cont) Device (Notes 18. & 19.) VGS Page
Min (Ω) (Ω) (Ω) Amps (Note 22.) (Watts) Max (Volts) Min No.
N–Channel
30 – 50 – 0.10 MMBF1374T1 0.10 1.0 382
20 1.0 1.4 – 0.30 MMBF2201NT1 0.15 1.0 388
P–Channel
20 2.2 3.5 – 0.30 MMBF2202PT1 0.15 1.0 392
Table 11. SC–88 / SOT–363 – Case 419B–01

(Volts) 10 V 4.5 V 2.7 V (cont) Device (Notes 18. & 19.) VGS Page
Min (Ω) (Ω) (Ω) Amps (Note 22.) (Watts) Max (Volts) Min No.
N–Channel
20 10 – – 0.1 NTUD01N02 0.15 0.5 262
18. TC = 25°C
21. Available in Tape and Reel only. T1 suffix = 3000 per reel, T3 suffix = 10,000 per reel.
23. VGS = 4.0 V
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12
Table 12. DPAK – Case 369A–13 (TO–252)

N-Channel
200 1.2 – – 4.0 MTD4N20E 40 1048
0.07 – 6.0 MTD6N20E 50 1066
100 0.25 – – 9.0 MTD9N10E 40 1084
60 0.094 – – 12 NTD3055–094 36 35
– 0.104 – 12 NTD3055L104 36 37
0.15 – – 12 MTD3055V 48 1019
– 0.18 – 12 MTD3055VL 48 1028
0.12 – – 15 MTD15N06V 55 942
– 0.085 – 15 MTD15N06VL 60 951
0.045 – – 20 MTD20N06HD 40 970
– 0.045 – 20 MTD20N06HDL 40 980
0.046 – – 20 NTD20N06 60 33
0.026 – – 32 NTD32N06 60 39
– 0.028 – 32 NTD32N06L 60 44
30 – 0.035 – 20 MTD20N03HDL 74 960
0.022 – – 20 MTD1302 74 932
– 0.027 – 20 NTD20N03L27 74 29
0.010 0.013 – 20 NTD4302 62 49
0.010 – – 30 MTD3302 96 1037
P-Channel
100 0.66 – – 6.0 MTD6P10E 50 1075
60 0.45 – – 5.0 MTD5P06V 40 1057
0.20 – – 12 MTD2955V 60 1010
– 0.175 – 15 MTD20P06HDL 72 1000
30 – 0.099 – 19 MTD20P03HDL 75 990
24. TC = 25°C
26. Also available in Tape and Reel. T4 suffix = 2500 per reel.
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13
Table 13. D2PAK – Case 418B–03 (TO–264)

N-Channel
200 0.16 – – 20 MTB20N20E 125 772
150 0.07 – – 29 MTB29N15E 125 790
100 0.04 – – 40 MTB40N10E 169 825
60 0.04 – – 32 MTB36N06V 90 816
– 0.05 – 30 MTB30N06VL 90 798
0.026 – – 45 NTB45N06 120 210
– 0.028 – 45 NTB45N06L 120 215
0.028 – – 42 MTB50N06V 125 834
– 0.032 – 42 MTB50N06VL 125 843
0.022 – – 52 MTB52N06V 165 862
– 0.025 – 52 MTB52N06VL 188 871
0.016 – – 55 MTB55N06Z 136 880
0.014 – – 60 MTB60N06HD 125 895
0.010 – – 75 MTB75N06HD 125 922
50 0.0095 – – 75 MTB75N05HD 125 915
– 0.014 – 60 MTB60N05HDL 150 885
30 0.0065 – – 75 MTB1306 150 765
0.0065 – – 75 NTB75N03–06 150 220
– 0.009 – 75 NTB75N03L09 150 225
25 – 0.009 – 75 MTB75N03HDL 125 905
P-Channel
60 0.12 – – 23 MTB23P06V 90 781
0.08 – – 30 MTB30P06V 125 807
30 – 0.025 – 50 MTB50P03HDL 125 852
27. TC = 25°C
29. Also available in Tape and Reel. T4 suffix = 800 per reel.
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14
Table 14. TO-220AB – Case 221A–09

(Volts) 10 V 5.0 V 2.7 V (cont) (Note NO TAG) Page
Min (Ω) (Ω) (Ω) Amps Device (Watts) Max No.
N-Channel
200 0.70 – – 7.0 MTP7N20E 50 1320
0.16 – – 20 MTP20N20E 125 1175
150 0.07 – – 29 MTP29N15E 125 1199
0.13 – – 20 MTP20N15E 112 1173
100 0.25 – – 10 MTP10N10E 75 1123
0.07 – – 27 MTP27N10E 104 1187
0.04 – – 40 MTP40N10E 169 1243
– 0.22 – 10 MTP10N10EL 40 1130
60 0.150 – – 12 MTP3055V 48 1213
– 0.18 – 12 MTP3055VL 48 1219
0.12 – – 15 MTP15N06V 55 1155
– 0.085 – 15 MTP15N06VL 60 1161
0.085 – – 20 MTP20N06V 60 1167
0.046 – – 27 NTP27N06 74 208
0.04 – – 32 MTP36N06V 90 1237
– 0.05 – 30 MTP30N06VL 90 1225
0.026 – – 45 NTP45N06 120 210
– 0.028 – 45 NTP45N06L 120 215
0.028 – – 42 MTP50N06V 125 1249
– 0.032 – 42 MTP50N06VL 125 1255
0.022 – – 52 MTP52N06V 165 1268
– 0.025 – 52 MTP52N06VL 165 1274
0.014 – – 60 MTP60N06HD 150 1286
0.01 – – 75 MTP75N06HD 150 1313
50 0.0095 – – 75 MTP75N05HD 150 1306
30 0.022 0.029 – 42 MTP1302 74 1141
0.0065 0.0085 – 75 MTP1306 150 1148
0.0065 – – 75 NTP75N03–06 150 220
– 0.009 – 75 NTP75N03L09 150 225
25 – 0.009 – 75 MTP75N03HDL 150 1299
P-Channel
500 6.0 – – 2.0 MTP2P50E 75 1207
200 1.0 – – 6.0 MTP6P20E 75 1293
100 0.30 – – 12 MTP12P10 75 1136
60 0.45 – – 5.0 MTP5P06V 40 1280
0.20 – – 12 MTP2955V 60 1193
0.12 – – 23 MTP23P06V 90 1181
0.08 – – 30 MTP30P06V 125 1231
30 – 0.025 – 50 MTP50P03HDL 125 1261
30. TC = 25°C
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Table 15. TO-247 (Isolated Mounting Hole) – Case 340K–01

(Volts) 10 V 4.5 V 2.7 V (cont) (Note 31.) Page
N-Channel
250 0.08 – – 32 MTW32N25E 250 1365
200 0.075 – – 32 MTW32N20E 180 1359
150 0.05 – – 35 MTW35N15E 180 1371
100 0.035 – – 45 MTW45N10E 180 1377
Table 16. TO-264 – Case 340G–02

N-Channel
200 0.028 – – 55 MTY55N20E 300 1383
Table 17. SMARTDISCRETES

V(BR)DSS Max RDS(on) @ VGS PD
(Volts) 10 V 5.0 V 2.7 V (Notes 31. & 32.) Page
Min (Ω) (Ω) (Ω) Function Device (Watts) Max No.
TO-220AB
62 (Clamped) – 0.75 – Current Limit, ESD MLP1N06CL 40 360
– 0.40 – Current Limit, ESD MLP2N06CL 40 366
DPAK
62 (Clamped) – 0.75 – Current Limit, ESD MLD1N06CLT4 40 354
(Note 33.)
D2PAK – 5 Lead
40 V – 0.02 – Temp Sense, ESD, NIB6404–5L 115 23
Overvoltage Protect
SO–8
30 V 0.05 – – Current Mirror, NIMD6302R2 20 27
ESD Protect (Note 34.)
31. TC = 25°C
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Table 18. TO-92

N-Channel
240 10 – 10 @ 2.5 V 0.2 VN2410L 0.35 1396
6.0 – 10 @ 2.5 V 0.2 VN2406L 0.35 1394
200 – 8.0 @ 2.8 V 10 @ 2.5 V 0.25 BS108 0.35 275
14 – 28 @ 2.6 V 0.25 BS107 0.35 271
6.0 – – 0.25 BS107A 0.35 271
90 2.0 – – 2.0 MPF990 1.0 761
60 7.5 – – 0.15 VN2222LL 0.4 1391
5.0 – – 0.5 BS170 0.35 277
5.0 6.0 – 0.2 2N7000 0.35 264
1.7 – – 2.0 MPF960 1.0 761
1.2 3.3 @ 5 V – 0.2 VN0300L 0.35 1389
35 1.4 – – 2.0 MPF930 1.0 761
1.4 – – 2.0 MPF930A 1.0 761
Table 19. Ignition IGBTs – Insulated Gate Bipolar Transistors

V(BR)CES Max VCE(on) @ VGE IC IC PD
(Volts) 4.0 V 4.5 V (pulse) (cont) (Notes 35. & 36.) Page
Min IC = 6.0 A IC = 10 A Amps Amps Device (Watts) Max No.
TO-220AB
400 V (Clamped) 1.6 1.9 50 15 MGP15N40CL 150 301
350 V (Clamped) 1.6 1.9 50 15 MGP15N35CL 150 293
1.6 1.8 50 19 MGP19N35CL 166 309
D2PAK
400 V (Clamped) 1.6 1.9 50 15 MGB15N40CLT4 150 301
(Note 37.)
350 V (Clamped) 1.6 1.9 50 15 MGB15N35CLT4 150 293
(Note 37.)
1.6 1.8 50 19 MGB19N35CLT4 166 309
(Note 37.)
DPAK
410 V (Clamped) 1.7 2.1 50 15 NGD15N41CLT4 96 21
(Note 38.)
35. TC = 25°C
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18
CHAPTER 1
MOSFET Data Sheets
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19
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20

N–Channel DPAK
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This Logic Level Insulated Gate Bipolar Transistor (IGBT) features
monolithic circuitry integrating ESD and Over–Voltage clamped
protection for use in inductive coil drivers applications. Primary uses 15 AMPS
include Ignition, Direct Fuel Injection, or wherever high voltage and
410 VOLTS
high current switching is required.
• Ideal for Coil–on–Plug Applications VCE(on) @ 10 A = 2.1 V MAX
• DPAK Package Offers Smaller Footprint and Increased Board Space
• Gate–Emitter ESD Protection C
• Temperature Compensated Gate–Collector Voltage Clamp Limits
Stress Applied to Load
• Integrated ESD Diode Protection RG
G
• New Cell Design Increases Unclamped Inductive Switching (UIS)
Energy Per Area RGE
• Short–Circuit Withstand Capability
• Low Threshold Voltage to Interface Power Loads to Logic or
E
Microprocessor Devices
• Low Saturation Voltage
• High Pulsed Current Capability
MARKING
• Optional Gate Resistor (RG) and Gate–Emitter Resistor (RGE) DIAGRAM
MAXIMUM RATINGS (–55°C ≤ TJ ≤ 175°C unless otherwise noted)

DPAK
Rating Symbol Value Unit CASE 369A TBD
STYLE 2
Collector–Emitter Voltage VCES 440 VDC
Collector–Gate Voltage VCER 440 VDC
Gate–Emitter Voltage VGE 15 VDC TBD = Specific Device Code
Collector Current–Continuous IC 15 ADC
@ TC = 25°C
ORDERING INFORMATION
Operating and Storage Temperature TJ, Tstg –55 to °C
Range 175 Device Package Shipping
NGD15N41CL DPAK 75 Units/Rail
NGD15N41CLT4 DPAK 2500/Tape & Reel
This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2001 21 Publication Order Number:

March, 2001 – Rev. 2 NGD15N41CL/D
NGD15N41CL
UNCLAMPED COLLECTOR–TO–EMITTER AVALANCHE CHARACTERISTICS (–55°C ≤ TJ ≤ 175°C)

Characteristic Symbol Value Unit
Single Pulse Collector–to–Emitter Avalanche Energy EAS mJ
VCC = 50 V, VGE = 5 V, Pk IL = 16 A, L = 1.8 mH, Starting TJ = 25°C 225
VCC = 50 V, VGE = 5 V, Pk IL = 15 A, L = 1.8 mH, Starting TJ = 150°C 200
THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Ambient DPAK RθJA 100 °C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

Characteristic Symbol Test Conditions Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Clamp Voltage BVCES IC = 2 mA 380 410 440 VDC
TJ = –40°C to 175°C
Zero Gate Voltage Collector Current ICES VCE = 300 V, – – 40 µADC

VGE = 0, TJ = 25°C
VCE = 300 V, – – 200
VGE = 0, TJ = 150°C
Reverse Collector–Emitter Leakage Current IECS VCE = –24 V – – 1.0 mA
Gate–Emitter Clamp Voltage BVGES IG = 5 mA 10 – 16 VDC
Gate Resistor (Optional) RG – – 70 – Ω
Gate Emitter Resistor (Optional) RGE – 10 – 26 kΩ
ON CHARACTERISTICS*
Gate Threshold Voltage VGE(th) IC = 1 mA 1.0 1.4 2.1 VDC
VGE = VCE
Threshold Temperature Coefficient (Negative) – – – 4.4 – mV/°C
Collector–to–Emitter On–Voltage VCE(on) IC = 6 A, VGE = 4 V – – 1.8 VDC
Collector–to–Emitter On–Voltage VCE(on) IC = 10 A, – – 2.1 VDC
VGE = 4.5 V,
TJ = 150°C
DYNAMIC CHARACTERISTICS
Input Capacitance CISS VCC = 15 V – 700 – pF
Output Capacitance COSS VGE = 0 V – 60 –
Transfer Capacitance CRSS f = 1 MHz – 6.0 –
SWITCHING CHARACTERISTICS*
Turn–Off Delay Time td(off) VCC = 300 V, – 4.0 – µSec
IC = 10 A
Fall Time tf RG = 1 kΩ, – 10 –
L = 300 µH
Turn–On Delay Time td(on) VCC = 10 V, – 1.0 – µSec
IC = 6.5 A
Rise Time tr RG = 1 kΩ, – 4.0 –
RL = 1 Ω
*Pulse Test: Pulse Width v 300 µS, Duty Cycle v 2%.
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Preferred Device

t

Self Protected with Temperature Sense
N–Channel D2PAK http://onsemi.com
SMARTDISCRETES devices are an advanced series of Power 52 AMPERES

MOSFETs which utilize ON Semiconductor’s latest MOSFET
technology process to achieve the lowest possible on–resistance per 40 VOLTS
silicon area while incorporating additional features such as clamp RDS(on) = 20 mΩ
diodes. They are capable of withstanding high energy in the avalanche
and commutation modes. The avalanche energy is specified to

eliminate guesswork in designs where inductive loads are switched
T2
and offer additional safety margin against unexpected voltage
transients.
This new SMARTDISCRETES device features integrated

Gate–to–Source diodes for ESD protection, and Gate–to–Drain clamp
for overvoltage protection. Also, this device integrates a sense diode T1
for temperature monitoring.
• Ultra Low RDS(on) Provides Higher Efficiency
• IDSS Specified at Elevated Temperature
MARKING
• Avalanche Energy Specified DIAGRAM
• Overvoltage Protection
• Temperature Sense Diode
• ESD Human Body Model Discharge Sensitivity Class 3
TBD
D2PAK
CASE 936D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) PLASTIC
Rating Symbol Value Unit
TBD = Specific Device Code
Drain–to–Source Voltage VDSS 40 Vdc
Drain–to–Gate Voltage VDGR 40 Vdc
Gate–to–Source Voltage VGS "10 Vdc
Operating and Storage TJ, Tstg –55 to °C ORDERING INFORMATION
Temperature Range +175
Device Package Shipping
Single Pulse Drain–to–Source Avalanche EAS 450 mJ
Energy – Starting TJ = 25°C (Note 1.)
(VDD = 25 Vdc, VGS = 5.0 Vdc, NIB6404–5L D2PAK TBD
IL(pk) = 25 A, L = 1.4 mH, RG = 10 kΩ)
Drain Current Adc Preferred devices are recommended choices for future use
– Continuous @ TA = 25°C ID 52 and best overall value.
– Continuous @ TA = 140°C ID 25
– Single Pulse (tpv10 µs) IDM 200
Total Power Dissipation (t ≤ 10 seconds) PD @ TA 115 W
Linear Derating Factor = 25°C 0.76 W/°C
Thermal Resistance °C/W
– Junction–to–Case RθJC 1.3
– Junction–to–Ambient (Note 1.) RθJA 80
1. Measured while surface mounted to an FR4 board using the minimum
recommended pad size. Typical value is 64°C/W.

February, 2001 – Rev. 1 NIB6404–5L/D
NIB6404–5L
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 2.) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc, –55°C < TJ < 175°C) 40 51 55
Temperature Coefficient (Negative) – 7.0 – mV/°C
Gate–to–Source Clamp Voltage (Note 2.) V(BR)GSS 10 13 20 Vdc
(VGS = 0 Vdc, IG = 20 µAdc)
Zero Gate Voltage Drain Current IDSS µAdc

(VDS = 35 Vdc, VGS = 0 Vdc) – 1.1 100
(VDS = 15 Vdc, VGS = 0 Vdc) – 0.2 2.0
(VDS = 35 Vdc, VGS = 0 Vdc, TJ = 125°C) – 4.0 20
Gate–Body Leakage Current (VGS = 5.0 Vdc, VDS = 0 Vdc) IGSS – 0.02 1.0 µAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage (Note 2.) VGS(th) Vdc
(VDS = VGS, ID = 1.0 mAdc) 1.0 1.7 2.0
Threshold Temperature Coefficient (Negative) – 4.5 – mV/°C
Static Drain–to–Source On–Resistance (Note 2.) RDS(on) – 18 20 mΩ
(VGS = 5.0 Vdc, ID = 20 Adc)
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 2.) gFS TBD 34 – mhos
Input Capacitance Ciss – 1720 – pF
Output Capacitance (VDS = 25 Vd
Vdc, VGS = 0 Vd
Vdc,
Coss – 525 –
f = 1.0 MHz)
Transfer Capacitance Crss – 120 –
SWITCHING CHARACTERISTICS (Note 3.)
Turn–On Delay Time td(on) – 16 – ns
Rise Time (VDD = 32 Vdc, ID = 25 Adc, tr – 263 –
VGS = 55.0
0 Vdc
Vdc,
Turn–Off Delay Time RG = 10 Ω) (Note 2.) td(off) – 149 –
Fall Time tf – 345 –
Gate Charge QT – 29 – nC
(VDS = 32 Vdc, ID = 25 Adc, Q1 – 6.0 –

VGS = 5.0 Vdc) (Note 2.) Q2 – 16 –
Q3 – 2.0 –
SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 2.) VSD – 0.876 1.2 Vdc
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.746 –
Reverse Recovery Time trr – 60 – ns
(IS = 25 Adc, VGS = 0 Vdc, ta – 29 –

dIS/dt = 100 A/µs) (Note 2.) tb – 32 –
Reverse Recovery Stored Charge QRR – 80 – pC
TEMPERATURE SENSE DIODE CHARACTERISTICS

Forward (Reverse) On–Voltage (IF(R) = 250 µAdc) (Note 2.) VAC(ACR) 715 743 775 mVdc
(IF(R) = 250 µAdc, TJ = 125°C) – 570 –
Temperature Coefficient IF(R) = 250 µAdc, VFTC 1.57 1.71 1.85 mV/°C
(Negative) TJ = 160°C
Forward Voltage Hysteresis IF(R) = 125 µAdc to 250 µAdc Vhys 25 37 50 mVdc
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
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NIB6404–5L
TYPICAL ELECTRICAL CHARACTERISTICS
50 40
5.0 V 4.0 V
45
I D, DRAIN CURRENT (AMPS)

4.5 V 35
3.5 V
40
30
35
30 TJ = 25°C 25
25 20
TJ = 175°C
20 3.0 V 15
15 25°C
10
10 –55°C
5.0 VGS = 2.5 V 5.0
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN–TO–SOURCE RESISTANCE (mW)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (mW)

50 50
45 45
40 TJ = 175°C 40
VGS = 3.0 V 3.5 V
35 35
30 30
25 25 4.0 V
25°C
20 20 5.0 V
15 15
10 V
10 10
–55°C
5.0 5.0 TJ = 25°C
0 0
0 10 20 30 40 50 0 10 20 30 40 50
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage
RDS(on), DRAIN–TO–SOURCE RESISTANCE
2.2 4500
VGS = 5.0 V VGS = 0 V
2.0 4000 TJ = 25°C
ID = 20 A f = 1.0 MHz
3500
C, CAPACITANCE (pF)
1.8
3000
(NORMALIZED)
1.6
2500
1.4
2000 Ciss
1.2
1500
1.0 1000
Coss
0.8 500
Crss
0.6 0
–50 0 50 100 150 200 0 5.0 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with Figure 6. Capacitance Variation

Temperature
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25
NIB6404–5L
5000 20
Ciss
4500 18
IS, SOURCE CURRENT (A)

4000 16
C, CAPACITANCE (pF)
3500 14
3000 Coss 12
2500 10
2000 8.0
1500 6.0
TJ = 175°C
1000 TJ = 25°C 4.0
VDS = 0 V 25°C
500 f = 1 MHz 2.0
0 0
0 2.0 4.0 6.0 8.0 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Diode Forward Voltage

versus Current
VFTC, TEMPERATURE COEFFICIENT (mV/°C)

1.0 –1.3
0.9 –1.4
VF, FORWARD VOLTAGE (V)
IF(R) = 500 mA
0.8 –1.5
250 mA –1.6
0.7 IF(R) = 250 mA
125 mA –1.7
0.6
–1.8
0.5
–1.9
50 mA
0.4 –2.0
25 mA
0.3 –2.1
–100 –50 0 50 100 150 200 –50 0 50 100 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Sense Diode Forward Voltage Figure 10. Sense Diode Temperature
Variation with Temperature Coefficient Variation with Temperature
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26
!

t
!
Self Protected with Current Sense
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N–Channel SO–8, Dual
SMARTDISCRETES devices are an advanced series of Power 5.0 AMPERES
MOSFETs which utilize ON Semiconductor’s latest MOSFET
technology process to achieve the lowest possible on–resistance per 30 VOLTS
silicon area while incorporating smart features. They are capable of RDS(on) = 50 mΩ
withstanding high energy in the avalanche and commutation modes.
The avalanche energy is specified to eliminate guesswork in designs Drain
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
This new SMARTDISCRETES device features an integrated Gate
Gate–to–Source clamp for ESD protection. Also, this device features a Sense Main FET
sense FET for current monitoring.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• IDSS Specified at Elevated Temperature Source Source
• Avalanche Energy Specified Sense Main
• Current Sense FET
• ESD Protected, Main FET and SENSEFET
ABSOLUTE MAXIMUM RATINGS
SOIC–8
Stresses beyond those listed may cause permanent damage to the device. CASE 751
These are stress ratings only and functional operation of the device at these STYLE 19
or any other conditions beyond those indicated in this specification is not
implied. Exposure to absolute maximum rated conditions for extended peri-
ods may affect device reliability.
MARKING DIAGRAM
MAIN MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 8
Source 1 Mirror 1
Rating Symbol Value Unit 2 7
Gate 1 Drain 1
Drain–to–Source Voltage VDSS 30 Vdc 3 TBD 6
Source 2 Mirror 2
Drain–to–Gate Voltage VDGR 30 Vdc 4 5
(RGS = 1.0 MW) Gate 2 Drain 2
Gate–to–Source Voltage VGS "16 Vdc (Top View)
Single Pulse Drain–to–Source EAS 250 mJ
Avalanche Energy (Note 1.) TBD = Specific Device Code
(VDD = 25 Vdc, VGS = 10 Vdc,
VDS = 20 Vdc, IL = 15 Apk,
L = 10 mH, RG = 25 Ω)
Drain Current ORDERING INFORMATION
– Continuous @ TA = 25°C ID 6.5 Adc
– Continuous @ TA = 100°C (Note 1.) ID 4.4 Adc Device Package Shipping
– Single Pulse (tpv10 µs) IDM 33 Apk
NIMD6302R2 SOIC–8 TBD
Maximum Power Dissipation (TA = 25°C) PD TBD W
1. Switching characteristics are independent of operating junction temperatures

February, 2001 – Rev. 1 NIMD6302R2/D
NIMD6302R2
MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 30 35 – Vdc
Temperature Coefficient (Positive) – 30 – mV/°C
(VDS = 30 Vdc, VGS = 0 Vdc) – – 10
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) – – 100
Gate–Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS – 22 32 µAdc
ON CHARACTERISTICS
Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) VGS(th) 1.0 – 2.0 Vdc
Static Drain–to–Source On–Resistance (Note 2.) RDS(on) mΩ

(VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25°C) – – 50
(VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 125°C) – – TBD
Forward Transconductance (Note 2.) gFS mhos
(VDS = 6.0 Vdc, ID = 15 Adc) – 7.4 –
(VDS = 15 Vdc, ID = 15 Adc) – 5.5 –
DYNAMIC CHARACTERISTICS (Note 3.)

Input Capacitance Ciss – 380 600 pF
Output Capacitance (VDS = 6.0
6 0 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 272 350
f = 1.0 MHz)
Transfer Capacitance Crss – 93 200

Turn–On Delay Time td(on) – 8.4 – ns
Rise Time (VDD = 6.0 Vdc, ID = 3.0 Adc, tr – 24 –
Turn–Off Delay Time VGS = 10 Vdc, RG = 4.7 Ω) td(off) – 18 –
Fall Time tf – 5.0 –
Gate Charge QT – 11.3 – nC
(VDS = 6.0 Vdc, ID = 3.0 Adc, Q1 – 2.8 –

VGS = 10 Vdc) Q2 – 1.9 –
Q3 – 2.2 –
Forward On–Voltage (Note 2.) (IS = 3.0 Adc, VGS = 0 Vdc) VSD
S – 0.76 – Vdc
Forward On–Voltage (Notes 2., 3.) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.62 –
Reverse Recovery Time (Note 3.) trr – 24.7 – ns
ta – 13 –
(IS = 3.0
3 0 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 12 –
Reverse Recovery Stored Charge QRR – 0.018 – mC
(Note 3.)
MIRROR MOSFET CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Main/Mirror MOSFET (VDS = 6.0 Vdc, IDmain = 25 mA) IRAT 192 200 208 –
Current Ratio (VDS = 6.0 Vdc, IDmain = 25 mA, 192 200 208
TA = 125°C)
Main/Mirror Current Ratio IDRAT –7.5 ±3.0 +7.5 %
(VDS = 6.0 Vdc, IDmain = 25 mA,
Variation versus Current
TA = 25 to 125°C)
and Temperature
Gate–Body Leakage Current VDS = 0 Vdc, VGS = 3.0 Vdc IGSS – – 100 nAdc
2. Pulse Test: Pulse Width = 300 µs, Duty Cycle = 2%.
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28
! "
#$%& '(
!
N–Channel DPAK
This logic level vertical power MOSFET is a general purpose part
that provides the “best of design” available today in a low cost power
package. Avalanche energy issues make this part an ideal design in. http://onsemi.com
The drain–to–source diode has a ideal fast but soft recovery.
Features 20 AMPERES
• Ultra–Low RDS(on), single base, advanced technology 30 VOLTS
• SPICE parameters available
RDS(on) = 27 mΩ
• Diode is characterized for use in bridge circuits
• IDSS and VDS(on) specified at elevated temperatures
N–Channel
• High Avalanche Energy Specified
• ESD JEDAC rated HBM Class 1, MM Class A, CDM Class 0
D
Typical Applications
• Power Supplies
• Inductive Loads G
• PWM Motor Controls
• Replaces MTD20N03L in many applications S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) MARKING

DIAGRAM
4
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc CASE 369A YWW
Gate–to–Source Voltage Vdc DPAK 20N3L
1 2 STYLE 2
– Continuous VGS "20 3
– Non–Repetitive (tpv10 ms) VGS "24
Drain Current 20N3L = Device Code
– Continuous @ TA = 25_C ID 20 Adc Y = Year
– Continuous @ TA = 100_C ID 16 WW = Work Week
Total Power Dissipation @ TA = 25_C PD 74 Watts PIN ASSIGNMENT
Derate above 25°C 0.6 W/°C 4
Total Power Dissipation @ TC = 25°C 1.75 W Drain
(Note 1.)
Range 150
Energy – Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5 Vdc, L =
1.0 mH, IL(pk) = 24 A, VDS = 34 Vdc) 1 2 3
Gate Drain Source
– Junction–to–Ambient ORDERING INFORMATION
RθJA 100
– Junction–to–Ambient (Note 1.) RθJA 71.4 Device Package Shipping
Maximum Lead Temperature for Soldering TL 260 °C
Purposes, 1/8″ from case for 10 seconds NTD20N03L27 DPAK 75 Units/Rail
1. When surface mounted to an FR4 board using the minimum recommended
NTD20N03L27–1 DPAK 75 Units/Rail
pad size and repetitive rating; pulse width limited by maximum junction
temperature. NTD20N03L27T4 DPAK 2500 Tape & Reel

January, 2001 – Rev. 0 NTD20N03L27/D
NTD20N03L27

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 10
(VDS = 30 Vdc, VGS = 0 Vdc, TJ =150°C) – – 100
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS – – ±100 nAdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.6 2.0
(VGS = 4.0 Vdc, ID = 10 Adc) – 28 31
(VGS = 5.0 Vdc, ID = 10 Adc) – 23 27
Static Drain–to–Source On–Resistance (Note 2.) VDS(on) Vdc
(VGS = 5.0 Vdc, ID = 20 Adc) – 0.48 0.54
(VGS = 5.0 Vdc, ID = 10 Adc, TJ = 150°C) – 0.40 –
Forward Transconductance (Note 2.) (VDS = 5.0 Vdc, ID = 10 Adc) gFS – 21 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 271 420
f = 1.0 MHz)

Turn–On Delay Time td(on) – 17 25 ns
Rise Time (VDD = 20 Vdc, ID = 20 Adc, tr – 137 160
VGS = 55.0
0 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) (Note 2.) td(off) – 38 45
Fall Time tf – 31 40
Gate Charge QT – 13.8 18.9 nC
(VDS = 48 Vd
Vdc, ID = 15 Adc,
Ad
Q1 – 2.8 –
VGS = 10 Vdc) (Note 2.)
Q2 – 6.6 –
Forward On–Voltage VSD Vdc
(IS = 20 Adc, VGS = 0 Vdc) (Note 2.) – 1.0 1.15
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.9 –
ta – 13 –
(IS =15
15 Adc,
Adc VGS = 0 Vdc,
Vdc
dlS/dt = 100 A/µs) (Note 2.) tb – 10 –
Reverse Recovery Stored QRR – 0.017 – µC
Charge
3. Switching characteristics are independent of operating junction temperature.
http://onsemi.com
30
NTD20N03L27
40 40
VGS = 10 V VDS > = 10 V
35 36
–ID, DRAIN CURRENT (AMPS)
VGS = 4 V
ID, DRAIN CURRENT (AMPS)

VGS = 8 V 32
30 VGS = 4.5 V
28
25 VGS = 5 V
24
VGS = 3.5 V TJ = 100°C
20 20
VGS = 6 V
16 TJ = 25°C
15 TJ = –55°C
VGS = 3 V 12
10
TJ = 25°C 8
5 VGS = 2.5 V 4
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
–VDS, DRAIN–TO–SOURCE VOLTAGE (V) –VGS, GATE–TO–SOURCE VOLTAGE (V)

RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)

0.04 0.03
VGS = 5 V TJ = 25°C
0.035 TJ = 100°C
0.03 0.025 VGS = 5 V
TJ = 25°C
0.025
0.02 TJ = –55°C 0.02
0.015 VGS = 10 V
0.01 0.015
0.005
0 0.01
2 5 8 12 15 18 22 25 28 32 35 38 0 4 8 12 16 20 24 28 32 36 40
Figure 3. On–Resistance vs. Drain Current and Figure 4. On–Resistance vs. Drain Current and
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
Temperature Gate Voltage
1.6 1000
ID = 10 A VGS = 0 V
VGS = 5 V
1.4
TJ = 125°C
–IDSS, LEAKAGE (nA)
100
1.2
TJ = 100°C
1
10
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 0 3 6 9 12 15 18 21 24 27 30
TJ, JUNCTION TEMPERATURE (°C) –VDS, DRAIN–TO–SOURCE VOLTAGE (V)
Figure 5. On–Resistance Variation with Figure 6. Drain–to–Source Leakage Current

Temperature vs. Voltage
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31
NTD20N03L27
2500 12
VGS, GATE–TO–SOURCE VOLTAGE (V)

VGS – VDS
Q
10
200
C, CAPACITANCE (pF)
8
1500 VGS
Ciss 6
1000
Q1 Q2
4
500 Coss
Crss 2 ID = 20 A
TJ = 25°C
0 0
10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 23 25 0 2 4 6 8 10 12 14
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate–to–Source and

Drain–to–Source Voltage vs. Total Charge
1000 20
VGS = 0 V
18
IS, SOURCE CURRENT (AMPS)
TJ = 25°C
16
tr 14
100
t, TIME (ns)
tf 12
td(off) 10
8
10 td(on) 6
VDS = 20 V
ID = 20 A 4
VGS = 5.0 V 2
TJ = 25°C
1 0
1 10 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
RG, GATE RESISTANCE (Ω) VSD, SOURCE–TO–DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current
vs. Gate Resistance
EAS, SINGLE PULSE DRAIN–TO–SOURCE
350
ID = 24 A
300
AVALANCHE ENERGY (mJ)
250
200
150
100
50
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Avalanche Energy vs.

Starting Junction Temperature
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32

#$%& '(

N–Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
http://onsemi.com
circuits.
Features 20 AMPERES
• Lower RDS(on) 60 VOLTS
• Lower VDS(on) RDS(on) = 46 mΩ
• Lower Capacitances
• Lower Total Gate Charge N–Channel
• Lower and Tighter VSD D
• Lower Diode Reverse Recovery Time

• Lower Reverse Recovery Stored Charge
G
• Power Supplies
• Converters 4
•
S
Power Motor Controls
• Bridge Circuits
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 2 1

3 2
Rating Symbol Value Unit 3
CASE 369A CASE 369
DPAK DPAK
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc (Bent Lead) (Straight Lead)
Gate–to–Source Voltage Vdc STYLE 2 STYLE 2
– Continuous VGS "20
– Non–repetitive (tpv10 ms) VGS "30 NTD20N06 = Device Code
Y = Year
Drain Current Adc
WW = Work Week
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Total Power Dissipation @ TA = 25°C PD 60 W
4
Derate above 25°C 0.40 W/°C
Drain
Total Power Dissipation @ TA = 25°C (Note 1.) 1.88 W
Total Power Dissipation @ TA = 25°C (Note 2.) 1.36 W 4
Drain YWW
Operating and Storage Temperature Range TJ, Tstg –55 to °C
NTD
175
YWW 20N06
NTD
Energy – Starting TJ = 25°C 20N06
L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc)
1 2 3
1 3
Thermal Resistance °C/W Gate Drain Source
Gate Source
2
Drain
Purposes, 1/8″ from case for 10 seconds
1. When surface mounted to an FR4 board using 1″ pad size,
NTD20N06 DPAK 75 Units/Rail
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended DPAK
NTD20N06–1 75 Units/Rail
pad size, (Cu Area 0.412 in2). Straight Lead
This document contains information on a new product. Specifications and information
herein are subject to change without notice. NTD20N06T4 DPAK 2500 Tape & Reel

March, 2001 – Rev. 3 NTD20N06/D
NTD20N06

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 71.7 –
Temperature Coefficient (Positive) – 79.4 – mV/°C
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 2.0 2.91 4.0
(VGS = 10 Vdc, ID = 10 Adc) – 37.5 46
Static Drain–to–Source On–Voltage (Note 3.) VDS(on) Vdc

(VGS = 10 Vdc, ID = 20 Adc) – 0.78 1.10
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) – 1.57 –
Forward Transconductance (Note 3.) (VDS = 7.0 Vdc, ID = 6.0 Adc) gFS – 13.2 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 213 300
f = 1.0 MHz)

Turn–On Delay Time td(on) – 9.5 20 ns
Rise Time (VDD = 30 Vdc, ID = 20 Adc, tr – 60.5 120
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) (Note 3.) td(off) – 27.1 60
Fall Time tf – 37.1 80
Gate Charge QT – 21.2 30 nC
(VDS = 48 Vd
Vdc, ID = 20 Adc,
Ad
Q1 – 5.6 –
Q2 – 7.3 –
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.87 –
Reverse Recovery Time trr – 42.9 – ns
(IS = 20 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 33 –
dIS/dt = 100 A/µs) (Note 3.)
tb – 9.9 –
Reverse Recovery Stored Charge QRR – 0.084 – µC
http://onsemi.com
34
!)

#$%& '(

N–Channel DPAK
Designed for low voltage, high speed switching applications in http://onsemi.com
circuits. 12 AMPERES
Features 60 VOLTS
• Lower RDS(on) RDS(on) = 94 mΩ
• Lower VDS(on)
• Lower and Tighter VSD N–Channel
• Lower Diode Reverse Recovery Time D

• Power Supplies G
• Converters
• Power Motor Controls S 4
• Bridge Circuits 4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

1 2 1
3
Drain–to–Source Voltage VDSS 60 Vdc CASE 369A CASE 369
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc DPAK DPAK
(Bent Lead) (Straight Lead)
Gate–to–Source Voltage Vdc
STYLE 2 STYLE 2
– Non–Repetitive (tpv10 ms) VGS "30 NTD3055–094 = Device Code
Drain Current Y = Year
– Continuous @ TA = 25°C ID 12 Adc WW = Work Week
– Single Pulse (tpv10 µs) IDM 45 Apk MARKING DIAGRAMS
Total Power Dissipation @ TA = 25°C PD 48 W & PIN ASSIGNMENTS
Total Power Dissipation @ TA = 25°C (Note 1.) 2.1 W Drain
Operating and Storage Temperature Range TJ, Tstg –55 to °C Drain YWW
+175 NTD
YWW 3055–094
Energy – Starting TJ = 25°C NTD
(VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH 3055–094
IL(pk) = 11 A, VDS = 60 Vdc)
1 2 3
Thermal Resistance 1 3
Gate Drain Source
– Junction–to–Case RθJC 3.13 °C/W Gate Source
– Junction–to–Ambient (Note 1.) RθJA 71.4 2
– Junction–to–Ambient (Note 2.) RθJA 100 Drain
Maximum Lead Temperature for Soldering TL 260 °C ORDERING INFORMATION

(Cu Area 1.127 in2). NTD3055–094 DPAK 75 Units/Rail
pad size, (Cu Area 0.412 in2). NTD3055–094–1
Straight Lead
75 Units/Rail
herein are subject to change without notice.
NTD3055–094T4 DPAK 2500 Tape & Reel

March, 2001 – Rev. 1 NTD3055–094/D
NTD3055–094

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 68 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 2.0 2.9 4.0
Static Drain–to–Source On–Resistance (Note 3.) RDS(on) mOhm
(VGS = 10 Vdc, ID = 6.0 Adc) – 84 94

(VGS = 10 Vdc, ID = 12 Adc) – 0.85 1.35
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C) – 0.77 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 107 150
f = 1.0 MHz)

Turn–Off Delay Time VGS = 10 Vdc, RG = 9.1 Ω) (Note 3.) td(off) – 25.2 50
(VDS = 48 Vd
Vdc, ID = 12 Adc,
Ad
Q1 – 3.1 –
Q2 – 4.2 –
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.82 –
(IS = 12 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 24 –
tb – 8.9 –
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#$%& '(

* %+%
N–Channel DPAK
Features 60 VOLTS
• Lower RDS(on) RDS(on) = 104 mΩ
• Lower VDS(on)
• Tighter VSD Specification N–Channel

• Power Supplies G
• Converters
• Power Motor Controls S 4
• Bridge Circuits 4

1 2 1
3
Drain–to–Source Voltage VDSS 60 Vdc CASE 369A CASE 369
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc DPAK DPAK
(Bent Lead) (Straight Lead)
STYLE 2 STYLE 2
– Non–Repetitive (tpv10 ms) VGS "20 NTD3055L104 = Device Code
Drain Current Y = Year
– Continuous @ TA = 25°C ID 12 Adc WW = Work Week
– Single Pulse (tpv10 µs) IDM 45 Apk MARKING DIAGRAMS
Total Power Dissipation @ TA = 25°C PD 48 W & PIN ASSIGNMENTS
Total Power Dissipation @ TA = 25°C (Note 1.) 2.1 W Drain
Operating and Storage Temperature Range TJ, Tstg –55 to °C Drain YWW
+175 NTD
YWW 3055L104
Energy – Starting TJ = 25°C NTD
(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH 3055L104
IL(pk) = 11 A, VDS = 60 Vdc)
1 2 3
Thermal Resistance 1 3
Gate Drain Source
– Junction–to–Case RθJC 3.13 °C/W Gate Source
– Junction–to–Ambient (Note 1.) RθJA 71.4 2
– Junction–to–Ambient (Note 2.) RθJA 100 Drain
Maximum Lead Temperature for Soldering TL 260 °C ORDERING INFORMATION

(Cu Area 1.127 in2). NTD3055L104 DPAK 75 Units/Rail
pad size, (Cu Area 0.412 in2). NTD3055L104–1
Straight Lead
75 Units/Rail
NTD3055L104T4 DPAK 2500 Tape & Reel

March, 2001 – Rev. 1 NTD3055L104/D
NTD3055L104

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 70 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.6 2.0
(VGS = 5.0 Vdc, ID = 6.0 Adc) – 89 104

(VGS = 5.0 Vdc, ID = 12 Adc) – 0.98 1.50
(VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150°C) – 0.86 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 105 150
f = 1.0 MHz)

Turn–Off Delay Time VGS = 5.0 Vdc, RG = 9.1 Ω) (Note 3.) td(off) – 19 40
(VDS = 48 Vd
Vdc, ID = 12 Adc,
Ad
Q1 – 2.0 –
VGS = 5.0 Vdc) (Note 3.)
Q2 – 4.0 –
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.82 –
(IS = 12 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 21 –
tb – 14 –
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38
!
#$%& '(
!
N–Channel DPAK
circuits. http://onsemi.com
Features 32 AMPERES
• Smaller Package than MTB36N06V
60 VOLTS
• Lower RDS(on)
• Lower and Tighter VSD D
Typical Applications G
• Power Supplies
•
4
Converters
S
• Power Motor Controls 4
• Bridge Circuits
1 2 1
3 2 3
CASE 369A CASE 369
Rating Symbol Value Unit DPAK DPAK
Drain–to–Source Voltage VDSS 60 Vdc (Bent Lead) (Straight Lead)
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc STYLE 2 STYLE 2
Gate–to–Source Voltage Vdc NTD32N06 = Device Code
– Continuous VGS "20 Y = Year
– Non–Repetitive (tpv10 ms) VGS "30 WW = Work Week
Drain Current T = MOSFET
– Continuous @ TA = 25°C ID 32 Adc
MARKING DIAGRAMS
– Single Pulse (tpv10 µs) IDM 90 Apk & PIN ASSIGNMENTS
Total Power Dissipation @ TA = 25°C PD 93.75 W 4
Derate above 25°C 0.625 W/°C Drain
Total Power Dissipation @ TA = 25°C (Note 2.) 1.5 W Drain YWW
Operating and Storage Temperature Range TJ, Tstg –55 to °C NTD
+175 YWW 32N06
NTD
32N06
(VDD = 50 Vdc, VGS = 10 Vdc, L = 1.0 mH,
IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 Ω) 1 2 3
1 3
Gate Drain Source
Gate Source
2
Drain
– Junction–to–Ambient (Note 2.) RθJA 100 ORDERING INFORMATION
NTD32N06 DPAK 75 Units/Rail
(Cu Area 1.127 in2). DPAK
NTD32N06–1 75 Units/Rail
2. When surface mounted to an FR4 board using minimum recommended pad Straight Lead
size, (Cu Area 0.412 in2).
NTD32N06T4 DPAK 2500 Tape & Reel
3. Repetitive rating; pulse width limited by maximum junction temperature.

March, 2001 – Rev. 1 NTD32N06/D
NTD32N06

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 70 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0
(VGS = 10 Vdc, ID = 16 Adc) – 21 26

(VGS = 10 Vdc, ID = 20 Adc) – 0.417 0.62
(VGS = 10 Vdc, ID = 32 Adc) – 0.680 –
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150°C) – 0.633 –
Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) gFS – 21.1 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 346 485
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Gate Charge QT – 33 60 nC
(VDS = 48 Vd
Vdc, ID = 32 Adc,
Ad
Q1 – 6.0 –
Q2 – 15 –

(IS = 32 Adc, VGS = 0 Vdc) (Note 4.) – 0.96 –
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.75 –
(IS = 32 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 37 –
tb – 14.3 –
http://onsemi.com
40
NTD32N06
60 60
VGS = 10 V VDS > = 10 V
VGS = 6 V

50 50
VGS = 6.5 V
40 40
VGS = 7 V VGS = 5.5 V
30 VGS = 8 V 30
VGS = 5 V
20 20 TJ = 25°C
VGS = 4.5 V
10 10 TJ = 100°C
VGS = 4 V TJ = –55°C
0 0
0 1 2 3 4 3 3.4 3.8 4.2 4.6 5 5.4 5.8 6.2 6.6 7


0.038 0.024
VGS = 10 V
0.034
TJ = 100°C 0.023
0.03
0.022
VGS = 10 V
0.026
0.021
TJ = 25°C
0.022
0.02
0.018 VGS = 15 V
TJ = –55°C
0.014 0.019
0.01 0.018
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Figure 3. On–Resistance vs. Gate–to–Source Figure 4. On–Resistance vs. Drain Current and
Voltage Gate Voltage
1.8 10000
ID = 16 A VGS = 0 V
VGS = 10 V
1.6
IDSS, LEAKAGE (nA)
TJ = 150°C
1.4 1000
(NORMALIZED)
1.2 TJ = 125°C
1 100
0.8 TJ = 100°C
0.6 10
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60

http://onsemi.com
41
NTD32N06
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

3200 12
VDS = 0 V VGS = 0 V TJ = 25°C
2800 QT
10 VGS
Ciss
C, CAPACITANCE (pF)
2400
8
2000 Q1
Crss
Q2
1600 Ciss 6
1200
4
800 Coss
2 ID = 32 A
400 Crss TJ = 25°C
0 0
10 5 VGS 0 VDS 5 10 15 20 25 0 4 8 12 16 20 24 28 32 36
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE Qg, TOTAL GATE CHARGE (nC)
(VOLTS)
1000 32
VDS = 30 V VGS = 0 V

ID = 32 A 28 TJ = 25°C
VGS = 10 V
24
t, TIME (ns)
20
100 tr 16
tf 12
td(off) 8
4
td(on)
10 0
1 10 100 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96
RG, GATE RESISTANCE (Ω) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
vs. Gate Resistance
1000 350
VGS = 20 V RDS(on) Limit ID = 32 A
SINGLE PULSE Thermal Limit
300
TC = 25°C Package Limit

100
250
dc 200
10
10 ms 150
1 ms
100 µs 100
1
Mounted on 3″ sq. FR4 board (1″ sq.
2 oz. Cu 0.06″ thick single sided) 50
with one die operating,10 s max
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.
Safe Operating Area Starting Junction Temperature
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42
NTD32N06
10
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
Normalized to RθJC at Steady State
1
(NORMALIZED)
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (s)
Figure 13. Thermal Response
10
Normalized to RθJA at Steady State,
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
1″ square Cu Pad, Cu Area 1.127 in2,

3 x 3 inch FR4 board
1
(NORMALIZED)
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
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43
!
#$%& '(
!
* %+%
N–Channel DPAK
Features
• Smaller Package than MTB30N06VL 32 AMPERES
• Lower Total Gate Charge
• Lower and Tighter VSD N–Channel
• Power Supplies
• Converters
G
• Power Motor Controls

• Bridge Circuits S
MARKING
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) DIAGRAM
Drain–to–Source Voltage VDSS 60 Vdc 4 YWW
CASE 369A
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc NTD
DPAK
Gate–to–Source Voltage Vdc 1 2 32N06L
STYLE 2
– Continuous VGS "15 3
– Non–Repetitive (tpv10 ms) VGS "20
Drain Current NTD32N06L = Device Code
– Continuous @ TA = 25°C ID 32 Adc Y = Year
– Continuous @ TA = 100°C ID 22 WW = Work Week
– Single Pulse (tpv10 µs) IDM 90 Apk T = MOSFET
Total Power Dissipation @ TA = 25°C PD 93.75 W
Derate above 25°C 0.625 W/°C PIN ASSIGNMENT
Drain
+175
(VDD = 50 Vdc, VGS = 5 Vdc, L = 1.0 mH,
IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 Ω) 1 3
2
Gate Source
Thermal Resistance °C/W Drain
– Junction–to–Ambient (Note 1.) RθJA 52 ORDERING INFORMATION
Purposes, 1/8″ from case for 10 seconds NTD32N06L DPAK 75 Units/Rail
NTD32N06L–1 DPAK 75 Units/Rail
2. When surface mounted to an FR4 board using minimum recommended pad NTD32N06LT4 DPAK 2500 Tape & Reel
size, (Cu Area 0.412 in2).

March, 2001 – Rev. 0 NTD32N06L/D
NTD32N06L

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 70 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.7 2.0
(VGS = 5 Vdc, ID = 16 Adc) – 23.7 28

(VGS = 5 Vdc, ID = 20 Adc) – 0.48 0.67
(VGS = 5 Vdc, ID = 32 Adc) – 0.78 –
(VGS = 5 Vdc, ID = 16 Adc, TJ = 150°C) – 0.61 –
Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) gFS – 27 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 343 480
f = 1.0 MHz)
VGS = 5 Vdc,
Vdc
(VDS = 48 Vd
Vdc, ID = 32 Adc,
Ad
Q1 – 4.5 –
Q2 – 14 –

(IS = 32 Adc, VGS = 0 Vdc) (Note 4.) – 0.95 –
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.74 –
(IS = 32 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 31 –
tb – 25 –
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45
NTD32N06L
60 60
VGS = 10 V VDS > = 10 V
VGS = 4.5 V

50 50
VGS = 5 V
40 VGS = 4 V 40
30 VGS = 6 V 30
VGS = 3.5 V
20 20
VGS = 8 V TJ = 25°C
10 VGS = 3 V 10
TJ = 100°C TJ = –55°C
0 0
0 1 2 3 4 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5

0.042 0.042
VGS = 5 V VGS = 10 V
0.038 0.038
0.034 TJ = 100°C 0.034
0.03 0.03
TJ = 25°C
0.026 0.026 TJ = 100°C
0.022 0.022 TJ = 25°C

TJ = –55°C
0.018 0.018
TJ = –55°C
0.014 0.014
0.01 0.01
0 10 20 30 40 50 60 0 10 20 30 40 50 60
1.8 10000
ID = 16 A VGS = 0 V
VGS = 5 V TJ = 150°C
1.6
IDSS, LEAKAGE (nA)
1000
(NORMALIZED)
1.4
TJ = 125°C
1.2
1 100
TJ = 100°C
0.8
0.6 10
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60

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46
NTD32N06L

4000 6
VDS = 0 V VGS = 0 V TJ = 25°C
3600 QT
5
3200 VGS
C, CAPACITANCE (pF)
Ciss
2800 Q1 Q2
4
2400 Crss
2000 3
1600 Ciss
2
1200
800 Coss
1 ID = 32 A
400 Crss TJ = 25°C
0 0
10 5 VGS 0 VDS 5 10 15 20 25 0 4 8 12 16 20 24
(VOLTS)
1000 32

ID = 32 A 28 TJ = 25°C
VGS = 5 V
24
tr
t, TIME (ns)
20
tf
100 16
12
td(off)
8
4
td(on)
10 0
1 10 100 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96
vs. Gate Resistance
1000 350
VGS = 20 V RDS(on) Limit ID = 32 A
SINGLE PULSE Thermal Limit
300
TC = 25°C Package Limit

100
250
dc 200
10 10 ms
1 ms 150
100 µs
100
1
Mounted on 3″ sq. FR4 board (1″ sq. 50
2 oz. Cu 0.06″ thick single sided)
with one die operating,10 s max
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
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47
NTD32N06L
10
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
Normalized to RθJC at Steady State
1
(NORMALIZED)
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (s)
10
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE

1
(NORMALIZED)
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
http://onsemi.com
48
!
#$%& '(
,- !
N–Channel DPAK
Features
• Ultra Low RDS(on) http://onsemi.com
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive 18.5 AMPERES
• Diode Exhibits High Speed, Soft Recovery 30 VOLTS
• Avalanche Energy Specified 10 mΩ @ VGS = 10 V
• IDSS Specified at Elevated Temperature N–Channel
• SO–8 Mounting Information Provided D
Applications
• DC–DC Converters G
• Low Voltage Motor Control
• Power Management in Portable and Battery Powered Products: S
4
4
i.e., Computers, Printers, Cellular and Cordless Telephones, and
PCMCIA Cards
1 2
3 12
CASE 369A 3
DPAK CASE 369
(Bend Lead) DPAK
STYLE 2 (Straight Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
YWW
T
YWW 4302
T
4302
1 2 3
1 3
Gate Drain Source
Gate 2 Source
Drain
4302 = Device Code
Y = Year
WW = Work Week
T = MOSFET
NTD4302 DPAK 75 Units/Rail
DPAK
NTD4302–1 75 Units/Rail
Straight Lead
NTD4302T4 DPAK 2500 Tape & Reel

March, 2001 – Rev. 1 NTD4302/D
NTD4302
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Gate–to–Source Voltage – Continuous VGS ±20 Vdc
Thermal Resistance
– Junction–to–Ambient (Note 1.) RθJA 1.3 °C/W
Total Power Dissipation @ TA = 25°C PD 96 Watts
Continuous Drain Current @ TA = 25°C ID 30 Amps
Pulsed Drain Current (Note 5.) IDM 90 Amps
Thermal Resistance
– Junction–to–Ambient (Note 2.) RθJA 25 °C/W
Total Power Dissipation @ TA = 25°C PD 5.0 Watts
Continuous Drain Current @ TA = 25°C ID 18.5 Amps
Thermal Resistance
Thermal Resistance
Operating and Storage Temperature Range TJ, Tstg –55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C EAS 722 mJ
(VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 17 Apk, L = 5.0 mH, RG = 25 Ω)
1. Mounted on Heat Sink, Steady State.
2. Mounted on 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Time ≤ 10 seconds.
3. Mounted on 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Steady State.
4. Minimum FR–4 or G–10 PCB, Steady State.
http://onsemi.com
50
NTD4302

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µA) 30 – –
Positive Temperature Coefficient – 25 – mV/°C
(VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25°C) – – 1.0
(VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125°C) – – 10
ON CHARACTERISTICS
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.9 3.0
Negative Temperature Coefficient – –3.8 –
Static Drain–Source On–State Resistance RDS(on) Ω
(VGS = 10 Vdc, ID = 18.5 Adc) – 0.0078 0.010
(VGS = 10 Vdc, ID = 10 Adc) – 0.0078 0.010
(VGS = 4.5 Vdc, ID = 5.0 Adc) – 0.010 0.013
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) gFS – 20 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 640 800
f = 1.0
1 0 MHz)
Reverse Transfer Capacitance Crss – 225 310
Rise Time (VDD = 25 Vdc, ID = 1.0 Adc, tr – 15 25
VGS = 10 Vdc,
Vdc
Turn–Off Delay Time RG = 6.0 Ω) td(off) – 85 130
VGS = 10 Vdc,
Vdc
Rise Time (VDD = 24 Vdc, ID = 18.5 Adc, tr – 25 –
VGS = 10 Vdc,
Vdc
Turn–Off Delay Time RG = 2.5 Ω) td(off) – 40 –
Gate Charge
g QT – 55 80 nC
(VDS = 24 Vd
Vdc, ID = 2.0
2 0 Ad
Adc,
Qgs (Q1) – 5.5 –
VGS = 10 Vdc)
Qgd (Q2) – 15 –
BODY–DRAIN DIODE RATINGS (Note 6.)
Diode Forward On–Voltage VSD Vdc
(IS = 2.3 Adc, VGS = 0 Vdc) – 0.75 1.0
(IS = 18.5 Adc, VGS = 0 Vdc) – 0.88 –
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.65 –
Reverse Recovery y Time trr – 39 65 ns
(IS = 2.3
2 3 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
dIS/dt = 100 A/µs)
tb – 19 –
Reverse Recovery Stored Charge Qrr – 0.043 – µC
6. Indicates Pulse Test: Pulse Width = 300 µsec max, Duty Cycle ≤ 2%.
http://onsemi.com
51
NTD4302
50 60
VGS = 4 V TJ = 25°C
VDS > = 10 V

VGS = 3.8 V 50
40
VGS = 4.4 V
VGS = 4.6 V 40
30
VGS = 5 V
30 TJ = 25°C
VGS = 7 V VGS = 3.4 V
20
20 TJ = 100°C
VGS = 10 V VGS = 3.2 V
10 TJ = –55°C
VGS = 2.8 V VGS = 3.0 V 10
0 0
0 0.5 1 1.5 2 2.5 3 2 3 4 5 6
VDS, DRAIN–TO–SOURCE VOLTAGE (V) VGS, GATE–TO–SOURCE VOLTAGE (V)


0.1 0.015
ID = 10 A TJ = 25°C
TJ = 25°C
0.075 VGS = 4.5 V

0.01
0.05
VGS = 10 V
0.005
0.025
0 0
0 2 4 6 8 10 0.00E+00 1.00E+01 2.00E+01 3.00E+01 4.00E+01 5.00E+01 6.00E+01
VGS, GATE–TO–SOURCE VOLTAGE (V) ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance vs. Figure 4. On–Resistance vs. Drain Current

Gate–To–Source Voltage and Gate Voltage
1.6 10000
ID = 18.5 A VGS = 0 V
VGS = 10 V
TJ = 150°C
1.4
1000
IDSS, LEAKAGE (nA)
(NORMALIZED)
1.2
100
TJ = 100°C
1
10
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (V)
Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current vs. Voltage
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52
NTD4302
VDS, DRAIN–TO–SOURCE– VOLTAGE (V)

VGS, GATE–TO–SOURCE– VOLTAGE (V)
60 12.5 30
VDS = 0 V VGS = 0 V TJ = 25°C
50 QT
10 25
C, CAPACITANCE (pF)
Ciss VD
40
7.5 20
30 VGS
Crss Ciss
5 15
20 Q1 Q2
Coss 2.5 10
10 Crss
ID = 2 A
TJ = 25°C
0 0 0
10 VGS 0 VDS 10 20 30 0 10 20 30 40 50 60
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

1000 25
VGS = 0 V
VDD = 24 V
TJ = 25°C
ID = 18.5 A
VGS = 10 V 20
t, TIME (ns)
15
100
tf
10
td(off)
tr
5
td(on)
10 0
1 10 100 0.5 0.6 0.7 0.8 0.9 1
RG, GATE RESISTANCE (Ω) VSD, SOURCE–TO–DRAIN VOLTAGE (V)
vs. Gate Resistance
http://onsemi.com
53
NTD4302

m!

%&'

" !
'((

" #$° ') '+
!
'* #$

Figure 11. Maximum Rated Forward Biased Figure 12. Diode Reverse Recovery Waveform
Safe Operating Area

.

- -
'23)' ..

" $

#

$
#

θ,' " ('
θ,
*0

- .
/
'
/

'
'#
- - " '&'# ,*0 " *0
θ,'

$ 6 4 # 5 5 5# 54
' !1!
Figure 13. Thermal Response – Various Duty Cycles
http://onsemi.com
54
NTD4302
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the interface between the board and the package. With the
total design. The footprint for the semiconductor packages correct pad geometry, the packages will self align when
must be the correct size to ensure proper solder connection subjected to a solder reflow process.
9$ 8
67 4

#$6
94
9
7 #64
68#9 9:#
inches
mm
SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed pattern of the opening in the stencil for the drain pad is not
circuit board, solder paste must be applied to the pads. critical as long as it allows approximately 50% of the pad to
Solder stencils are used to screen the optimum amount. be covered with paste.
These stencils are typically 0.008 inches thick and may be
ÇÇ ÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇ ÇÇ
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
ÇÇ ÇÇ

ÇÇ ÇÇÇÇÇÇ
packages, the stencil opening should be the same as the pad
ÇÇ ÇÇÇÇÇÇ
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
ÇÇ ÇÇÇ

solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
Figure 14. Typical Stencil for DPAK and
should be approximately 50% of the tab area. The opening D2PAK Packages
for the leads is still a 1:1 registration. Figure 14 shows a
typical stencil for the DPAK and D2PAK packages. The
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated • When shifting from preheating to soldering, the
temperature of the device. When the entire device is heated maximum temperature gradient shall be 5°C or less.
to a high temperature, failure to complete soldering within • After soldering has been completed, the device should
a short time could result in device failure. Therefore, the be allowed to cool naturally for at least three minutes.
following items should always be observed in order to Gradual cooling should be used as the use of forced
minimize the thermal stress to which the devices are cooling will increase the temperature gradient and
subjected. result in latent failure due to mechanical stress.
• Always preheat the device. • Mechanical stress or shock should not be applied
• The delta temperature between the preheat and during cooling.
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the * Soldering a device without preheating can cause
leads and the case must not exceed the maximum excessive thermal shock and stress which can result in
temperature ratings as shown on the data sheet. When damage to the device.
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C. * Due to shadowing and the inability to set the wave height
• The soldering temperature and time shall not exceed to incorporate other surface mount components, the D2PAK
260°C for more than 10 seconds. is not recommended for wave soldering.
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55
NTD4302
TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of temperature versus time. The line on the graph shows the
control settings that will give the desired heat pattern. The actual temperature that might be experienced on the surface
operator must set temperatures for several heating zones of a test board at or near a central solder joint. The two
and a figure for belt speed. Taken together, these control profiles are based on a high density and a low density
settings make up a heating “profile” for that particular board. The Vitronics SMD310 convection/infrared reflow
circuit board. On machines controlled by a computer, the soldering system was used to generate this profile. The type
computer remembers these profiles from one operating of solder used was 62/36/2 Tin Lead Silver with a melting
session to the next. Figure 15 shows a typical heating point between 177–189°C. When this type of furnace is
profile for use when soldering a surface mount device to a used for solder reflow work, the circuit boards and solder
printed circuit board. This profile will vary among joints tend to heat first. The components on the board are
soldering systems, but it is a good starting point. Factors then heated by conduction. The circuit board, because it has
that can affect the profile include the type of soldering a large surface area, absorbs the thermal energy more
system in use, density and types of components on the efficiently, then distributes this energy to the components.
board, type of solder used, and the type of board or Because of this effect, the main body of a component may
substrate material being used. This profile shows be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7

PREHEAT VENT HEATING HEATING HEATING VENT COOLING
ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“RAMP” “RAMP” “SOAK” “SPIKE” 205° TO 219°C
PEAK AT
200°C DESIRED CURVE FOR HIGH 170°C SOLDER
MASS ASSEMBLIES JOINT
160°C
150°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
100°C 140°C (DEPENDING ON
MASS OF ASSEMBLY)
100°C
DESIRED CURVE FOR LOW

MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL) TMAX

Figure 15. Typical Solder Heating Profile
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56
!!!

'(
!-!
P–Channel TSOP–6
Features http://onsemi.com
• Ultra Low RDS(on)
• Higher Efficiency Extending Battery Life –3.3 AMPERES
• Miniature TSOP–6 Surface Mount Package
–12 VOLTS
Applications
75 m @ VGS = –4.5 V
• Power Management in Portable and Battery–Powered Products, i.e.:
Cellular and Cordless Telephones, and PCMCIA Cards
P–Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.) 1 2 5 6

DRAIN
Drain–to–Source Voltage VDSS –12 Volts
Gate–to–Source Voltage – Continuous VGS "8.0 Volts
3
Thermal Resistance GATE
Junction–to–Ambient (Note 1.) RθJA 62.5 °C/W
Total Power Dissipation @ TA = 25°C Pd 2.0 Watts
Drain Current –3.3 Amps 4
– Continuous @ TA = 25°C ID SOURCE
– Pulsed Drain Current (Tp t 10 µS) IDM –20 Amps
Maximum Operating Power Dissipation Pd 1.0 Watts
Maximum Operating Drain Current ID –2.35 Amps
MARKING
DIAGRAM
Thermal Resistance
Junction–to–Ambient (Note 2.) RθJA 128 °C/W
3
Total Power Dissipation @ TA = 25°C Pd 1.0 Watts 2
1 TSOP–6 433
Drain Current
– Continuous @ TA = 25°C ID –2.35 Amps CASE 318G x
– Pulsed Drain Current (Tp t 10 µS) IDM –14 Amps 4 STYLE 1
Maximum Operating Power Dissipation Pd 0.5 Watts 5
6
Operating and Storage Temperature Range TJ, Tstg –55 to °C 433 = Device Code
150 x = Date Code
Purposes for 10 Seconds
PIN ASSIGNMENT
1. Mounted onto a 2″ square FR–4 board (1″ sq. 2 oz. cu. 0.06″ thick single
sided), t t 5.0 seconds. Drain Drain ;(1
2. Mounted onto a 2″ square FR–4 board (1″ sq. 2 oz. cu. 0.06″ thick single 6 5 4
sided), operating to steady state.
1 2 3
Drain Drain Gate
NTGS3433T1 TSOP–6 3000 Tape & Reel


December, 2000 – Rev. 0 NTGS3433T1/D
NTGS3433T1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Notes 3. & 4.)
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –10 µA) –12 – –

(VGS = 0 Vdc, VDS = –8 Vdc, TJ = 25°C) – – –1.0
Gate–Body Leakage Current IGSS nAdc
(VGS = –8.0 Vdc, VDS = 0 Vdc) – – –100

(VGS = +8.0 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.50 –0.70 –1.50
Static Drain–Source On–State Resistance RDS(on) W

(VGS = –4.5 Vdc, ID = –3.3 Adc) – 0.055 0.075
(VGS = –2.5 Vdc, ID = –2.9 Adc) – 0.075 0.095
Forward Transconductance gFS mhos
(VDS = –10 Vdc, ID = –3.3 Adc) – 7.0 –
Total Gate Charge Qtot – 7.0 15 nC
(VDS = –10
10 Vdc,
Vd VGS = –4.54 5 Vdc,
Vd
Gate–Source Charge Qgs – 2.0 –
ID = –3.3 Adc)
Gate–Drain Charge Qgd – 3.5 –
(VDS = –5.0
5 0 Vdc,
Vd VGS = 0 Vdc,
Vd
Output Capacitance Coss – 450 –
f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 200 –
SWITCHING CHARACTERISTICS
Rise Time (VDD = –10
10 Vdc, ID = –1.0
1.0 Adc, tr – 20 30
Turn–Off Delay Time VGS = –4.5 Vdc, Rg = 6.0 W) td(off) – 110 120
Reverse Recovery Time (IS = –1.7 Adc, dlS/dt = 100 A/µs) trr – 30 – ns
BODY–DRAIN DIODE RATINGS
Diode Forward On–Voltage (IS = –1.7 Adc, VGS = 0 Vdc) VSD – –0.80 –1.5 Vdc
Diode Forward On–Voltage (IS = –3.3 Adc, VGS = 0 Vdc) VSD – –0.90 – Vdc
3. Indicates Pulse Test: P.W. = 300 µsec max, Duty Cycle = 2%.
4. Class 1 ESD rated – Handling precautions to protect against electrostatic discharge is mandatory.
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58
NTGS3433T1
12 20
VGS = –5 V VGS = –2.5 V VDS ≥ –10 V
18

10 VGS = –3 V 16 TJ = –55°C
VGS = –3.5 V
14 TJ = 25°C
8 VGS = –4 V
VGS = –4.5 V 12
6 10
VGS = –2 V TJ = 125°C
8
4
6
TJ = 25°C
4
2
VGS = –1.5 V 2
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 0.5 1 1.5 2 2.5 3 3.5 4
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

0.4 0.3
ID = –3.3 A TJ = 25°C
0.35
TJ = 25°C 0.25
0.3
0.2
0.25
0.2 0.15 VGS = –2.5 V
0.15
0.1
0.1 VGS = –4.5 V
0.05
0.05
0 0
0 2 4 6 8 0 2 4 6 8 10 12 14 16 18 20
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –ID, DRAIN CURRENT (AMPS)
1.6 1200
ID = –3.3 A VGS = 0 V
VGS = –4.5 V 1000 TJ = 25°C
1.4
C, CAPACITANCE (pF)
800
1.2
600 Ciss
1
400 Coss
0.8 200 Crss
0.6 0
–50 –25 0 25 50 75 100 125 150 0 2.5 5 7.5 10 12.5 15 17.5 20
TJ, JUNCTION TEMPERATURE (°C) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Temperature
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59
NTGS3433T1
6 10
–VGS, GATE–TO–SOURCE VOLTAGE
–IS, SOURCE CURRENT (AMPS)

9 VGS = 0 V
5
QT 8
4 7
6 TJ = 150°C
(VOLTS)
3 5
Qgs
Qgd 4
2
3 TJ = 25°C
TJ = 25°C 2
1
ID = –3.3 A
1
0 0
0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 1.2
Qg, TOTAL GATE CHARGE (nC) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 7. Gate–to–Source and Figure 8. Diode Forward Voltage vs. Current

1
NORMALIZED EFFECTIVE TRANSIENT
Duty Cycle = 0.5

THERMAL IMPEDANCE
0.2
0.1
0.1
0.05
0.02
0.01 Single Pulse

0.1
1E–04 1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
SQUARE WAVE PULSE DURATION (sec)
Figure 9. Normalized Thermal Transient Impedance, Junction–to–Ambient
20
16
POWER (W)
12
0
0.01 0.10 1.00 10.00 100.00
TIME (sec)
Figure 10. Single Pulse Power
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Features
• Higher Efficiency Extending Battery Life http://onsemi.com
1 AMPERE
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: 20 VOLTS
Cellular and Cordless Telephones, and PCMCIA Cards RDS(on) = 90 m
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) P–Channel
# $ 9
Thermal Resistance
Junction–to–Ambient (Note 1.) RθJA 244 °C/W 4
Drain Current – Continuous @ TA = 25°C ID –1.65 Amps
Thermal Resistance 6
Drain Current – Continuous @ TA = 25°C ID –2.35 Amps MARKING
DIAGRAM
Thermal Resistance
Junction–to–Ambient (Note 3.) RθJA 62.5 °C/W 3
1 TSOP–6 441
CASE 318G W
4 STYLE 1
Operating and Storage Temperature Range TJ, Tstg –55 to °C 5
150 6

Purposes for 10 Seconds 441 = Device Code
W = Work Week
1. Minimum FR–4 or G–10PCB, operating to steady state.
sided), operating to steady state. PIN ASSIGNMENT
sided), t t 5.0 seconds. ()% ()% ;(1
6 5 4
1 2 3
()% ()% )'1

November, 2000 – Rev. 1 NTGS3441T1/D
NTGS3441T1
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –10 µA) –20 – –

(VGS = –8.0 Vdc, VDS = 0 Vdc) – – –100

(VGS = +8.0 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.45 –1.05 –1.50

(VGS = –4.5 Vdc, ID = –3.3 Adc) – 0.069 0.090
(VGS = –2.5 Vdc, ID = –2.9 Adc) – 0.117 0.135
(VDS = –10 Vdc, ID = –3.3 Adc) – 6.8 –
(VDS = –5.0
5 0 Vdc,
Vd VGS = 0 Vdc,
Vd
Output Capacitance Coss – 265 – pF
f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 100 – pF
20 Vdc, ID = –1.6
1.6 Adc, tr – 23.5 45 ns
Turn–Off Delay Time VGS = –4.5 Vdc, Rg = 6.0 W) td(off) – 27 50 ns
Fall Time tf – 24 45 ns
(VDS = –10
10 Vdc,
Vd VGS = –4.54 5 Vdc,
Vd
Gate–Source Charge Qgs – 1.3 – nC
ID = –3.3 Adc)
Gate–Drain Charge Qgd – 2.5 – nC

Reverse Recovery Time (IS = –1.6 Adc, dIS/dt = 100 A/µs) trr – 30 60 ns
5. Handling precautions to protect against electrostatic discharge is mandatory.
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62
NTGS3441T1
10 20
TJ = 25°C VGS = –2.7 V VDS> = –10 V

TJ = 25°C
8 16
VGS = –2.5 V
TJ = –55°C
6 VGS = –3 V 12
TJ = 100°C
VGS = –3.5 V
VGS = –4 V
4 VGS = –4.5 V 8
VGS = –6 V VGS = –2 V
2 4
VGS = –10 V VGS = –1.5 V
0 0
0 0.4 0.8 1.2 1.6 2 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
0.4 0.28

ID = –3.3 A TJ = 25°C
RDS(on), DRAIN–TO–SOURCE
TJ = 25°C 0.24
0.3 0.2 VGS = –2.5 V

RESISTANCE (Ω)
0.16
0.2
0.12
VGS = –4.5 V
0.08
0.1
0.04
0 0
2 3 4 5 6 7 8 0 4 8 12 16 20
100
VGS = 0 V
ID = –3.3 A
1.4
VGS = –4.5 V
RESISTANCE (NORMALIZED)
TJ = 125°C
1.2 10
TJ = 100°C
1
1 TJ = 25°C
0.8
0.6 0.1
–50 –25 0 25 50 75 100 125 150 0 4 8 12 16 20

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63
NTGS3441T1
1200 8
VDS = 0 V VGS = 0 V TJ = 25°C

Ciss
C, CAPACITANCE (pF)
900 6
QT
(VOLTS)
Crss
600 4
Ciss Qgs Qgd
VDD = –20 V
300 2 ID = –3.3 A
Coss TJ = 25°C
Crss
0 0
8 4 0 4 8 12 16 20 0 2 4 6 8
–VGS –VDS Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE
VOLTAGE (VOLTS) Figure 8. Gate–to–Source and
Figure 7. Capacitance Variation Drain–to–Source Voltage vs. Total Charge
1.3 10
VGS(th), GATE THRESHOLD VOLTAGE
–IS, SOURCE CURRENT (AMPS) VGS = 0 V

1.2 ID = –250 µA TJ = 25°C
8
1.1
(NORMALIZED)
6
1
0.9 4
0.8
2
0.7
0.6 0
–50 –25 0 25 50 75 100 125 150 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
TJ, JUNCTION TEMPERATURE (°C) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 9. Gate Threshold Voltage Variation Figure 10. Diode Forward Voltage vs. Current
with Temperature
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64
NTGS3441T1
20
16
POWER (W)
12
0
0.01 0.10 1.00 10.00 100.00
TIME (sec)
1
Duty Cycle = 0.5

THERMAL IMPEDANCE
0.2
0.1
0.1
0.05
0.02
0.01 Single Pulse

0.01
1E–04 1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
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65
NTGS3441T1
INFORMATION FOR USING THE TSOP–6 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

must be the correct size to insure proper solder connection subjected to a solder reflow process.
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The melting temperature of solder is higher than the rated • The soldering temperature and time shall not exceed
temperature of the device. When the entire device is heated 260°C for more than 10 seconds.
to a high temperature, failure to complete soldering within • When shifting from preheating to soldering, the
a short time could result in device failure. Therefore, the maximum temperature gradient shall be 5°C or less.
following items should always be observed in order to • After soldering has been completed, the device should
minimize the thermal stress to which the devices are be allowed to cool naturally for at least three minutes.
subjected. Gradual cooling should be used as the use of forced
• Always preheat the device. cooling will increase the temperature gradient and
• The delta temperature between the preheat and result in latent failure due to mechanical stress.
soldering should be 100°C or less.* • Mechanical stress or shock should not be applied
• When preheating and soldering, the temperature of the during cooling.
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When * Soldering a device without preheating can cause
using infrared heating with the reflow soldering excessive thermal shock and stress which can result in
method, the difference shall be a maximum of 10°C. damage to the device.
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Features
• Miniature TSOP6 Surface Mount Package
2 AMPERES
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: 20 VOLTS
Cellular and Cordless Telephones, and PCMCIA Cards RDS(on) = 65 m
# $ 9
Gate–to–Source Voltage – Continuous VGS "12 Volts
Thermal Resistance
Drain Current – Continuous @ TA = 25°C ID –3.1 Amps MARKING
DIAGRAM
Thermal Resistance
Junction–to–Ambient (Note 3.) RθJA 62.5 °C/W 3
1 TSOP–6 443
CASE 318G W
4 STYLE 1
Operating and Storage Temperature Range TJ, Tstg –55 to °C 5
150 6

Purposes for 10 Seconds 443 = Device Code
W = Work Week
1. Minimum FR–4 or G–10PCB, operating to steady state.
sided), operating to steady state. PIN ASSIGNMENT
sided), t t 5.0 seconds. ()% ()% ;(1
6 5 4
1 2 3
()% ()% )'1

November, 2000 – Rev. 1 NTGS3443T1/D
NTGS3443T1
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –10 µA) –20 – –

(VGS = –12 Vdc, VDS = 0 Vdc) – – –100

(VGS = +12 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.60 –0.95 –1.50

(VGS = –4.5 Vdc, ID = –4.4 Adc) – 0.058 0.065
(VGS = –2.7 Vdc, ID = –3.7 Adc) – 0.082 0.090
(VGS = –2.5 Vdc, ID = –3.5 Adc) – 0.092 0.100
(VDS = –10 Vdc, ID = –4.4 Adc) – 8.8 –
(VDS = –5.0
5 0 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
20 Vdc, ID = –1.0
1.0 Adc, tr – 18 45 ns
Turn–Off Delay Time VGS = –4.5 Vdc, Rg = 6.0 W) td(off) – 30 50 ns
Fall Time tf – 31 50 ns
(VDS = –10
10 Vdc,
Vd VGS = –4.54 5 Vdc,
Vd
Gate–Source Charge Qgs – 1.4 – nC
ID = –4.4 Adc)
Gate–Drain Charge Qgd – 2.9 – nC

Reverse Recovery Time (IS = –1.7 Adc, dIS/dt = 100 A/µs) trr – 30 – ns
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68
NTGS3443T1
8 8
VGS = –5 V VGS = –2.5 V VDS≥ = –10 V

TJ = 25°C
6 VGS = –3 V 6
VGS = –4.5 V
VGS = –4 V
4 VGS = –3.5 V 4
VGS = –2 V
TJ = 25°C
2 2
TJ = 125°C
VGS = –1.5 V TJ = –55°C
0 0
0 0.4 0.8 1.2 1.6 2 0.6 1 1.4 1.8 2.2 2.6 3
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.4 0.16
ID = –4.4 A TJ = 25°C
0.35
TJ = 25°C 0.14
0.3
0.12 VGS = –2.5 V
0.25
0.2 VGS = –2.7 V

0.1
0.15
0.08
0.1 VGS = –4.5 V
0.06
0.05
0 0.04
1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 7 8
1.5 100
TJ = 125°C
ID = –4.4 A
1.4
VGS = –4.5 V TJ = 100°C
1.3 10
1.2
1.1 1
TJ = 25°C
1
0.9 0.1
0.8 VGS = 0 V
0.7 0.01
–50 –25 0 25 50 75 100 125 150 0 4 8 12 16 20

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69
NTGS3443T1
1200 5
QT
TJ = 25°C
1000 VGS = 0 V
–VGS, GATE–TO–SOURCE
4 VGS
C, CAPACITANCE (pF)
VOLTAGE (VOLTS)
800
3 Q1 Q2
600 Ciss
2
400
Coss
200 1 TJ = 25°C
Crss ID = –4.4 A
0 0
0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC)

1.3 4
VGS(th), GATE THRESHOLD VOLTAGE
VGS = 0 V
1.2 ID = –250 µA
1.1 3
TJ = 150°C
(NORMALIZED)
1
2
0.9 TJ = 25°C
0.8
1
0.7
0.6 0
–50 –25 0 25 50 75 100 125 150 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
TJ, JUNCTION TEMPERATURE (°C) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 9. Gate Threshold Voltage Variation Figure 10. Diode Forward Voltage vs. Current
with Temperature
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70
NTGS3443T1
20
16
POWER (W)
12
0
0.01 0.10 1.00 10.00 100.00
TIME (sec)
1
Duty Cycle = 0.5

THERMAL IMPEDANCE
0.2
0.1
0.1
0.05
0.02
0.01 Single Pulse

0.01
1E–04 1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
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NTGS3443T1

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-!
N–Channel TSOP–6
Features
• Logic Level Gate Drive
• Diode Exhibits High Speed, Soft Recovery 5.3 AMPERES
• Avalanche Energy Specified 20 VOLTS
• IDSS Specified at Elevated Temperature RDS(on) = 45 m
Applications
• Power Management in portable and battery–powered products, i.e. N–Channel
computers, printers, PCMCIA cards, cellular and cordless
Drain 1 2 5 6
• Lithium Ion Battery Applications
• Notebook PC

Rating Symbol Value Unit Gate 3

Gate–Source Voltage – Continuous VGS 12 Vdc
Source 4
Thermal Resistance
Total Power Dissipation @ TA = 25°C Pd 2.0 Watts MARKING
Drain Current
DIAGRAM
– Continuous @ TA = 25°C ID 5.3 Amps
– Pulsed Drain Current (tp t 10 µs) IDM 25 Amps 3
1 TSOP–6 446
CASE 318G W
4 STYLE 1
Drain Current 5
– Continuous @ TA = 25°C ID 3.7 Amps 6
– Pulsed Drain Current (tp t 10 µs) IDM 20 Amps 446 = Device Code
Operating and Storage Temperature Range TJ, Tstg –55 to °C W = Work Week
150
Maximum Lead Temperature for Soldering TL 260 °C PIN ASSIGNMENT
Purposes for 10 seconds
Drain Drain Source
6 5 4
sided), t t 5.0 seconds.
1 2 3
Drain Drain Gate

March, 2001 – Rev. 2 NTGS3446/D
NTGS3446T1

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
Zero Gate Voltage Collector Current IDSS µAdc
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ±12 Vdc, VDS = 0) IGSS(f) – – 100 nAdc
IGSS(r) – – –100

ID = 0.25 mA, VDS = VGS 0.6 0.85 1.2
Temperature Coefficient (Negative) – –2.5 – mV/°C
Static Drain–to–Source On–Resistance RDS(on) mW
(VGS = 4.5 Vdc, ID = 5.3 Adc) – 36 45
(VGS = 2.5 Vdc, ID = 4.4 Adc) – 44 55
Forward Transconductance (VDS = 10 Vdc, ID = 5.3 Adc) gFS – 12 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 200 350
f = 1.0 MHz)
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6.0 Ω) td(off) – 35 60
(VDS = 10 Vd
Vdc, ID = 5.3
5 3 Ad
Adc,
Qgs – 2.0 –
VGS = 4.5 Vdc)
Qgd – 2.0 –

Forward On–Voltage (Note 3.) VSD Vdc
(IS = 1.7 Adc, VGS = 0 Vdc) – 0.74 1.1
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 85°C) – 0.66 –
ta – 11 –
(IS = 1.7
1 7 Adc,
Adc VGS = 0 Vdc,
Vdc
diS/dt = 100 A/µs) tb – 9.0 –
Charge
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74
NTGS3446T1
RDS(on), DRAIN–TO–SOURCE RESISTANCE 1.8 100

ID = 5.3 A
1.6 VGS = 4.5 V tf
1.4 td(off)
(NORMALIZED)
t, TIME (ns)
tr
1.2
10
1 td(on)
0.8
VDD = 10 V
0.6 ID = 1.0 A
VGS = 4.5 V
0.4 1
–50 –25 0 25 50 75 100 125 150 1 10 100
TJ, JUNCTION TEMPERATURE (°C) RG, GATE RESISTANCE (Ω)
Figure 1. On–Resistance Variation with Figure 2. Resistive Switching Time Variation

Temperature vs. Gate Resistance
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• Higher Efficiency Extending Battery Life –3.5 AMPERES
–30 VOLTS
Applications
100 m @ VGS = –10 V
Cellular and Cordless Telephones, and PCMCIA Cards
P–Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.) 1 2 5 6

DRAIN
3
Thermal Resistance GATE
Drain Current –3.5 Amps 4
– Continuous @ TA = 25°C ID SOURCE
Maximum Operating Power Dissipation Pd 1.0 Watts
MARKING
DIAGRAM
Thermal Resistance
3
1 TSOP–6
Drain Current 455
– Continuous @ TA = 25°C ID –2.5 Amps CASE 318G x
– Pulsed Drain Current (Tp t 10 µS) IDM –14 Amps 4 STYLE 1
Maximum Operating Power Dissipation Pd 0.5 Watts 5
6
Operating and Storage Temperature Range TJ, Tstg –55 to °C 455 = Device Code
150 x = Date Code
Purposes for 10 Seconds
PIN ASSIGNMENT
sided), t t 5.0 seconds. Drain Drain ;(1
2. Mounted onto a 2″ square FR–4 board (1″ sq. 2 oz. cu. 0.06″ thick single 6 5 4
1 2 3
Drain Drain Gate


December, 2000 – Rev. 0 NTGS3455T1/D
NTGS3455T1
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –10 µA) –30 – –

(VGS = –20.0 Vdc, VDS = 0 Vdc) – – –100

(VGS = +20.0 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –1.0 –1.87 –3.0

(VGS = –10 Vdc, ID = –3.5 Adc) – 0.094 0.100
(VGS = –4.5 Vdc, ID = –2.7 Adc) – 0.144 0.170
(VDS = –15 Vdc, ID = –3.5 Adc) – 6.0 –
(VDS = –15
15 Vdc,
Vd VGS = –1010 Vdc,
Vd
ID = –3.5 Adc)
(VDS = –5.0
5 0 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
20 Vdc, ID = –1.0
1.0 Adc, tr – 15 30
Turn–Off Delay Time VGS = –10 Vdc, Rg = 6.0 W) td(off) – 20 35
Reverse Recovery Time (IS = –1.7 Adc, dlS/dt = 100 A/µs) trr – 30 – ns
4. Class 1 ESD rated – Handling precautions to protect against electrostatic discharge is mandatory.
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77
NTGS3455T1
20 20
VGS = –10 V
18 TJ = –55°C

VGS = –9 V
16 VGS = –6 V 16
VGS = –8 V
14 TJ = 25°C
VGS = –7 V
12 VGS = –5 V 12 TJ = 125°C
10
8 VGS = –4 V 8
6
4 4
TJ = 25°C VGS = –3 V 2
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 4 5 6 7

0.3 0.3
TJ = 25°C
ID = –3.5 A
0.25 0.25
TJ = 25°C
0.2 0.2 VGS = –4.5 V
0.15 0.15
VGS = –10 V
0.1 0.1
0.05 0.05
0 0
2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20
1.6 700
ID = –3.5 A VGS = 0 V
VGS = –10 V TJ = 25°C
1.4
C, CAPACITANCE (pF)
500
Ciss
1.2
300
1 Coss
100
0.8
Crss
0.6 –100
–50 –25 0 25 50 75 100 125 150 0 5 10 15 20 25 30

Temperature
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78
NTGS3455T1
12 10
11

VGS = 0 V
10 QT
8
9
8
6 TJ = 150°C
(VOLTS)
7
6
Qgs
5 4
Qgd
4
TJ = 25°C
3
TJ = 25°C 2
2
ID = –3.5 A
1
0 0
0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4
Qg, TOTAL GATE CHARGE (nC) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 7. Gate–to–Source and Figure 8. Diode Forward Voltage vs. Current

1
Duty Cycle = 0.5

THERMAL IMPEDANCE
0.2
0.1
0.1
0.05
0.02
0.01 Single Pulse

0.1
1E–04 1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
20
16
POWER (W)
12
0
0.01 0.10 1.00 10.00 100.00
TIME (sec)
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.)

/0 10% ! 23
'(
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D1 D2
G1 G2
PRODUCT SUMMARY S1 S2
VDS (V) rDS(on) (Ω) ID (A)
0.085 @ VGS = 10 V "3.9 N–Channel MOSFET N–Channel MOSFET
30
0.143 @ VGS = 4.5 V "3.0
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Steady
Rating Symbol 5 secs State Unit ChipFET
Drain–Source Voltage VDS 30 V CASE 1206A
STYLE 2
Gate–Source Voltage VGS "20 V
Continuous Drain Current ID A
(TJ = 150°C) (Note 1.) PIN CONNECTIONS
TA = 25°C "3.9 "2.9
TA = 85°C "2.8 "2.1
D1 8 1 S1
Pulsed Drain Current IDM "10 A
D1 7 2 G1
Continuous Source Current IS 1.8 0.9 A
(Diode Conduction) (Note 1.) D2 6 3 S2
Maximum Power Dissipation PD W
D2 5 4 G2
(Note 1.)
TA = 25°C 2.1 1.1
TA = 85°C 1.1 0.6
Operating Junction and Storage TJ, Tstg –55 to +150 °C MARKING DIAGRAM
Temperature Range
1. Surface Mounted on 1″ x 1″ FR4 Board.
A6
A6 = Specific Device Code

This document contains information on a product under development. ON Semiconductor NTHD5902T1 ChipFET 3000/Tape & Reel

December, 2000 – Rev. 0 NTHD5902T1/D
NTHD5902T1
Characteristic Symbol Typ Max Unit
Maximum Junction–to–Ambient (Note 2.) RthJA °C/W
t v 5 sec 50 60
Steady State 90 110
Maximum Junction–to–Foot RthJF 30 40 °C/W
Steady State

Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.0 – – V
Gate–Body Leakage IGSS VDS = 0 V, VGS = "20 V – – "100 nA
Zero Gate Voltage Drain Current IDSS
SS VDS = 24 V, VGS = 0 V – – 1.0 µA
VDS = 24 V, VGS = 0 V, – – 5.0
TJ = 85°C
On–State Drain Current (Note 3.) ID(on) VDS w 5.0 V, VGS = 10 V 10 – – A

Drain–Source On–State Resistance (Note 3.) rDS(on)
S( ) VGS = 10 V, ID = 2.9 A – 0.072 0.085 Ω
VGS = 4.5 V, ID = 2.2 A – 0.120 0.143
Forward Transconductance (Note 3.) gfs VDS = 15 V, ID = 2.9 A – 20 – S
Diode Forward Voltage (Note 3.) VSD IS = 0.9 A, VGS = 0 V – 0.8 1.2 V
Dynamic (Note 4.)
Total Gate Charge Qg – 5.0 7.5 nC
VDS = 15 V
V, VGS = 10 V
V,
ID = 2.9 A
Rise Time tr VDD = 15 V, RL = 15 Ω – 12 18
ID ^ 1.0
1 0 A,
A VGEN = 10 V,V
Turn–Off Delay Time td(off) RG = 6 Ω – 12 18
Source–Drain Reverse Recovery Time trr IF = 0.9 A, di/dt = 100 A/µs – 40 80
3. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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NTHD5902T1
10 10
VGS = 10
thru 5 V
8 8
ID,Drain Current (A)

6 4V 6
4 4
125°C
2 2 25°C
3V
TC = –55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5
VDS, Drain–to–Source Voltage (V) VGS, Gate–to–Source Voltage (V)
Figure 1. Output Characteristics Figure 2. Transfer Characteristics
0.20 400
r DS(on),On–Resistance ( Ω )
300
Ciss
0.15
C, Capacitance (pF)
VGS = 4.5 V
0.10 200
VGS = 10 V
Coss
0.05
100 Crss
0 0
0 2 4 6 8 10 0 4 8 12 16 20
ID, Drain Current (A) VDS, Drain–to–Source Voltage (V)
Figure 3. On–Resistance vs. Drain Current Figure 4. Capacitance
10 1.8
VGS = 10 V
VGS,Gate–to–Source Voltage (V)
VDS = 15 V 1.6
8 ID = 2.9 A
ID = 2.9 A
(Normalized)
1.4
6
1.2
4
1.0
2 0.8
0 0.6
0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 150
Qg, Total Gate Charge (nC) TJ, Junction Temperature (°C)
Figure 5. Gate Charge Figure 6. On–Resistance vs.
Junction Temperature
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NTHD5902T1
10 0.20
rDS(on),On–Resistance ( Ω )
I S,Source Current (A)
0.15
ID = 2.9 A
TJ = 150°C
0.10
TJ = 25°C
0.05
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10
Figure 7. Source–Drain Diode Forward Voltage Figure 8. On–Resistance vs. Gate–to–Source
Voltage
0.4 50
0.2 40
ID = 250 µA
V GS (th),Varience (V)
–0.0
Power (W)
30
–0.2
20
–0.4
10
–0.6
–0.8 0
–50 –25 0 25 50 75 100 125 150 10–4 10–3 10–2 10 –1 1 10 100 600
TJ, Temperature (°C) Time (sec)
Figure 9. Threshold Voltage Figure 10. Single Pulse Power
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NTHD5902T1

2
1
Normalized Effective Transient
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
1. Duty Cycle, D = t
0.02 2
2. Per Unit Base = RthJA = 90°C/W
3. TJM – TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
Square Wave Pulse Duration (sec)
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
Figure 12. Normalized Thermal Transient Impedance, Junction–to–Foot
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S1 S2
G1 G2
PRODUCT SUMMARY D1 D2
P–Channel MOSFET P–Channel MOSFET
0.155 @ VGS = –4.5 V "2.9
–20 0.180 @ VGS = –3.6 V "2.7

0.260 @ VGS = –2.5 V "2.2

ChipFET
Steady CASE 1206A
Rating Symbol 5 secs State Unit STYLE 2
Drain–Source Voltage VDS –20 V
Gate–Source Voltage VGS "12 V PIN CONNECTIONS
(TJ = 150°C) (Note 1.)
TA = 25°C "2.9 "2.1 D1 8 1 S1
TA = 85°C "2.1 "1.5
D1 7 2 G1
D2 6 3 S2
Continuous Source Current IS –1.8 –0.9 A
(Diode Conduction) (Note 1.) D2 5 4 G2
(Note 1.)
TA = 25°C 2.1 1.1
TA = 85°C 1.1 0.6 MARKING DIAGRAM
Operating Junction and Storage TJ, Tstg –55 to +150 °C
Temperature Range
A7

NTHD5903T1
t v 5 sec 50 60
Steady State 90 110
Maximum Junction–to–Foot (Drain) RthJF 30 40 °C/W
Steady State

Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = –250 µA –0.6 – – V
SS VDS = –16 V, VGS = 0 V – – –1.0 µA
VDS = –16 V, VGS = 0 V, – – –5.0
TJ = 85°C
On–State Drain Current (Note 3.) ID(on) VDS v –5.0 V, VGS = –4.5 V –10 – – A
S( ) VGS = –4.5 V, ID = –2.1 A – 0.130 0.155 Ω
VGS = –3.6 V, ID = –2.0 A – 0.150 0.180
VGS = –2.5 V, ID = –1.7 A – 0.215 0.260
Forward Transconductance (Note 3.) gfs VDS = –10 V, ID = –2.1 A – 5.0 – S
Diode Forward Voltage (Note 3.) VSD IS = –0.9 A, VGS = 0 V – –0.8 –1.2 V
Dynamic (Note 4.)
10 V
VDS = –10 V, VGS = –4.5
45V V,
ID = –2.1 A
Rise Time tr VDD = –10 V, RL = 10 Ω – 35 55
ID ^ –1.0
–1 0 A
A, VGEN = –4
–4.5
5VV,
Source–Drain Reverse Recovery Time trr IF = –0.9 A, di/dt = 100 A/µs – 40 80
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NTHD5903T1
10 10
3.5 V
VGS = 5 thru 4 V TC = –55°C
8 8
3V
I D,Drain Current (A)

25°C
6 6 125°C
2.5 V
4 4
2V
2 2
1.5 V
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0.4 600
500
0.3 VGS = 2.5 V
C, Capacitance (pF)
Ciss
400
0.2 VGS = 3.6 V 300
VGS = 4.5 V 200

0.1
Coss
100
Crss
0 0
0 2 4 6 8 10 0 4 8 12 16 20
5 1.6
VDS = 10 V VGS = 4.5 V

4 ID = 2.1 A 1.4
ID = 2.1 A
(Normalized)
3 1.2
2 1.0
1 0.8
0 0.6
0 0.5 1.0 1.5 2.0 2.5 3.0 –50 –25 0 25 50 75 100 125 150

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NTHD5903T1
10 0.40
0.35
ID = 2.1 A
0.30
0.25
TJ = 150°C 0.20
0.15
TJ = 25°C
0.10
0.05
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 5
Voltage
0.4 50
0.3
40
ID = 250 µA
0.2
Power (W)
30
0.1
20
0.0
10
–0.1
–0.2 0
–50 –25 0 25 50 75 100 125 150 10–4 10–3 10–2 10 –1 1 10 100 600
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NTHD5903T1

2
1
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
0.02 2
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
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D1 D2
G1 G2
PRODUCT SUMMARY S1 S2

N–Channel MOSFET N–Channel MOSFET
0.075 @ VGS = 4.5 V "4.2
20
0.134 @ VGS = 2.5 V "3.1

Steady
ChipFET
Rating Symbol 5 secs State Unit
CASE 1206A
Drain–Source Voltage VDS 20 V STYLE 2
Continuous Drain Current ID A PIN CONNECTIONS
(TJ = 150°C) (Note 1.)
TA = 25°C "4.2 "3.1
TA = 85°C "3.0 "2.2 D1 8 1 S1
Pulsed Drain Current IDM "10 A D1 7 2 G1

Continuous Source Current IS 1.8 0.9 A D2 6 3 S2
(Diode Conduction) (Note 1.)
D2 5 4 G2
(Note 1.)
TA = 25°C 2.1 1.1
Temperature Range
1. Surface Mounted on 1″ x 1″ FR4 Board. A2

NTHD5904T1
t v 5 sec 50 60
Steady State 90 110
Steady State

Static
SS VDS = 16 V, VGS = 0 V – – 1.0 µA
VDS = 16 V, VGS = 0 V, – – 5.0
TJ = 85°C
On–State Drain Current (Note 3.) ID(on) VDS w 5.0 V, VGS = 4.5 V 10 – – A
S( ) VGS = 4.5 V, ID = 3.1 A – 0.065 0.075 Ω
VGS = 2.5 V, ID = 2.3 A – 0.115 0.143
Forward Transconductance (Note 3.) gfs VDS = 10 V, ID = 3.1 A – 8.0 – S
Dynamic (Note 4.)
VDS = 10 V
V, VGS = 4.5
4 5 V,
V
ID = 3.1 A
ID ^ 1.0
1 0 A,
A VGEN = 4.5
4 5 V,
V
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NTHD5904T1
10 10
TC = –55°C
VGS = 5 thru 3 V
8 8 25°C
D,Drain Current (A)

2.5 V 125°C
6 6
4 4
I
2V
2 2
1.5 V
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0.30 600
0.25 500
Ciss
C, Capacitance (pF)
0.20 400
0.15 VGS = 2.5 V 300
0.10 200 Coss

VGS = 4.5 V
0.05 100 Crss
0 0
0 2 4 6 8 10 0 4 8 12 16 20
5 1.6
VGS = 4.5 V
VDS = 10 V
4 ID = 3.1 A 1.4 ID = 3.1 A
(Normalized)
3 1.2
2 1.0
1 0.8
0 0.6
0 1 2 3 4 –50 –25 0 25 50 75 100 125 150
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NTHD5904T1
10 0.20
0.15
ID = 3.1 A
TJ = 150°C
0.10
TJ = 25°C
0.05
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5
Voltage
0.4 50
0.2
40
–0.0 ID = 250 µA
Power (W)
30
–0.2
20
–0.4
10
–0.6
–0.8 0
–50 –25 0 25 50 75 100 125 150 10–4 10–3 10–2 10 –1 1 10 100 600
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NTHD5904T1

2
1
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
0.02 2
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
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S1 S2
G1 G2
PRODUCT SUMMARY D1 D2

P–Channel MOSFET P–Channel MOSFET
0.090 @ VGS = –4.5 V "4.1
–8.0 0.130 @ VGS = –2.5 V "3.4

0.180 @ VGS = –1.8 V "2.9

ChipFET
Steady CASE 1206A
Drain–Source Voltage VDS –8.0 V
Gate–Source Voltage VGS "8.0 V
PIN CONNECTIONS
(TJ = 150°C) (Note 1.)
TA = 25°C "4.1 "3.0 D1 8 1 S1
TA = 85°C "2.9 "2.2
D1 7 2 G1
Continuous Source Current IS –1.8 –0.9 A D2 6 3 S2
D2 5 4 G2
(Note 1.)
TA = 25°C 2.1 1.1
Temperature Range
A9

NTHD5905T1
t v 5 sec 50 60
Steady State 90 110
Steady State

Static
Gate–Body Leakage IGSS VDS = 0 V, VGS = "8.0 V – – "100 nA
SS VDS = –6.4 V, VGS = 0 V – – –1.0 µA
VDS = –6.4 V, VGS = 0 V, – – –5.0
TJ = 85°C
S( ) VGS = –4.5 V, ID = –3.0 A – 0.075 0.090 Ω
VGS = –2.5 V, ID = –2.5 A – 0.110 0.130
VGS = –1.8 V, ID = –1.0 A – 0.150 0.180
Forward Transconductance (Note 3.) gfs VDS = –5.0 V, ID = –3.0 A – 7.0 – S
Dynamic (Note 4.)
40V
VDS = –4.0 V, VGS = –4.5
45V V,
ID = –3.0 A
Rise Time tr VDD = –4.0 V, RL = 4 Ω – 45 70
ID ^ –1.0
–1 0 A
A, VGEN = –4
–4.5
5VV,
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NTHD5905T1
10 10
VGS = 5 2.5 V TC = –55°C
thru 3 V
8 8 25°C
D,Drain Current (A)

2V 125°C
6 6
4 4
1.5 V
2 2
1V
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0
0.30 1000
0.25
800
VGS = 1.8 V Ciss
C, Capacitance (pF)
0.20
600
0.15 VGS = 2.5 V
400
VGS = 4.5 V
0.10
Coss
200
0.05
Crss
0 0
0 2 4 6 8 10 0 4 8 12 16 20
5 1.6
VGS = 4.5 V
4 1.4 ID = 3 A
(Normalized)
3 1.2
2 1.0
1 0.8
0 0.6
0 1 2 3 4 5 6 –50 –25 0 25 50 75 100 125 150

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NTHD5905T1
10 0.25
0.20 ID = 3 A
0.15
TJ = 150°C
0.10
0.05
TJ = 25°C
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 5
Figure 7. Source Diode Forward Voltage Figure 8. On–Resistance vs. Gate–to–Source

Voltage
0.4 50
0.3
40
0.2 ID = 250 µA
Power (W)
30
0.1
20
0.0
10
–0.1
–0.2 0
–50 –25 0 25 50 75 100 125 150 10–4 10–3 10–2 10 –1 1 10 100 600
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NTHD5905T1
1
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
0.02 2
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
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PRODUCT SUMMARY S
VDS (V) rDS(on) (Ω) ID (A) N–Channel MOSFET

0.035 @ VGS = 10 V "6.7
30
0.055 @ VGS = 4.5 V "5.3

ChipFET
Steady
CASE 1206A
STYLE 1
Drain–Source Voltage VDS 30 V
PIN CONNECTIONS
(TJ = 150°C) (Note 1.)
TA = 25°C "6.7 "4.9 D 8 1 D
TA = 85°C "4.8 "3.5
Pulsed Drain Current IDM "20 A D 7 2 D
Continuous Source Current IS 2.1 1.1 A D 6 3 D

S 5 4 G
(Note 1.)
TA = 25°C 2.5 1.3
TA = 85°C 1.3 0.7
MARKING DIAGRAM
Temperature Range
NTHS5402T1 ChipFET 3000/Tape & Reel

December, 2000 – Rev. 0 NTHS5402T1/D
NTHS5402T1
t v 5 sec 40 50
Steady State 80 95
Steady State

Static
SS VDS = 24 V, VGS = 0 V – – 1.0 µA
VDS = 24 V, VGS = 0 V, – – 5.0
TJ = 85°C
On–State Drain Current (Note 3.) ID(on) VDS w 5.0 V, VGS = 10 V 20 – – A

S( ) VGS = 10 V, ID = 4.9 A – 0.030 0.035 Ω
VGS = 4.5 V, ID = 3.9 A – 0.045 0.055
Dynamic (Note 4.)
Total Gate Charge Qg – 13 20 nC
VDS = 15 V
V, VGS = 10 V
V,
ID = 4.9 A
ID ^ 1.0
1 0 A,
A VGEN = 10 V,V
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NTHS5402T1
TYPICAL CHARACTERISTICS
20 20
VGS = 10 thru 5 V
4V
16 16

12 12
8 8
3V TC125°C
4 4 25°C
TC = –55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0.10 1200
1000
0.08 Ciss
C, Capacitance (pF)
800
0.06
VGS = 4.5 V
600
0.04 VGS = 10 V
400
0.02 Coss
200
Crss
0 0
0 4 8 12 16 20 0 6 12 18 24 30
10 1.6
VDS = 15 V VGS = 10 V
8 ID = 4.9 A 1.4
ID = 4.9 A
(Normalized)
6 1.2
4 1.0
2 0.8
0 0.6
0 3 6 9 12 15 –50 –25 0 25 50 75 100 125 150

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NTHS5402T1
20 0.10
TJ = 150°C
10 0.08
ID = 4.9 A
0.06
0.04
TJ = 25°C
0.02
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10
VSD, Source–to–Drain Voltage (V) VGS, Gate–to–Source Voltage (V)

Voltage
0.4 50
0.2
40
ID = 250 µA
–0.0
Power (W)
30
–0.2
20
–0.4
10
–0.6
–0.8 0
–50 –25 0 25 50 75 100 125 150 10–3 10–2 10 –1 1 10 100 600
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NTHS5402T1
1
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
2
0.02 2. Per Unit Base = RthJA = 80°C/W
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
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NTHS5402T1
80 mm 80 mm
18 mm
25 mm
68 mm
28 mm 28 mm
26 mm 26 mm
Figure 13. Figure 14.
BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in confines of the basic footprint. The drain copper area is
Figure 13. This is sufficient for low power dissipation 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
MOSFET applications, but power semiconductor dissipation path away from the device (through the copper
performance requires a greater copper pad area, leadframe) and into the board and exterior chassis (if
particularly for the drain leads. applicable) for the single device. The addition of a further
The minimum recommended pad pattern shown in copper area and/or the addition of vias to other board layers
Figure 14 improves the thermal area of the drain will enhance the performance still further.
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
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PRODUCT SUMMARY S
VDS (V) rDS(on) (Ω) ID (A) N–Channel MOSFET
0.030 @ VGS = 4.5 V "7.2

20
0.045 @ VGS = 2.5 V "5.9
MAXIMUM RATINGS (TA = 25°C unless otherwise noted) ChipFET

Steady CASE 1206A
Drain–Source Voltage VDS 20 V

(TJ = 150°C) (Note 1.)
TA = 25°C "7.2 "5.2 D 8 1 D
TA = 85°C "5.2 "3.8
D 7 2 D
D 6 3 D
Continuous Source Current IS 2.1 1.1 A
(Diode Conduction) (Note 1.) S 5 4 G
(Note 1.)
TA = 25°C 2.5 1.3
Temperature Range

NTHS5404T1 ChipFET 3000/Tape & Reel

NTHS5404T1
t v 5 sec 40 50
Steady State 80 95
Steady State

Static
SS VDS = 16 V, VGS = 0 V – – 1.0 µA
VDS = 16 V, VGS = 0 V, – – 5.0
TJ = 85°C
On–State Drain Current (Note 3.) ID(on) VDS w 5.0 V, VGS = 4.5 V 20 – – A
S( ) VGS = 4.5 V, ID = 5.2 A – 0.025 0.030 Ω
VGS = 2.5 V, ID = 4.3 A – 0.038 0.045
Dynamic (Note 4.)
VDS = 10 V
V, VGS = 4.5
4 5 V,
V
ID = 5.2 A
ID ^ 1.0
1 0 A,
A VGEN = 4.5
4 5 V,
V
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NTHS5404T1
80 mm 80 mm
18 mm
25 mm
68 mm
28 mm 28 mm
26 mm 26 mm
Figure 1. Figure 2.
BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in the basic footprint. The drain copper area is 0.0054 sq. in.
Figure 1. This is sufficient for low power dissipation (or 3.51 sq. mm). This will assist the power dissipation path
MOSFET applications, but power semiconductor away from the device (through the copper leadframe) and
performance requires a greater copper pad area, into the board and exterior chassis (if applicable) for the
particularly for the drain leads. single device. The addition of a further copper area and/or
The minimum recommended pad pattern shown in the addition of vias to other board layers will enhance the
Figure 2 improves the thermal area of the drain connections performance still further.
(pins 1, 2, 3, 6, 7, 8) while remaining within the confines of
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D
PRODUCT SUMMARY
VDS (V) rDS(on) (Ω) ID (A) P–Channel MOSFET
0.055 @ VGS = –4.5 V "5.3
–20 0.06 @ VGS = –3.6 V "5.1

0.083 @ VGS = –2.5 V "4.3
ChipFET
MAXIMUM RATINGS (TA = 25°C unless otherwise noted) CASE 1206A
Steady STYLE 1
(TJ = 150°C) (Note 1.)
D 8 1 D
TA = 25°C "5.3 "3.9
TA = 85°C "3.8 "2.8
D 7 2 D
D 6 3 D
Continuous Source Current IS –2.1 –1.1 A
(Note 1.) S 5 4 G
(Note 1.)
TA = 25°C 2.5 1.3
MARKING DIAGRAM
TA = 85°C 1.3 0.7
Temperature Range
A3
This document contains information on a product under development. ON Semiconductor NTHS5441T1 ChipFET 3000/Tape & Reel

NTHS5441T1
t v 5 sec 40 50
Steady State 80 95
Steady State

Static
SS VDS = –16 V, VGS = 0 V – – –1.0 µA
VDS = –16 V, VGS = 0 V, – – –5.0
TJ = 85°C
S( ) VGS = –3.6 V, ID = –3.7 A – 0.050 0.06 Ω
VGS = –2.5 V, ID = –3.1 A – 0.070 0.083
Forward Transconductance (Note 3.) gfs VDS = –10 V, ID = –3.9 A – 12 – S
Dynamic (Note 4.)
VDS = –10
10 V
V, VGS = –4.5
45V V,
ID = –3.9 A
ID ^ –1.0
–1 0 A
A, VGEN = –4
–4.5
5VV,
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110
NTHS5441T1
80 mm 80 mm
18 mm
25 mm
68 mm
28 mm 28 mm
26 mm 26 mm
Figure 1. Figure 2.
BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in the basic footprint. The drain copper area is 0.0054 sq. in.
Figure 1. This is sufficient for low power dissipation (or 3.51 sq. mm). This will assist the power dissipation path
MOSFET applications, but power semiconductor away from the device (through the copper leadframe) and
performance requires a greater copper pad area, into the board and exterior chassis (if applicable) for the
particularly for the drain leads. single device. The addition of a further copper area and/or
The minimum recommended pad pattern shown in the addition of vias to other board layers will enhance the
Figure 2 improves the thermal area of the drain connections performance still further.
(pins 1, 2, 3, 6, 7, 8) while remaining within the confines of
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D
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω) ID (A) P–Channel MOSFET
0.065 @ VGS = –4.5 V "4.9
–20 0.074 @ VGS = –3.6 V "4.6

0.110 @ VGS = –2.5 V "3.8
ChipFET
MAXIMUM RATINGS (TA = 25°C unless otherwise noted) CASE 1206A
STYLE 1
Steady
PIN CONNECTIONS
(TJ = 150°C) (Note 1.) D 8 1 D
TA = 25°C "4.9 "3.6
TA = 85°C "3.5 "2.6 D 7 2 D
Pulsed Drain Current IDM "15 A D 6 3 D

Continuous Source Current IAS –2.1 –1.1 A S 5 4 G
(Note 1.)
(Note 1.)
TA = 85°C 1.3 0.7
Temperature Range A4

January, 2001 – Rev. 1 NTHS5443T1/D
NTHS5443T1
t v 5 sec 40 50
Steady State 80 95
Steady State

Static
SS VDS = –16 V, VGS = 0 V – – –1.0 µA
VDS = –16 V, VGS = 0 V, – – –5.0
TJ = 85°C
Drain–Source On–State Resistance rDS(on)
S( ) VGS = –4.5 V, ID = –3.6 A – 0.056 0.065 Ω
(N t 3
(Note 3.))
VGS = –3.6 V, ID = –3.3 A – 0.065 0.074
VGS = –2.5 V, ID = –2.7 A – 0.095 0.110
Forward Transconductance (Note 3.) gfs VDS = –10 V, ID = –3.6 A – 10 – S
Dynamic (Note 4.)
Total Gate Charge Qg – 9.0 14 nC
10 V
VDS = –10 V, VGS = –4.5
45V V,
ID = –3.6 A
Turn–On Delay Time td(on) – 15 25 µs
ID ^ –1.0
–1 0 A
A, VGEN = –4
–4.5
5VV,
Source–Drain Reverse Recovery Time trr IF = –1.1 A, di/dt = 100 A/µs – 30 60 ns
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PRODUCT SUMMARY D
VDS (V) rDS(on) (Ω) ID (A) P–Channel MOSFET

0.035 @ VGS = –4.5 V "7.1
–8.0 0.047 @ VGS = –2.5 V "6.2

0.062 @ VGS = –1.8 V "5.7
MAXIMUM RATINGS (TA = 25°C unless otherwise noted) ChipFET

Steady CASE 1206A
Drain–Source Voltage VDS –8.0 V

Gate–Source Voltage VGS "8.0 V
PIN CONNECTIONS
(TJ = 150°C) (Note 1.)
TA = 25°C "7.1 "5.2 D 8 1 D
TA = 85°C "5.2 "3.7
D 7 2 D
Continuous Source Current IS –2.1 –1.1 A D 6 3 D
(Note 1.)
S 5 4 G
(Note 1.)
TA = 25°C 2.5 1.3
Temperature Range
A5


January, 2001 – Rev. 1 NTHS5445T1/D
NTHS5445T1
t v 5 sec 40 50
Steady State 80 95
Steady State

Static
Gate–Body Leakage IGSS VDS = 0 V, VGS = "8.0 V – – "100 nA
SS VDS = –6.4 V, VGS = 0 V – – –1.0 µA
VDS = –6.4 V, VGS = 0 V, – – –5.0
TJ = 85°C
S( ) VGS = –4.5 V, ID = –5.2 A – 0.030 0.035 Ω
VGS = –2.5 V, ID = –4.5 A – 0.040 0.047
VGS = –1.8 V, ID = –2.0 A – 0.052 0.062
Forward Transconductance (Note 3.) gfs VDS = –5.0 V, ID = –5.2 A – 18 – S
Dynamic (Note 4.)
40V
VDS = –4.0 V, VGS = –4.5
45V V,
ID = –5.2 A
Rise Time tr VDD = –4.0 V, RL = 4 Ω – 45 70
ID ^ –1.0
–1 0 A
A, VGEN = –4
–4.5
5VV,
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NTHS5445T1
20 20
VGS = 5 thru 2.5 V TC = –55°C
16 2V 16 25°C

12 12 125°C
8 8
1.5 V
4 4
1V
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5
0.10 3000
2500
0.08 VGS = 1.8 V Ciss
C, Capacitance (pF)
2000
0.06
VGS = 2.5 V 1500
0.04 VGS = 4.5 V Coss
1000
0.02
500
Crss
0 0
0 4 8 12 16 20 0 2 4 6 8
5 1.6
VDS = 4 V VGS = 4.5 V

4 ID = 5.2 A 1.4
ID = 5.2 A
(Normalized)
3 1.2
2 1.0
1 0.8
0 0.6
0 4 8 12 16 20 –50 –25 0 25 50 75 100 125 150
Figure 5. Gate Charge Figure 6. On–Resistance vs. Junction
Temperature
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116
NTHS5445T1
20 0.10
TJ = 150°C
10 0.08
0.06 ID = 5.2 A
0.04
TJ = 25°C
0.02
1 0
0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5

Voltage
0.4 50
0.3
40
ID = 250 µA
0.2
Power (W)
30
0.1
20
0.0
10
–0.1
–0.2 0
–50 –25 0 25 50 75 100 125 150 10–3 10–2 10 –1 1 10 100 600
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NTHS5445T1

2
1
Duty Cycle = 0.5

Thermal Impedance
Notes:
PDM
0.2
t1
0.1 t2
0.1
0.05 t1
2
0.02 2. Per Unit Base = RthJA = 80°C/W
0.01
10–4 10–3 10–2 10 –1 1 10 100 600
2
1
Duty Cycle = 0.5
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10–4 10–3 10–2 10 –1 1 10
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118
NTHS5445T1
80 mm 80 mm
18 mm
25 mm
68 mm
28 mm 28 mm
26 mm 26 mm
Figure 13. Figure 14.
BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in confines of the basic footprint. The drain copper area is
Figure 13. This is sufficient for low power dissipation 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
MOSFET applications, but power semiconductor dissipation path away from the device (through the copper
performance requires a greater copper pad area, leadframe) and into the board and exterior chassis (if
particularly for the drain leads. applicable) for the single device. The addition of a further
The minimum recommended pad pattern shown in copper area and/or the addition of vias to other board layers
Figure 14 improves the thermal area of the drain will enhance the performance still further.
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
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!#!

#$%& '(
!- !
Dual P–Channel SO–8
Features
http://onsemi.com
• High Efficiency Components in a Dual SO–8 Package
• High Density Power MOSFET with Low RDS(on)
• Miniature SO–8 Surface Mount Package – Saves Board Space –3.05 AMPERES
• Diode Exhibits High Speed with Soft Recovery –30 VOLTS
• Avalanche Energy Specified
0.085 W @ VGS = –10 V
• Mounting Information for the SO–8 Package is Provided
P–Channel
Applications
• DC–DC Converters D
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
G
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit S
Drain–to–Source Voltage VDSS –30 V
Gate–to–Source Voltage – Continuous VGS ±20 V MARKING
DIAGRAM
Thermal Resistance –
SO–8 ED3P03
Continuous Drain Current @ 25°C ID –2.34 A
CASE 751 LYWW
Continuous Drain Current @ 70°C ID –1.87 A 8
STYLE 11
Pulsed Drain Current (Note 4.) IDM –8.0 A
Thermal Resistance – 1
Total Power Dissipation @ TA = 25°C PD 1.25 W ED3P03 = Device Code
Continuous Drain Current @ 25°C ID –3.05 A L = Assembly Location
Continuous Drain Current @ 70°C ID –2.44 A Y = Year
Pulsed Drain Current (Note 4.) IDM –12 A WW = Work Week
Junction–to–Ambient (Note 3.) RθJA 62.5 °C/W PIN ASSIGNMENT
Source–1 1 8 Drain–1
Pulsed Drain Current (Note 4.) IDM –15 A Gate–1 2 7 Drain–1
Operating and Storage TJ, Tstg –55 to °C Source–2 3 6 Drain–2
Gate–2 4 5 Drain–2
Energy – Starting TJ = 25°C Top View
(VDD = –30 Vdc, VGS = –4.5 Vdc, Peak
IL = –7.5 Apk, L = 5 mH, RG = 25 Ω) ORDERING INFORMATION
Purposes, 1/8″ from case for 10 seconds Device Package Shipping
1. Minimum FR–4 or G–10 PCB, t = Steady State.
NTMD3P03R2 SO–8 2500/Tape & Reel
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t = steady state.
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single This document contains information on a product under
sided), t ≤ 10 seconds. development. ON Semiconductor reserves the right to
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. change or discontinue this product without notice.

January, 2001 – Rev. 0 NTMD3P03R2/D
NTMD3P03R2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5.)

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –30 – –
Temperature Coefficient (Positive) – –30 – mV/°C
(VDS = –24 Vdc, VGS = 0 Vdc, TJ = 25°C) – – –1.0
(VDS = –24 Vdc, VGS = 0 Vdc, TJ = 125°C) – – –20
(VGS = –20 Vdc, VDS = 0 Vdc) – – –100
(VGS = +20 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –1.0 –1.7 –2.5
Temperature Coefficient (Negative) – 3.6 –
Static Drain–to–Source On–State Resistance RDS(on) Ω
(VGS = –10 Vdc, ID = –3.05 Adc) – 0.063 0.085
(VGS = –4.5 Vdc, ID = –1.5 Adc) – 0.090 0.125
Forward Transconductance (VDS = –15 Vdc, ID = –3.05 Adc) gFS – 5.0 – Mhos
Output Capacitance (VDS = –24
24 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 170 325
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Notes 6. and 7.)
Rise Time (VDD = –24 Vdc, ID = –3.05 Adc, tr – 16 30
VGS = –10
10 Vdc
Vdc,
Rise Time (VDD = –24 Vdc, ID = –1.5 Adc, tr – 42 –
VGS = –4.5
4 5 Vdc,
Vdc
Total Gate Charge Qtot – 16 25 nC
(VDS = –24 Vdc,
Gate–Source Charge VGS = –10 Vdc, Qgs – 2.0 –
ID = –3.05
3 05 Adc)
Ad )

Diode Forward On–Voltage (IS = –3.05 Adc, VGS = 0 V) VSD – –0.96 –1.25 Vdc
(IS = –3.05 Adc, VGS = 0 V, TJ = 125°C) – –0.78 –
(IS = –3.05
3 05 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 18 –
dIS/dt = 100 A/µs)
tb – 16 –
6. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
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121
NTMD3P03R2
6 6
VGS = –10 V
VGS = –4.4 V VDS > = –10 V

5 VGS = –8 V 5
VGS = –4 V
VGS = –6 V
VGS = –4.6 V
4 4
TJ = 25°C VGS = –4.8 V TJ = 100°C
3 VGS = –3.6 V 3
VGS = –2.8 V
VGS = –3.2 V TJ = 25°C
2 VGS = –5 V 2
VGS = –3 V TJ = –55°C
VGS = –2.6 V
1 1
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 2 3 4 5


0.7 0.7
ID = –3.05 A ID = –1.5 A
0.6 TJ = 25°C 0.6 TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
3 4 5 6 7 8 2 3 4 5 6 7
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. On–Resistance vs. Gate–to–Source Figure 4. On–Resistance vs. Gate–to–Source
Voltage Voltage
0.25 1.6
ID = –3.05 A
TJ = 25°C VGS = –10 V
1.4
0.2 VGS = –4.5 V
(NORMALIZED)
1.2
0.15
1
VGS = –10 V
0.1
0.8
0.05 0.6
1 2 3 4 5 6 –50 –25 0 25 50 75 100 125 150
–ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance vs. Drain Current and Figure 6. On Resistance Variation with
Gate Voltage Temperature
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NTMD3P03R2
10000
VGS = 0 V VDS = 0 V VGS = 0 V
1200
Ciss
C, CAPACITANCE (pF)
TJ = 150°C 1000
IDSS, LEAKAGE (nA)
1000
800
Ciss
TJ = 125°C 600 Crss
100 400
Coss
200
Crss
TJ = 25°C
10 0
6 10 14 18 22 26 30 10 5 0 5 10 15 20 25 30
–VGS –VDS
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) GATE–TO–SOURCE OR DRAIN–TO–SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain–to–Source Leakage Current Figure 8. Capacitance Variation
vs. Voltage
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
12 30 1000
VDS = –24 V
QT ID = –3.05 A
10 25
VGS = –10 V
VDS
8 20 100
t, TIME (ns)
VGS td(off)
6 15 tf
Q1 tr
4 Q2 10 10
td(on)
2 5
ID = –3.05 A
TJ = 25°C
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ω)
Figure 9. Gate–to–Source and Figure 10. Resistive Switching Time Variation

Drain–to–Source Voltage vs. Total Charge vs. Gate Resistance
1000 3
VDS = –24 V VGS = 0 V
ID = –1.5 A TJ = 25°C
2.5
VGS = –4.5 V
2
t, TIME (ns)
100 1.5
tr
td(off)
tf 1
td(on)
0.5
10 0
1 10 100 0.2 0.4 0.6 0.8 1 1.2
RG, GATE RESISTANCE (Ω) –VSD, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
vs. Gate Resistance
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123
NTMD3P03R2
100
VGS = 12 V
SINGLE PULSE
1.0 ms
TC = 25°C
10
10 ms di/dt
IS
1.0 dc
trr
ta tb
0.1 TIME
RDS(on) LIMIT
THERMAL LIMIT tp 0.25 IS
PACKAGE LIMIT
0.01 IS
1 1.0 10 100
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Safe Operating Area
1.0
D = 0.5
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESPONSE
0.2
0.1
0.1
0.05 Chip Normalized to RθJA at Steady State (1″ pad)
Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω 24.4 Ω
0.02
0.01 0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F

Single Pulse Ambient
0.01
1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
t, TIME (s)
Figure 15. FET Thermal Response
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124
NTMD3P03R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

Surface mount board layout is a critical portion of the total interface between the board and the package. With the
design. The footprint for the semiconductor packages must correct pad geometry, the packages will self–align when
be the correct size to ensure proper solder connection subjected to a solder reflow process.
9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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125
NTMD3P03R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

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#$%& '(
-
N–Channel Enhancement Mode
Dual SO–8 Package http://onsemi.com
Features
• Higher Efficiency Extending Battery Life 6.0 AMPERES
• Logic Level Gate Drive 20 VOLTS
• Miniature Dual SO–8 Surface Mount Package
• Diode Exhibits High Speed, Soft Recovery
35 mW @ VGS = 4.5 V
• SO–8 Mounting Information Provided N–Channel
Applications D
• DC–DC Converters
Computers, Printers, Cellular and Cordless Telephones and PCMCIA G
Cards
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) S
Drain–to–Source Voltage VDSS 20 V
Drain–to–Gate Voltage (RGS = 1.0 MW) VDGR 20 V 8
Gate–to–Source Voltage – Continuous VGS "12 V
1
Junction–to–Ambient (Note 1.) RθJA 62.5 °C/W SO–8
Total Power Dissipation @ TA = 25°C PD 2.0 W CASE 751
Continuous Drain Current @ TA = 25°C ID 6.5 A STYLE 11
Continuous Drain Current @ TA = 70°C ID 5.5 A
Pulsed Drain Current (Note 4.) IDM 20 A
MARKING DIAGRAM
Thermal Resistance – & PIN ASSIGNMENT
1 8
Total Power Dissipation @ TA = 25°C PD 1.22 W Source 1 Drain 1
Continuous Drain Current @ TA = 25°C ID 5.07 A 2 7
Gate 1 E6N02 Drain 1
Continuous Drain Current @ TA = 70°C ID 4.07 A 3 6
Pulsed Drain Current (Note 4.) IDM 16 A Source 2 LYWW Drain 2
4 5
Gate 2 Drain 2
Junction–to–Ambient (Note 3.) RθJA 172 °C/W (Top View)
E6N02 = Device Code
L = Assembly Location
Y = Year
1. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single WW = Work Week
sided), t < 10 seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single
sided), t = steady state. ORDERING INFORMATION
3. Minimum FR–4 or G–10 PCB, t = steady state.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Device Package Shipping
NTMD6N02R2 SO–8 2500/Tape & Reel

November, 2000 – Rev. 0 NTMD6N02R2/D
NTMD6N02R2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (continued)

Operating and Storage Temperature Range TJ, Tstg –55 to +150 °C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 20 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering Purposes for 10 seconds TL 260 °C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 5.)
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25°C) – – 1.0
Gate–Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc
Gate–Body Leakage Current (VGS = –12 Vdc, VDS = 0 Vdc) IGSS – – –100 nAdc
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) 0.6 0.9 1.2
(VGS = 4.5 Vdc, ID = 6.0 Adc) – 0.028 0.035
(VGS = 4.5 Vdc, ID = 4.0 Adc) – 0.028 0.043
(VGS = 2.7 Vdc, ID = 2.0 Adc) – 0.033 0.048
(VGS = 2.5 Vdc, ID = 3.0 Adc) – 0.035 0.049
Forward Transconductance (VDS = 12 Vdc, ID = 3.0 Adc) gFS – 10 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 260 450
f = 1.0 MHz)

VGS = 4
4.55 Vdc
Vdc,
VGS = 4
4.55 Vdc
Vdc,
(VDS = 16 Vdc,
Gate–Source Charge VGS = 4.5 Vdc, Qgs – 1.5 –
ID = 6.0
6 0 Ad
Adc))
5. Handling precautions to protect against electrostatic discharge is mandatory
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128
NTMD6N02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (continued) (Note 8.)
Diode Forward On–Voltage (IS = 4.0 Adc, VGS = 0 Vdc) VSD – 0.83 1.1 Vdc
(IS = 6.0 Adc, VGS = 0 Vdc) – 0.88 1.2
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.75 –
(IS = 6.0
6 0 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 15 –
dIS/dt = 100 A/µs)
tb – 15 –
12 12
10 V 2.5 V 2.0 V
VDS ≥ 10 V

10 4.5 V 10
TJ = 25°C
3.2 V
8 8
1.8 V
6 6
4 25°C
4 100°C
2 VGS = 1.5 V 2 TJ = –55°C
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 0.5 1 1.5 2 2.5

R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.07 0.05
ID = 6.0 A TJ = 25°C
0.06
TJ = 25°C
0.04
0.05
VGS = 2.5 V
0.04
0.03 4.5 V
0.03
0.02
0.02
0.01
0 0.01
0 2 4 6 8 10 1 3 5 7 9 11 13
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Figure 4. On-Resistance versus Drain Current

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129
NTMD6N02R2
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

1.6 1000
VGS = 0 V
ID = 6.0 A TJ = 125°C
1.4 VGS = 4.5 V 100
I DSS , LEAKAGE (nA)

100°C
1.2 10
(NORMALIZED)
1 1 25°C
0.8 0.1
0.6 0.01
–50 –25 0 25 50 75 100 125 150 4 8 12 16 20
Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage Current

Temperature versus Voltage
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)

2500 5 20
V DS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VDS = 0 V VGS = 0 V QT
TJ = 25°C
2000 Ciss 4 16
C, CAPACITANCE (pF)
VDS
VGS
1500 3 12
Crss
ID = 6 A
1000 Q1 Q2 VDS = 16 V
2 8
Ciss VGS = 4.5 V
TJ = 25°C
500 1 4
Coss
Crss
0 0 0
10 5 0 5 10 15 20 0 4 8 12 16
VGS VDS Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
VDS = 16 V
ID = 6.0 A
VGS = 4.5 V
t, TIME (ns)
100
tf
tr
td(off)
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
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NTMD6N02R2
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
5 100
VGS = 12 V
I S, SOURCE CURRENT (AMPS)
VGS = 0 V
I D , DRAIN CURRENT (AMPS)

SINGLE PULSE
1 ms
4 TJ = 25°C TC = 25°C
10
3
10 ms
2
1
1 RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT dc
0 0.1
0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current Figure 11. Maximum Rated Forward Biased
Safe Operating Area
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
Figure 12. Diode Reverse Recovery Waveform
1
D = 0.5
0.2
THERMAL RESISTANCE
0.1
0.1
0.05
0.02 *0

θ,' " ('
θ,
0.01
- .
/
0.01

/
'
'
'# ,*0 " *0
θ,'
SINGLE PULSE - - " '&'#
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
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NTMD6N02R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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132
NTMD6N02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C
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133
#
Preferred Device
#$%& '(

P–Channel SO–8, Dual
Features
• Miniature Dual SO–8 Surface Mount Package 6 AMPERES
20 VOLTS
• SO–8 Mounting Information Provided RDS(on) = 33 mW
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: P–Channel
Cellular and Cordless Telephones and PCMCIA Cards
D
G
Thermal Resistance – S
Continuous Drain Current @ TA = 25°C ID –7.8 A MARKING
Continuous Drain Current @ TA = 70°C ID –5.7 A DIAGRAM
Maximum Operating Power Dissipation PD 0.5 W
Maximum Operating Drain Current ID –3.89 A
Pulsed Drain Current (Note 4.) IDM –40 A
SO–8, Dual
CASE 751 E6P02
Junction–to–Ambient (Note 2.) RθJA 98 °C/W STYLE 11 LYWW
1
Continuous Drain Current @ TA = 25°C ID –6.2 A
E6P02 = Device Code
L = Location Code
Y = Year
WW = Work Week
Total Power Dissipation @ TA = 25°C PD 0.75 W PIN ASSIGNMENT
Continuous Drain Current @ TA = 70°C ID –3.5 A Source–1 1 8 Drain–1
Maximum Operating Power Dissipation PD 0.2 W Gate–1 2 7 Drain–1
Pulsed Drain Current (Note 4.) IDM –30 A Source–2 3 6 Drain–2
1. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single Gate–2 4 5 Drain–2
sided), t = 10 seconds. Top View
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single
3. Minimum FR–4 or G–10 PCB, t = steady state. ORDERING INFORMATION
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
NTMD6P02R2 SO–8 2500 Tape & Reel
Preferred devices are recommended choices for future use

and best overall value.

November, 2000 – Rev. 1 NTMD6P02R2/D
NTMD6P02R2

(VDD = –20 Vdc, VGS = –5.0 Vdc, Peak IL = –5.0 Apk, L = 40 mH, RG = 25 Ω)
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
Temperature Coefficient (Positive) – –11.6 – mV/°C
(VGS = –12 Vdc, VDS = 0 Vdc) – – –100
(VGS = +12 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.6 –0.88 –1.20
(VGS = –4.5 Vdc, ID = –6.2 Adc) – 0.027 0.033
(VGS = –2.5 Vdc, ID = –5.0 Adc) – 0.038 0.050
(VGS = –2.5 Vdc, ID = –3.1 Adc) – 0.038 –
Forward Transconductance (VDS = –10 Vdc, ID = –6.2 Adc) gFS – 15 – Mhos
Output Capacitance 16 Vdc,
(VDS = –16 Vd VGS = 0 Vdc,
Vd
Coss – 515 775
f = 1.0 MHz)
10 Vdc,
VGS = –10 Vdc
VGS = –4.5
4 5 Vdc,
Vdc
(VDS = –16 Vdc,
Gate–Source Charge VGS = –4.5 Vdc, Qgs – 4.0 –
ID = –6.2
6 2 Ad
Adc))
http://onsemi.com
135
NTMD6P02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (continued) (Note 8.)
BODY–DRAIN DIODE RATINGS (Note 9..)
(IS = –1.7 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.65 –
(IS = –6.2 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.80 –
Reverse Recovery Time trr – 50 80 ns
(IS = –1.7
1 7 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
dIS/dt = 100 A/µs)
tr – 30 –
12 10
–10 V –4.5 V –2.1 V
VDS ≥ –10 V

–3.8 V
10
8.0
TJ = 25°C
8.0
–3.1 V 6.0
6.0 –2.5 V
–1.8 V 25°C
4.0
4.0
100°C
TJ = –55°C
2.0
2.0 –1.5 V
VGS = –1.3 V
0 0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 0 1.0 1.5 2.0 2.5

RDS(on), DRAIN–TO–SOURCE RESISTANCE (W)
0.05 0.05
ID = –6.2 A TJ = 25°C
0.04 TJ = 25°C
0.04 VGS = –2.5 V
–2.7 V
0.03
0.03 –4.5 V
0.02
0.02
0.01
0 0.01
0 2.0 4.0 6.0 8.0 10 0 2.0 4.0 6.0 8.0 10 12 14

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136
NTMD6P02R2

1.6 1000
VGS = 0 V
TJ = 125°C
ID = –6.2 A
1.4 VGS = –4.5 V 100
–I DSS , LEAKAGE (nA)

100°C
(NORMALIZED)
1.2 10
1 1
25°C
0.8 0.1
0.6 0.01
–50 –25 0 25 50 75 100 125 150 4 8 12 16 20


5000 5 20
4500 TJ = 25°C
4000 Ciss 4 16
C, CAPACITANCE (pF)
VDS
3500 VGS
3000 3 Q1 Q2 12
2500 Crss
2000 2 8
1500 Ciss ID = –6.2 A
VDS = –16 V
1000 1 VGS = –4.5 V 4
Coss
500 Crss TJ = 25°C
0 0 0
10 5.0 0 5.0 10 15 20 0 5.0 10 15 20 25
Figure 8. Gate–To–Source and Drain–To–Source

Figure 7. Capacitance Variation
1000 1000
VDD = –16 V VDD = –16 V
ID = –1.0 A ID = –6.2 A
VGS = –10 V td(off) VGS = –4.5 V
tf
t, TIME (ns)
t, TIME (ns)
100 100
tf
tr tr
td(off)
td(on)
td(on)
10 10
1 10 100 1 10 100
RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation Figure 10. Resistive Switching Time Variation
versus Gate Resistance versus Gate Resistance
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137
NTMD6P02R2
5 100
VGS = 2.5 V
VGS = 0 V SINGLE PULSE
–ID , DRAIN CURRENT (AMPS)

TC = 25°C 1.0 ms
4 TJ = 25°C
10
3
10 ms
2
1
1 RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT dc
0 0.1
0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Safe Operating Area
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
10
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.05
θ
0.02 2%* :$ Ω : Ω #:9 Ω $::9 Ω :89 Ω
0.01
Rthja(t)
0.01
$6 . 8$6 . 4:6 . :87 . :$$ .
SINGLE PULSE +%1'
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
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138
NTMD6P02R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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139
NTMD6P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C
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140
"
#$%& '(
)- 213
2#13
Complementary SO–8
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Rating Symbol N P Unit 9.5 AMPERES, 20 VOLTS
Drain–to–Source Voltage VDSS 20 –20 Vdc RDS(on) = 24 mW (N–Channel)
Gate–to–Source Voltage VGS ±20 ±12 Vdc 4 AMPERES, 20 VOLTS
Drain Current – Continuous ID 7.0 4.5 A RDS(on) = 108 mW (P–Channel)
(Note 1.)
Operating and Storage TJ, Tstg –55 to +150 °C N–Channel P–Channel
Temperature Range
D D
Thermal Resistance (Note 2.) °C/W
– Junction–to–Ambient RθJA 50 50
1. Mounted on 1″ square FR–4 board.
2. Mounted on 1″ square FR–4 board, t ≤ 10 seconds.
G G
S S
MARKING
DIAGRAM
SO–8
NTMDC02
8 CASE 751 YWW
STYLE 20
1
NTMDC02 = Device Code

Y = Year
WW = Work Week
PIN ASSIGNMENT
Source (N) 1 8 Drain

Gate (N) 2 7 Drain
Source (P) 3 6 Drain
Gate (P) 4 5 Drain
Top View
NTMD7C02R2 SO–8 2500 Units/Rail

January, 2001 – Rev. 0 NTMD7C02/D
NTMD7C02
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Polarity Min Typ Max Unit
OFF CHARACTERISTICS
(VDS = 20 Vdc, VGS = 0 Vdc) (N) – – 1.0
(VDS = 20 Vdc, VGS = 0 Vdc) (P) – – 1.0
(VGS = 20 Vdc, VDS = 0 Vdc) (N) – – 100
(VGS = 12 Vdc, VDS = 0 Vdc) (P) – – 100
(VDS = VGS, ID = 250 µAdc) (N) 1.0 – –
(VDS = VGS, ID = 250 µAdc) (P) 0.6 – –
Static Drain–to–Source On–State Resistance RDS(on) mOhms
(VGS = 4.5 Vdc, ID = 7.0 Adc) (N) – 19 24
(VGS = 4.5 Vdc, ID = 4.5 Adc) (P) – 63 74
(VGS = 2.5 Vdc, ID = 3.5 Adc) (P) – 94 108
Input Capacitance Ciss (N) – 1470 1750 pF
(P) – 500 570
Vdc,
Coss (N) – 660 770
VGS = 0 Vdc,
(P) – 190 220
f = 1.0 MHz)
Transfer Capacitance Crss (N) – 189 260
(P) – 58 80
Turn–On Delay Time td(on) (N) – 22 30 ns
(P) – 12 20
Rise Time (VDD = 10 Vdc, tr (N) – 38 50
ID = 1.0 Adc, (P) – 22 30
Turn–Off Delay Time VGS = 4.5 Vdc, td(off) (N) – 38 50
RG = 6.0 Ω) (P) – 36 50
Fall Time tf (N) – 31 45
(P) – 24 35
Gate Charge QT (N) – 16 20 nC
(P) – 7.0 9.0
(VDS = 10 Vd
Vdc,
Qgs (N) – 4.5 6.0
ID = 4.5 Adc,
(P) – 0.6 1.0
VGS = 4.5 Vdc)
Qgd (N) – 7.0 9.0
(P) – 1.7 2.5
Forward On–Voltage (IS = 1.7 Adc, VGS = 0 Vdc, VSD (N) – 730 760 Vdc
(Note 3.) TJ = 25_C) (P) – 840 870
Reverse Recovery Time trr (N) – 104 160 ns
(P) – 24 36
ta (N) – 18 28
(IF = 1.7 Adc, VGS = 0 Vdc, (P) – 13.5 22
di/dt = 100 Aµs) tb (N) – 85 140
(P) – 11 20
Reverse Recovery Stored Qrr (N) – 0.082 0.12 µC
Charge (P) – 0.018 0.028
3. Pulse Test: Pulse Width = 300 µs, Duty Cycle= 2%.
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142
#

#$%& '(

P–Channel Enhancement–Mode
Single SO–8 Package http://onsemi.com
Features
• Ultra Low RDS(on) –10 AMPERES
• Logic Level Gate Drive –20 VOLTS
• Miniature SO–8 Surface Mount Package 14 mW @ VGS = –4.5 V
• SO–8 Mounting Information Provided P–Channel
Applications D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) G
Drain–to–Source Voltage VDSS –20 Vdc S
Gate–to–Source Voltage – Continuous VGS "12 Vdc
Continuous Drain Current @ 25°C ID –10 A 8
Maximum Operating Power Dissipation PD 0.6 W 1
Pulsed Drain Current (Note 3.) IDM –50 A SO–8
Thermal Resistance – CASE 751
Junction–to–Ambient (Note 2.) RθJA 80 °C/W STYLE 12
Continuous Drain Current @ 25°C ID –8.8 A MARKING DIAGRAM
Continuous Drain Current @ 70°C ID –6.4 A & PIN ASSIGNMENT
Maximum Operating Drain Current ID –4.5 A 1 8
Source Drain
Pulsed Drain Current (Note 3.) IDM –44 A 2 7
Operating and Storage TJ, Tstg –55 to °C Source E10P02 Drain
3 LYWW 6
Temperature Range +150 Source Drain
4 5
Single Pulse Drain–to–Source Avalanche EAS 500 mJ Gate Drain
(VDD = –20 Vdc, VGS = –4.5 Vdc, Top View
Peak IL = 5.0 Apk, L = 40 mH,
RG = 25 Ω) E10P02 = Device Code
Maximum Lead Temperature for Soldering TL 260 °C Y = Year
Purposes, 1/8″ from case for 10 seconds WW = Work Week
1. Mounted onto a 2″ square FR–4 Board (1″ sq. Cu 0.06″ thick single sided),
t = 10 seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. Cu 0.06″ thick single sided),
t = steady state.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%. Device Package Shipping
reserves the right to change or discontinue this product without notice. NTMS10P02R2 SO–8 2500/Tape & Reel

December, 2000 – Rev. 2 NTMS10P02R2/D
NTMS10P02R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = –12 Vdc, VDS = 0 Vdc) – – –100
(VGS = +12 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.6 –0.88 –1.20
(VGS = –4.5 Vdc, ID = –10 Adc) – 0.012 0.014
(VGS = –2.5 Vdc, ID = –8.8 Adc) – 0.017 0.020
Forward Transconductance (VDS = –10 Vdc, ID = –10 Adc) gFS – 30 – Mhos
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 1100 1670
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Notes 5. & 6.)

VGS = –4.5
4 5 Vdc,
Vdc
Rise Time (VDD = –10 Vdc, ID = –10 Adc, tr – 100 –
4 5 Vdc,
VGS = –4.5 Vdc
(VDS = –10 Vdc,
ID = –10
10 Ad
Adc))
Gate–Drain Charge Qgd – 17 –
(IS = –2.1 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.60 –
Diode Forward On–Voltage (IS = –10 Adc, VGS = 0 Vdc) VSD – –0.90 – Vdc
(IS = –10 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.75 –
(IS = –2.1
2 1 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 25 –
dIS/dt = 100 A/µs)
tb – 40 –
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144
NTMS10P02R2
20 10
–2.3 V –2.1 V
VDS ≥ –10 V
8.0

15 TJ = 25°C
–10 V
–3.1 V 6.0
–1.9 V
10
25°C
4.0
5.0 VGS = –1.7 V

100°C TJ = –55°C
2.0
0 0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 0.5 1.0 1.5 2.0 2.5

0.100 0.020
TJ = 25°C VGS = –2.5 V
ID = –10 A
TJ = 25°C
0.075
0.016
0.050
VGS = –4.5 V
0.012
0.025
0 0.008
0 2.0 4.0 6.0 8.0 10 6.0 10 14 18


<
1.6 10,000
VGS = 0 V
ID = –10 A
1.4 VGS = –4.5 V

1000 TJ = 125°C
1.2
1.0 TJ = 100°C
100
0.8
0.6 10
–50 –25 0 25 50 75 100 125 150 2.0 6.0 10 14 18

http://onsemi.com
145
NTMS10P02R2
10,000
VGS = 0 V VDS = 0 V
TJ = 25°C
8000 Ciss
C, CAPACITANCE (pF)
6000
Crss
4000
Ciss
2000
Coss
Crss
0
10 5.0 0 5.0 10 15 20
–VGS –VDS

–VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)

5.0 10
QT
4.0 VGS 8.0

VDS
3.0 6.0
Q1 Q2
2.0 4.0
ID = –10 A
1.0 TJ = 25°C 2.0
Q3
0 0
0 10 20 30 40 50
Qg, TOTAL GATE CHARGE (nC)
1000 1000
VDD = –10 V td(off) VDD = –10 V
td(off)
ID = –1.0 A tf ID = –10 A
VGS = –4.5 V VGS = –4.5 V
tr
t, TIME (ns)
t, TIME (ns)
tr tf
100 100
td(on)
td(on)
10 10
1.0 10 100 1.0 10 100
http://onsemi.com
146
NTMS10P02R2
100
2.0
VGS = 0 V
–ID , DRAIN CURRENT (AMPS)

TJ = 25°C 100 ms
1.6
10 1.0 ms
1.2
VGS = 2.5 V 10 ms
SINGLE PULSE
0.8 1.0 TC = 25°C
0.4 RDS(on) LIMIT

THERMAL LIMIT
PACKAGE LIMIT dc
0 0.1
0.50 0.55 0.60 0.65 0.70 0.1 1.0 10 100
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Safe Operating Area
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
10
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1.0 D = 0.5
0.2
0.1
0.1
0.05
θ
0.02 2%* 94 Ω 9$# Ω 788 Ω 96 Ω 7$# Ω
0.01
Rthja(t)
0.01
4: . 998 . $$6 . 764: . :#69 .
+%1'
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
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NTMS10P02R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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148
NTMS10P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
149
!#!

#$%& '(
!- !
P–Channel SO–8
Features
http://onsemi.com
• High Efficiency Components in a Single SO–8 Package
• High Density Power MOSFET with Low RDS(on)
• Miniature SO–8 Surface Mount Package – Saves Board Space –3.05 AMPERES
• Diode Exhibits High Speed with Soft Recovery –30 VOLTS
0.085 W @ VGS = –10 V
• Mounting Information for the SO–8 Package is Provided
P–Channel
Applications
• DC–DC Converters D
G
Rating Symbol Value Unit S
Gate–to–Source Voltage – Continuous VGS ±20 V MARKING
DIAGRAM
SO–8 E3P03
CASE 751 LYWW
Continuous Drain Current @ 70°C ID –1.87 A 8
STYLE 13
Total Power Dissipation @ TA = 25°C PD 1.25 W E3P03 = Device Code
Continuous Drain Current @ 25°C ID –3.05 A L = Assembly Location
Continuous Drain Current @ 70°C ID –2.44 A Y = Year
Pulsed Drain Current (Note 4.) IDM –12 A WW = Work Week
PIN ASSIGNMENT
N.C. 1 8 Drain
Pulsed Drain Current (Note 4.) IDM –15 A Source 2 7 Drain
Operating and Storage TJ, Tstg –55 to °C Source 3 6 Drain
Temperature Range +150 4 5
Gate Drain
(VDD = –30 Vdc, VGS = –4.5 Vdc, Peak
IL = –7.5 Apk, L = 5 mH, RG = 25 Ω) ORDERING INFORMATION
Purposes, 1/8″ from case for 10 seconds Device Package Shipping
1. Minimum FR–4 or G–10 PCB, t = Steady State. NTMS3P03R2 SO–8 2500/Tape & Reel
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single This document contains information on a product under
sided), t ≤ 10 seconds. development. ON Semiconductor reserves the right to
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. change or discontinue this product without notice.

January, 2001 – Rev. 0 NTMS3P03R2/D
NTMS3P03R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –30 – –
(VGS = –20 Vdc, VDS = 0 Vdc) – – –100
(VGS = +20 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –1.0 –1.7 –2.5
(VGS = –10 Vdc, ID = –3.05 Adc) – 0.063 0.085
(VGS = –4.5 Vdc, ID = –1.5 Adc) – 0.090 0.115
24 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 170 325
f = 1.0 MHz)

VGS = –10
10 Vdc
Vdc,
4 5 Vdc,
VGS = –4.5 Vdc
(VDS = –24 Vdc,
ID = –3.05
3 05 Adc)
Ad )
(IS = –3.05 Adc, VGS = 0 V, TJ = 125°C) – –0.78 –
(IS = –3.05
3 05 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 18 –
dIS/dt = 100 A/µs)
tb – 16 –
http://onsemi.com
151
NTMS3P03R2
6 6
VGS = –10 V
VGS = –4.4 V VDS > = –10 V

5 VGS = –8 V 5
VGS = –4 V
VGS = –6 V
VGS = –4.6 V
4 4
TJ = 25°C VGS = –4.8 V TJ = 100°C
3 VGS = –3.6 V 3
VGS = –2.8 V
VGS = –3.2 V TJ = 25°C
2 VGS = –5 V 2
VGS = –3 V TJ = –55°C
VGS = –2.6 V
1 1
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 2 3 4 5


0.7 0.7
ID = –3.05 A ID = –1.5 A
0.6 TJ = 25°C 0.6 TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
3 4 5 6 7 8 2 3 4 5 6 7
Voltage Voltage
0.25 1.6
ID = –3.05 A
TJ = 25°C VGS = –10 V
1.4
0.2 VGS = –4.5 V
(NORMALIZED)
1.2
0.15
1
VGS = –10 V
0.1
0.8
0.05 0.6
1 2 3 4 5 6 –50 –25 0 25 50 75 100 125 150
http://onsemi.com
152
NTMS3P03R2
10000
1200
Ciss
C, CAPACITANCE (pF)
TJ = 150°C 1000
IDSS, LEAKAGE (nA)
1000
800
600 Crss Ciss

TJ = 125°C
100 400
Coss
200
Crss
TJ = 25°C
10 0
6 10 14 18 22 26 30 10 5 0 5 10 15 20 25 30
–VGS –VDS
VOLTAGE (VOLTS)
vs. Voltage
12 30 1000
VDS = –24 V
QT ID = –3.05 A
10 25
VGS = –10 V
VDS
8 20 100
td(off)
t, TIME (ns)
VGS
6 15 tf
Q1 tr
4 Q2 10 10
td(on)
2 5
ID = –3.05 A
TJ = 25°C
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

1000 3
VDS = –24 V VGS = 0 V
ID = –1.5 A TJ = 25°C
2.5
VGS = –4.5 V
2
t, TIME (ns)
100 1.5
tr
td(off)
tf 1
td(on)
0.5
10 0
1 10 100 0.2 0.4 0.6 0.8 1 1.2
RG, GATE RESISTANCE (Ω) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
vs. Gate Resistance
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153
NTMS3P03R2
100
VGS = 12 V
SINGLE PULSE
1.0 ms
TA = 25°C
10
10 ms di/dt
IS
1.0 dc
trr
ta tb
0.1 TIME
RDS(on)
PACKAGE LIMIT
0.01 IS
0.1 1.0 10 100
Safe Operating Area
1.0
D = 0.5
THERMAL RESPONSE
0.2
0.1
0.1
Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω 24.4 Ω
0.02
0.01 0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F

0.01
1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
t, TIME (s)
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154
NTMS3P03R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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155
NTMS3P03R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
156

#$%& '(
-
N–Channel Enhancement–Mode
Single SO–8 Package
Features
• High Density Power MOSFET with Ultra Low RDS(on) Providing http://onsemi.com
Higher Efficiency
• Miniature SO–8 Surface Mount Package Saving Board Space; 4.2 AMPERES
Mounting Information for the SO–8 Package is Provided
• IDSS Specified at Elevated Temperature 20 VOLTS
• Drain–to–Source Avalanche Energy Specified 0.045 W @ VGS = 4.5 V
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: Single N–Channel
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones D

Drain–to–Source Voltage VDSS 20 V G
Drain–to–Gate Voltage (RGS = 1.0 mW) VDGR 20 V
Gate–to–Source Voltage – Continuous VGS ±10 V S
Continuous Drain Current @ 25°C ID 5.9 A
Continuous Drain Current @ 70°C ID 4.7 A
Pulsed Drain Current (Note 4.) IDM 25 A 8
Total Power Dissipation @ TA = 25°C PD 1.25 W SO–8
Continuous Drain Current @ 25°C ID 4.2 A CASE 751
Continuous Drain Current @ 70°C ID 3.3 A STYLE 13
Junction–to–Ambient (Note 3.) RθJA 162 °C/W MARKING DIAGRAM
Total Power Dissipation @ TA = 25°C PD 0.77 W & PIN ASSIGNMENT
Continuous Drain Current @ 25°C ID 3.3 A 1 8
Continuous Drain Current @ 70°C ID 2.6 A N.C. Drain
Pulsed Drain Current (Note 4.) IDM 15 A 2 7
Source E4N01 Drain
Operating and Storage TJ, Tstg –55 to °C 3
LYWW
6
Source Drain
Temperature Range +150 4 5
Single Pulse Drain–to–Source Avalanche EAS 169 mJ Gate Drain
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL
= 7.5 Apk, L = 6 mH, RG = 25 Ω) E4N01 = Device Code
Maximum Lead Temperature for Soldering TL 260 °C L = Assembly Location
Purposes, 1/8″ from case for 10 seconds Y = Year
WW = Work Week
sided), t ≤ 10 seconds.
sided), t = steady state. ORDERING INFORMATION
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Device Package Shipping
NTMS4N01R2 SO–8 2500/Tape & Reel

February, 2001 – Rev. 2 NTMS4N01R2/D
NTMS4N01R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25°C) – 0.2 –
(VGS = +10 Vdc, VDS = 0 Vdc) – – 100
(VGS = –10 Vdc, VDS = 0 Vdc) – – –100
ON CHARACTERISTICS
(VDS = VGS, ID = 250 µAdc) 0.6 0.95 1.2
(VGS = 4.5 Vdc, ID = 4.2 Adc) – 0.030 0.04
(VGS = 2.7 Vdc, ID = 2.1 Adc) – 0.035 0.05
(VGS = 2.5 Vdc, ID = 2.0 Adc) – 0.037 –
Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) gFS – 10 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 260 400
f = 1.0 MHz)

VGS = 4
4.55 Vdc
Vdc,
(VDS = 12 Vdc,
Gate–Source Charge VGS = 4.5 Vdc, Qgs – 2.0 –
ID = 4.2
4 2 Ad
Adc))

Diode Forward On–Voltage (IS = 4.2 Adc, VGS = 0 Vdc) VSD – 0.85 1.1 Vdc
(IS = 4.2 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.70 –
(IS = 4.2
4 2 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 12 –
dIS/dt = 100 A/µs)
tb – 8.0 –
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158
NTMS4N01R2
7
8V 2.1 V 1.9 V
8 VDS ≥ 10 V
6

4.5 V
3.1 V
5 TJ = 25°C
2.7 V 6
2.5 V
4 2.3 V
3 1.7 V 4
100°C
2
2 25°C
1 1.5 V TJ = –55°C
VGS = 1.3 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0.5 1 1.5 2 2.5

RDS(on), DRAIN–TO SOURCE–RESISTANCE (W)
RDS(on), DRAIN–TO SOURCE–RESISTANCE (W)

0.08 0.05
ID = 4.2 A TJ = 25°C
0.07 TJ = 25°C
0.04
VGS = 2.5 V
0.06
VGS = 2.7 V
0.05 0.03
VGS = 4.5 V
0.04
0.02
0.03
0.02 0.01
0 2 4 6 8 0 2 4 6 8 10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

1.6 10,000
VGS = 0 V
ID = 4.2 A
1.4 VGS = 4.5 V
IDSS, LEAKAGE (nA)
TJ = 150°C
1.2
1000
1
TJ = 125°C
0.8
0.6 100
–50 –25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 20

http://onsemi.com
159
NTMS4N01R2
2500
VDS = 0 V VGS = 0 V
Ciss TJ = 25°C
2000
C, CAPACITANCE (pF)
1500
Crss
1000
Ciss
500
Coss
Crss
0
8 6 4 2 0 2 4 6 8 10 12
VGS VDS

5 20

QT
4 VGS 16
VDS
3 12
Q1 Q2
2 8
ID = 4.2 A
1 TJ = 25°C 4
0 0
0 2 4 6 8 10 12
Qg, TOTAL GATE CHARGE (nC)
1000 1000
VDD = 10 V VDD = 10 V
ID = 4.2 A ID = 2.1 A
VGS = 4.5 V VGS = 4.5 V
t, TIME (ns)
t, TIME (ns)
td(off) tf
100 tf 100
td(off)
tr
tr
td(on) td(on)
10 10
1 10 100 1 10 100
http://onsemi.com
160
NTMS4N01R2
4 100
VGS = 20 V
VGS = 0 V
ID , DRAIN CURRENT (AMPS)

SINGLE PULSE 100 ms
TJ = 25°C
TC = 25°C
3 10 1.0 ms
10 ms
2 1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT dc
1 0.1
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz.
Cu 0.06″ thick single sided), 10s max.
0 0.01
0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 1 10 100
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Safe Operating Area
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
10
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
θ
0.02 2%* ## Ω # Ω #$8: Ω :#4 Ω 9894 Ω
0.01
0.01
# . #: . 4$: . 464 . 866 .
+%1'
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
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161
NTMS4N01R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
http://onsemi.com
162
NTMS4N01R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
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#

#$%& '(
-
Features
• High Density Power MOSFET with Ultra Low RDS(on)
Providing Higher Efficiency –4.5 AMPERES
• Miniature SO–8 Surface Mount Package – Saves Board Space –12 VOLTS
• Diode Exhibits High Speed with Soft Recovery
0.045 W @ VGS = –4.5 V
• Drain–to–Source Avalanche Energy Specified
• Mounting Information for the SO–8 Package is Provided Single P–Channel
Applications D
MAXIMUM RATINGS G
Please See the Table on the Following Page

S
1
SO–8
CASE 751
STYLE 13
MARKING DIAGRAM
& PIN ASSIGNMENT
1 8
N.C. Drain
2 7
Source E4P01 Drain
3 LYWW 6
Source Drain
4 5
Gate Drain
Top View
E4P01 = Device Code

Y = Year
WW = Work Week
NTMS4P01R2 SO–8 2500/Tape & Reel


February, 2001 – Rev. 0 NTMS4P01R2/D
NTMS4P01R2

Drain–to–Gate Voltage (RGS = 1.0 mW) VDGR –12 V
Gate–to–Source Voltage – Continuous VGS ±10 V
1. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state.
http://onsemi.com
165
NTMS4P01R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –12 – –
(VGS = –10 Vdc, VDS = 0 Vdc) – – –100
(VGS = +10 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.65 –0.9 –1.15
(VGS = –4.5 Vdc, ID = –4.5 Adc) – 0.030 0.045
(VGS = –2.7 Vdc, ID = –2.25 Adc) – 0.040 0.055
(VGS = –2.5 Vdc, ID = –2.25 Adc) – 0.045 –
Forward Transconductance (VDS = –2.5 Vdc, ID = –2.25 Adc) gFS – 10 – Mhos
Output Capacitance (VDS = –9.6
9 6 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 635 1000
f = 1.0 MHz)
VGS = –4.5
4 5 Vdc,
Vdc
(VDS = –9.6 Vdc,
ID = –4.5
4 5 Ad
Adc))
(IS = –4.5 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.7 –
(IS = –4.5
4 5 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
dIS/dt = 100 A/µs)
tb – 18 –
http://onsemi.com
166
NTMS4P01R2
8 –8 V
–2.3 V –2.1 V
TJ = 25°C VDS ≥ –10 V
7 8

–4.5 V
6 –3.7 V
–3.1 V
–2.7 V –1.9 V 6
5
4
–2.5 V 4
3 100°C
–1.7 V
2 25°C
2
1 TJ = –55°C
VGS = –1.3 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0.5 1 1.5 2 2.5


0.12 0.05
ID = –4.5 A
TJ = 25°C
TJ = 25°C
VGS = –2.5 V
0.09 0.04
VGS = –2.7 V
0.06 0.03
VGS = –4.5 V
0.03 0.02
0 0.01
0 2 4 6 8 2 4 6 8

1.6 10,000
VGS = 0 V
ID = –4.5 A
1.4
VGS = –4.5 V TJ = 150°C
1.2
1000
1
TJ = 125°C
0.8
0.6 100
–50 –25 0 25 50 75 100 125 150 2 4 6 8 10 12

http://onsemi.com
167
NTMS4P01R2

5 10
VDS = 0 V VGS = 0 V
4000
Ciss TJ = 25°C QT
4 8
C, CAPACITANCE (pF)
–VDS –VGS
3000
3 Q1 Q2 6
Crss
2000
Ciss 2 4
1000 ID = –4.5 A
Coss 1 2
TJ = 25°C
Crss
0 0 0
10 8 6 4 2 0 2 4 6 8 10 12 0 4 8 12 16 20 24
GATE–TO–SOURCE OR Figure 8. Gate–To–Source and Drain–To–Source

DRAIN–TO–SOURCE VOLTAGE (VOLTS) Voltage versus Total Charge
1000 4
VGS = 0 V

VDD = –12 V
ID = –4.5 A TJ = 25°C
VGS = –4.5 V 3
td(off)
tf
t, TIME (ns)
tr
100 2
td(on)
1
10 0
1 10 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
RG, GATE RESISTANCE (OHMS) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage versus Current

100
VGS = 10 V
SINGLE PULSE
TC = 25°C
10 1.0 ms
10 ms
di/dt
1 IS
RDS(on) LIMIT
THERMAL LIMIT trr
dc
PACKAGE LIMIT ta tb
0.1
Mounted on 2″ sq. FR4 board TIME
(1″ sq. 2 oz. Cu 0.06″ thick
single sided), 10s max. tp 0.25 IS
0.01
0.1 1 10 100 IS
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Safe Operating Area
http://onsemi.com
168
NTMS4P01R2
10
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
θ
0.02 2%* 94 Ω 9$# Ω 788 Ω 96 Ω 7$# Ω
0.01
0.01
4: . 998 . $$6 . 764: . :#69 .
+%1'
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

9
$#
#:$ $$
: 6
#6 $ inches

9 #: mm
http://onsemi.com
169
NTMS4P01R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
170
#

#$%& '(
-
Features
• High Density Power MOSFET with Ultra Low RDS(on)
Providing Higher Efficiency –5.4 AMPERES
• Miniature SO–8 Surface Mount Package – Saves Board Space –20 VOLTS
• Diode Exhibits High Speed with Soft Recovery
0.033 W @ VGS = –4.5 V
• Drain–to–Source Avalanche Energy Specified
• Mounting Information for the SO–8 Package is Provided Single P–Channel
Applications D
MAXIMUM RATINGS G
Please See the Table on the Following Page

S
1
SO–8
CASE 751
STYLE 13
MARKING DIAGRAM
& PIN ASSIGNMENT
1 8
N.C. Drain
2 7
Source E5P02 Drain
3 LYWW 6
Source Drain
4 5
Gate Drain
Top View
E5P02 = Device Code

Y = Year
WW = Work Week
NTMS5P02R2 SO–8 2500/Tape & Reel


February, 2001 – Rev. 0 NTMS5P02R2/D
NTMS5P02R2

Drain–to–Gate Voltage (RGS = 1.0 mW) VDGR –20 V
Gate–to–Source Voltage – Continuous VGS ±10 V
Junction–to–Ambient (Note 1) RθJA 50 °C/W
Operating and Storage TJ, Tstg –55 to +150 °C
Temperature Range
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state.
http://onsemi.com
172
NTMS5P02R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VDS = –20 Vdc, VGS = 0 Vdc, TJ = 25°C) – –0.2 –
(VGS = –10 Vdc, VDS = 0 Vdc) – – –100
(VGS = +10 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.65 –0.9 –1.25
(VGS = –4.5 Vdc, ID = –5.4 Adc) – 0.026 0.033
(VGS = –2.5 Vdc, ID = –2.7 Adc) – 0.037 0.048
Forward Transconductance (VDS = –9.0 Vdc, ID = –5.4 Adc) gFS – 15 – Mhos
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 510 900
f = 1.0 MHz)
VGS = –4.5
4 5 Vdc,
Vdc
VGS = –4.5
4 5 Vdc,
Vdc
(VDS = –16 Vdc,
ID = –5.4
5 4 Ad
Adc))

(IS = –5.4 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.72 –
(IS = –5.4
5 4 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
dIS/dt = 100 A/µs)
tb – 20 –
http://onsemi.com
173
NTMS5P02R2
12 12
–8 V –2.3 V
TJ = 25°C VDS ≥ –10 V

10 –4.5 V 10
–3.7 V –2.1 V
–3.1 V
8 8
–2.7 V
6 –2.5 V 6
–1.9 V 100°C
4 4
25°C TJ = –55°C
–1.7 V
2 2
VGS = –1.3 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 1.5 2 2.5 3


0.08 0.05
ID = –5.4 A
TJ = 25°C
TJ = 25°C VGS = –2.5 V
0.06 0.04
VGS = –2.7 V
0.04 0.03
VGS = –4.5 V
0.02 0.02
0 0.01
0 2 4 6 8 10 2 4 6 8 10 12

1.6 10,000
VGS = 0 V
ID = –5.4 A
1.4 TJ = 150°C
VGS = –4.5 V
1.2
1000
1 TJ = 125°C
0.8
0.6 100
–50 –25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 20

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174
NTMS5P02R2

5 20
4000
Ciss TJ = 25°C
4 –VGS 16
C, CAPACITANCE (pF)
–VDS
3000
3 Q1 Q2 12
Crss
2000
2 8
Ciss
ID = –5.4 A
1000 TJ = 25°C
1 4
Coss
Crss
0 0 0
10 5 0 5 10 15 20 0 4 8 12 16 20 24
GATE–TO–SOURCE OR Figure 8. Gate–To–Source and Drain–To–Source

DRAIN–TO–SOURCE VOLTAGE (VOLTS) Voltage versus Total Charge
1000
VDD = –16 V 5

VGS = 0 V
ID = –5.4 A TJ = 25°C
VGS = –4.5 V
td(off) 4
tf
t, TIME (ns)
tr
3
100
2
td(on)
1
10 0
1 10 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage versus Current

100
VGS = 20 V
SINGLE PULSE
TC = 25°C 1 ms
10
di/dt
IS
10 ms
trr
1
ta tb
RDS(on) LIMIT TIME
THERMAL LIMIT
PACKAGE LIMIT dc tp 0.25 IS
0.1
0.1 1 10 100 IS
Safe Operating Area
http://onsemi.com
175
NTMS5P02R2
10
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
θ
0.02 2%* 94 Ω 9$# Ω 788 Ω 96 Ω 7$# Ω
0.01
0.01
4: . 998 . $$6 . 764: . :#69 .
+%1'
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

9
$#
#:$ $$
: 6
#6 $ inches

9 #: mm
http://onsemi.com
176
NTMS5P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
177
#

(45
Power MOSFET and Schottky Diode
Dual SO–8 Package
Features
• High Efficiency Components in a Single SO–8 Package http://onsemi.com
• High Density Power MOSFET with Low RDS(on),
Schottky Diode with Low VF
MOSFET
• Independent Pin–Outs for MOSFET and Schottky Die –2.3 AMPERES
Allowing for Flexibility in Application Use –20 VOLTS
• Less Component Placement for Board Space Savings 90 mW @ VGS = –4.5 V
• SO–8 Surface Mount Package,
Mounting Information for SO–8 Package Provided
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: SCHOTTKY DIODE
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
2.0 AMPERES
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 20 VOLTS
580 mV @ IF = 2.0 A
Thermal Resistance – Junction–to–Ambient
(Note 1.) RθJA 175 °C/W 8
Continuous Drain Current @ TA = 25°C ID –2.3 A 8 # :

Continuous Drain Current @ TA = 100°C ID –1.45 A 9
Pulsed Drain Current (Note 4.) IDM –9.0 A 1
4
Thermal Resistance – Junction–to–Ambient SO–8
6 $
(Note 2.) RθJA 105 °C/W CASE 751
Total Power Dissipation @ TA = 25°C PD 1.19 W STYLE 18 /
MARKING DIAGRAM
Thermal Resistance – Junction–to–Ambient & PIN ASSIGNMENTS
(Note 3.) RθJA 62.5 °C/W
Total Power Dissipation @ TA = 25°C PD 2.0 W 1 8
Continuous Drain Current @ TA = 25°C ID –3.85 A Anode Cathode
2 7
Continuous Drain Current @ TA = 100°C ID –2.43 A Anode E2P102 Cathode
Source LYWW Drain
Operating and Storage TJ, Tstg –55 to °C 4 5
Gate Drain
(Top View)
Energy – Starting TJ = 25°C E2P102 = Device Code
(VDD = –20 Vdc, VGS = –4.5 Vdc, Peak IL L = Assembly Location
= –5.0 Apk, L = 28 mH, RG = 25 Ω) Y = Year
Maximum Lead Temperature for Soldering TL 260 °C WW = Work Week
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single ORDERING INFORMATION
sided), Steady State.
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single Device Package Shipping
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. NTMSD2P102LR2 SO–8 2500/Tape & Reel

December, 2000 – Rev. 1 NTMSD2P102LR2/D
NTMSD2P102LR2
SCHOTTKY MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Peak Repetitive Reverse Voltage VRRM 20 V
DC Blocking Voltage VR
Average Forward Current (Note 5.) IO 1.0 A
(Rated VR, TA = 100°C)
Peak Repetitive Forward Current IFRM 2.0 A
(Note 5.) (Rated VR, Square Wave, 20 kHz, TA = 105°C)
Non–Repetitive Peak Surge Current (Note 5.) IFSM 20 A
(Surge Applied at Rated Load Conditions, Half–Wave, Single Phase, 60 Hz)

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = –10 Vdc, VDS = 0 Vdc) – – –100
(VGS = +10 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.5 –0.90 –1.5
(VGS = –4.5 Vdc, ID = –2.4 Adc) – 0.070 0.090
(VGS = –2.7 Vdc, ID = –1.2 Adc) – 0.100 0.130
(VGS = –2.5 Vdc, ID = –1.2 Adc) – 0.110 0.150
Forward Transconductance gFS Mhos
(VDS = –10 Vdc, ID = –1.2 Adc) – 4.2 –
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 200 300
f = 1.0 MHz)
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179
NTMSD2P102LR2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) (Note 7.)
4 5 Vdc,
VGS = –4.5 Vdc
VGS = –2.7
2 7 Vdc,
Vdc
(VDS = –16 Vdc,
ID = –2.4
2 4 Ad
Adc))

(IS = –2.4 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.75 –
(IS = –2.4
2 4 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 16 –
dIS/dt = 100 A/µs)
tb – 21 –
SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 8.)
g
Maximum Instantaneous Forward Voltage VF TJ = 25°C TJ = 125°C Volts
IF = 1.0
1 0 Ad
Adc
0.47 0.39
IF = 2.0 Adc
0.58 0.53
Maximum Instantaneous Reverse Current IR TJ = 25°C TJ = 125°C mA

Vd
VR = 20 Vdc
0.05 10
Maximum Voltage Rate of Change VR = 20 Vdc dV/dt 10,000 V/ms
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NTMSD2P102LR2
4 5
VGS = –2.1 V TJ = 25°C
VDS > = –10 V

VGS = –10 V
4
3 VGS = –4.5 V
VGS = –1.9 V
VGS = –2.5 V
3
2
VGS = –1.7 V 2 TJ = 25°C
1
VGS = –1.5 V 1
TJ = 100°C
TJ = 55°C
0 0
0 2 4 6 8 10 1 1.5 2 2.5 3
Figure 1. On–Region Characteristics. Figure 2. Transfer Characteristics.


0.2 0.12
TJ = 25°C TJ = 25°C
0.15 0.1
VGS = –2.7 V
0.1 0.08
VGS = –4.5 V
0.05 0.06
0 0.04
2 4 6 8 1 1.5 2 2.5 3 3.5 4 4.5
Voltage. Gate Voltage.
1.6 1000
ID = –2.4 A VGS = 0 V
VGS = –4.5 V TJ = 125°C

1.4 100
TJ = 100°C
1.2 10
TJ = 25°C
1 1
0.8 0.1
0.6 0.01
–50 –25 0 25 50 75 100 125 150 0 4 8 12 16 20

Temperature. vs. Voltage.
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NTMSD2P102LR2

1500 5 20
VDS = 0 V VGS = 0 V
QT 18
1200 Ciss TJ = 25°C 4 16
C, CAPACITANCE (pF)
14
900 3 VGS 12
Crss
Q1 10
Q2
600 Ciss 2 8
6
300 ID = –2.4 A
Coss 1 VDS 4
TJ = 25°C
Crss 2
0 0 0
10 5 0 5 10 15 20 0 2 4 6 8 10 12 14
Figure 8. Gate–to–Source and
VOLTAGE (VOLTS) Drain–to–Source Voltage versus Total Charge
1000 100
VDD = –10 V td (off)
ID = –1.2 A
VGS = –2.7 V tr tf
t, TIME (ns)
t, TIME (ns)
td
100 10 (on)
tr
tf
td (off) VDD = –10 V
ID = –2.4 A
VGS = –4.5 V
td (on)
10 1.0
1.0 10 100 1.0 10 100
2
VGS = 0 V
TJ = 25°C di/dt
1.6
IS
trr
1.2
ta tb
TIME
0.8
tp 0.25 IS
0.4 IS
0
0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 12. Diode Reverse Recovery Waveform
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage

versus Current
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NTMSD2P102LR2
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
D = 0.5
0.2
Normalized to R∅ja at Steady State (1 inch pad)

0.1 0.1
0.0125 Ω 0.0563 Ω 0.110 Ω 0.273 Ω 0.113 Ω 0.436 Ω
0.05
0.02
0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F
Single Pulse
0.01
1E–03 1E–02 1E–01 1E+00 1E+03 1E+02 1E+03
t, TIME (s)
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
10 10
IF, INSTANTANEOUS FORWARD
TJ = 125°C
CURRENT (AMPS)
CURRENT (AMPS)
TJ = 125°C
85°C
1.0 1.0
85°C 25°C
25°C
–40°C
0.1 0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS) VF, MAXIMUM INSTANTANEOUS
FORWARD VOLTAGE (VOLTS)
Figure 14. Typical Forward Voltage Figure 15. Maximum Forward Voltage
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NTMSD2P102LR2
1E–2
IR, MAXIMUM REVERSE CURRENT (AMPS)

1E–1
IR , REVERSE CURRENT (AMPS)
TJ = 125°C
TJ = 125°C
1E–3 1E–2
85°C
1E–4 1E–3
1E–5 1E–4
25°C
25°C
1E–6 1E–5
1E–7 1E–6
0 5.0 10 15 20 0 5.0 10 15 20
VR, REVERSE VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS)
Figure 16. Typical Reverse Current Figure 17. Maximum Reverse Current
IO, AVERAGE FORWARD CURRENT (AMPS)

1000 1.6
TYPICAL CAPACITANCE AT 0 V = 170 pF dc
1.4 FREQ = 20 kHz
C, CAPACITANCE (pF)
1.2 SQUARE WAVE
1.0
Ipk/Io = p
100 0.8
Ipk/Io = 5.0
0.6
Ipk/Io = 10
0.4
Ipk/Io = 20
0.2
10 0
0 5.0 10 15 20 0 20 40 60 80 100 120 140 160
VR, REVERSE VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)
Figure 18. Typical Capacitance Figure 19. Current Derating

PFO, AVERAGE POWER DISSIPATION (WATTS)
0.7
SQUARE dc
0.6 WAVE
Ipk/Io = p
0.5
Ipk/Io = 5.0
0.4 Ipk/Io = 10
Ipk/Io = 20
0.3
0.2
0.1
0
0 0.5 1.0 1.5 2.0
Figure 20. Forward Power Dissipation
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184
NTMSD2P102LR2
1.0
D = 0.5
0.2
THERMAL RESISTANCE
0.1
0.1
0.05 NORMALIZED TO RqJA AT STEADY STATE (1″ PAD)
0.02
0.01 4 W $6 W $# W 6$:$ W 4:7 W

0.01 , 6 . 8# . $# . #:6 . $896 .
SINGLE PULSE
=
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
Figure 21. Schottky Thermal Response
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NTMSD2P102LR2

9
$#
#:$ $$
: 6
inches
mm
#6 $
9 #:
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186
NTMSD2P102LR2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

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!#

(45
Dual SO–8 Package
http://onsemi.com
Features
• High Density Power MOSFET with Low RDS(on), MOSFET
Schottky Diode with Low VF –3.05 AMPERES
• Independent Pin–Outs for MOSFET and Schottky Die
• Less Component Placement for Board Space Savings 0.085 W @ VGS = –10 V
Applications SCHOTTKY DIODE
• DC–DC Converters 1.0 AMPERES
20 VOLTS
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones 470 mV @ IF = 1.0 A

Drain–to–Source Voltage VDSS –20 V 8 # :

Gate–to–Source Voltage – Continuous VGS "20 V 9
1
SO–8 6 $
CASE 751
Continuous Drain Current @ TA = 25°C ID –2.34 A /
STYLE 18
Thermal Resistance – MARKING DIAGRAM
Junction–to–Ambient (Note 2.) RθJA 100 °C/W & PIN ASSIGNMENTS
1 8
Continuous Drain Current @ TA = 70°C ID –2.44 A 2 7
Anode E3P102 Cathode
Source LYWW Drain
Thermal Resistance – 4 5
Junction–to–Ambient (Note 3.) RθJA 62.5 °C/W Gate Drain
Total Power Dissipation @ TA = 25°C PD 2.0 W (Top View)
Continuous Drain Current @ TA = 70°C ID –3.10 A E3P102 = Device Code
Pulsed Drain Current (Note 4.) IDM –15 A L = Assembly Location
Operating and Storage TJ, Tstg –55 to °C Y = Year
Temperature Range +150 WW = Work Week
Energy – Starting TJ = 25°C (VDD = ORDERING INFORMATION
–20 Vdc, VGS = –4.5 Vdc, Peak IL =
–7.5 Apk, L = 5 mH, RG = 25 Ω) Device Package Shipping
Purposes, 1/8″ from case for 10 seconds NTMSD3P102R2 SO–8 2500/Tape & Reel
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), Steady State.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

January, 2001 – Rev. 0 NTMSD3P102R2/D
NTMSD3P102R2

Thermal Resistance – Junction–to–Ambient (Note 5.) RθJA 204 °C/W
Peak Repetitive Forward Current IFRM 2.0 A
(Note 7.) (Rated VR, Square Wave, 20 kHz, TA = 105°C)

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = –20 Vdc, VDS = 0 Vdc) – – –100
(VGS = +20 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –1.0 –1.7 –2.5
(VGS = –10 Vdc, ID = –3.05 Adc) – 0.063 0.085
(VGS = –4.5 Vdc, ID = –1.5 Adc) – 0.090 0.125
(VDS = –15 Vdc, ID = –3.05 Adc) – 5.0 –
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 190 350
f = 1.0 MHz)
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NTMSD3P102R2

10 Vdc,
VGS = –10 Vdc
VGS = –4.5
4 5 Vdc,
Vdc
(VDS = –20 Vdc,
ID = –3.05
3 05 Adc)
Ad )

(IS = –3.05 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.78 –
(IS = –3.05
3 05 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 18 –
dIS/dt = 100 A/µs)
tb – 16 –
g
IF = 1.0
1 0 Ad
Adc
0.47 0.39
IF = 2.0 Adc
0.58 0.53
Maximum Instantaneous Reverse Current IR TJ = 25°C TJ = 125°C mA

Vd
VR = 20 Vdc
0.05 10
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NTMSD3P102R2
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
6 6
VGS = –10 V
VGS = –4.4 V VDS > = –10 V

5 VGS = –8 V 5
VGS = –4 V
VGS = –6 V
VGS = –4.6 V
4 4
TJ = 25°C VGS = –4.8 V TJ = 100°C
3 VGS = –3.6 V 3
VGS = –2.8 V
VGS = –3.2 V TJ = 25°C
2 VGS = –5 V 2
VGS = –3 V TJ = –55°C
VGS = –2.6 V
1 1
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 2 3 4 5


0.7 0.7
ID = –3.05 A ID = –1.5 A
0.6 TJ = 25°C 0.6 TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
3 4 5 6 7 8 2 3 4 5 6 7
Voltage Voltage
0.25 1.6
ID = –3.05 A
TJ = 25°C VGS = –10 V
1.4
0.2 VGS = –4.5 V
(NORMALIZED)
1.2
0.15
1
VGS = –10 V
0.1
0.8
0.05 0.6
1 2 3 4 5 6 –50 –25 0 25 50 75 100 125 150
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NTMSD3P102R2
10000
1200
Ciss
C, CAPACITANCE (pF)
1000
IDSS, LEAKAGE (nA)
TJ = 150°C
1000
800
Ciss
600 Crss
TJ = 125°C
100 400 Coss
200 Crss
TJ = 25°C
10 0
2 4 6 8 10 12 14 16 18 20 10 5 0 5 10 15 20
–VGS –VDS
VOLTAGE (VOLTS)
vs. Voltage
12 24 1000
VDS = –20 V
QT ID = –3.05 A
10 20
VGS = –10 V
VDS
8 16 100
t, TIME (ns)
VGS td(off)
6 12 tf
Q1 tr
4 Q2 8 10
td(on)
2 4
ID = –3.05 A
TJ = 25°C
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

1000 3
VDS = –20 V VGS = 0 V
ID = –1.5 A TJ = 25°C
2.5
VGS = –4.5 V
2
t, TIME (ns)
100 1.5
tr
td(off)
tf 1
td(on)
0.5
10 0
1 10 100 0.2 0.4 0.6 0.8 1 1.2
RG, GATE RESISTANCE (Ω) –VSD, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
vs. Gate Resistance
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NTMSD3P102R2
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
1.0
D = 0.5
THERMAL RESPONSE
0.2
0.1
0.1
Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω 24.4 Ω
0.02
0.01 0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F

0.01
1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
t, TIME (s)
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NTMSD3P102R2
10 10

TJ = 125°C
CURRENT (AMPS)
CURRENT (AMPS)
TJ = 125°C
85°C
1.0 1.0
85°C 25°C
25°C
–40°C
0.1 0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS) VF, MAXIMUM INSTANTANEOUS
FORWARD VOLTAGE (VOLTS)
1E–2
IR, MAXIMUM REVERSE CURRENT (AMPS)
1E–1
IR , REVERSE CURRENT (AMPS)
TJ = 125°C
TJ = 125°C
1E–3 1E–2
85°C
1E–4 1E–3
1E–5 1E–4
25°C
25°C
1E–6 1E–5
1E–7 1E–6
0 5.0 10 15 20 0 5.0 10 15 20
VR, REVERSE VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS)
1000 1.6
TYPICAL CAPACITANCE AT 0 V = 170 pF dc
1.4 FREQ = 20 kHz
C, CAPACITANCE (pF)
1.2 SQUARE WAVE
1.0
Ipk/Io = p
100 0.8
Ipk/Io = 5.0
0.6
Ipk/Io = 10
0.4
Ipk/Io = 20
0.2
10 0
0 5.0 10 15 20 0 20 40 60 80 100 120 140 160
VR, REVERSE VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)
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NTMSD3P102R2
PFO, AVERAGE POWER DISSIPATION (WATTS)

0.7
SQUARE dc
0.6 WAVE
Ipk/Io = p
0.5
Ipk/Io = 5.0
0.4 Ipk/Io = 10
Ipk/Io = 20
0.3
0.2
0.1
0
0 0.5 1.0 1.5 2.0
1.0
D = 0.5
0.2
THERMAL RESISTANCE
0.1
0.1
0.05 NORMALIZED TO RqJA AT STEADY STATE (1″ PAD)
0.02
0.01 4 W $6 W $# W 6$:$ W 4:7 W

0.01 , 6 . 8# . $# . #:6 . $896 .
SINGLE PULSE
=
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
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NTMSD3P102R2

9
$#
#:$ $$
: 6
#6 $
9 #:
inches
mm
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NTMSD3P102R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

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!#!!

(45
Dual SO–8 Package
http://onsemi.com
Features
• High Density Power MOSFET with Low RDS(on), MOSFET
Schottky Diode with Low VF –3.05 AMPERES
• Independent Pin–Outs for MOSFET and Schottky Die
• Less Component Placement for Board Space Savings 0.085 W @ VGS = –10 V
Applications SCHOTTKY DIODE
• DC–DC Converters 3.0 AMPERES
30 VOLTS
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones 420 mV @ IF = 3.0 A

Drain–to–Source Voltage VDSS –30 V 8 # :

Gate–to–Source Voltage – Continuous VGS "20 V 9
1
SO–8 6 $
CASE 751
Continuous Drain Current @ TA = 25°C ID –2.34 A /
STYLE 18
Thermal Resistance – MARKING DIAGRAM
Junction–to–Ambient (Note 2.) RθJA 100 °C/W & PIN ASSIGNMENTS
1 8
Continuous Drain Current @ TA = 70°C ID –2.44 A 2 7
Anode E3P303 Cathode
Source LYWW Drain
Thermal Resistance – 4 5
Junction–to–Ambient (Note 3.) RθJA 62.5 °C/W Gate Drain
Total Power Dissipation @ TA = 25°C PD 2.0 W (Top View)
Continuous Drain Current @ TA = 70°C ID –3.10 A E3P303 = Device Code
Pulsed Drain Current (Note 4.) IDM –15 A L = Assembly Location
Operating and Storage TJ, Tstg –55 to °C Y = Year
Temperature Range +150 WW = Work Week
Energy – Starting TJ = 25°C (VDD = ORDERING INFORMATION
–30 Vdc, VGS = –4.5 Vdc, Peak IL =
–7.5 Apk, L = 5 mH, RG = 25 Ω) Device Package Shipping
Purposes, 1/8″ from case for 10 seconds NTMSD3P303R2 SO–8 2500/Tape & Reel
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

January, 2001 – Rev. 0 NTMSD3P303R2/D
NTMSD3P303R2

Thermal Resistance – Junction–to–Ambient (Note 7.) RθJA 62.5 °C/W
Peak Repetitive Forward Current (Note 7.) IFRM 6.0 A
(Rated VR, Square Wave, 20 kHz, TA = 105°C)

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –30 – –
(VGS = –20 Vdc, VDS = 0 Vdc) – – –100
(VGS = +20 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –1.0 –1.7 –2.5
(VGS = –10 Vdc, ID = –3.05 Adc) – 0.063 0.085
(VGS = –4.5 Vdc, ID = –1.5 Adc) – 0.090 0.125
(VDS = –15 Vdc, ID = –3.05 Adc) – 5.0 –
24 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 170 325
f = 1.0 MHz)
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NTMSD3P303R2

10 Vdc,
VGS = –10 Vdc
VGS = –4.5
4 5 Vdc,
Vdc
(VDS = –24 Vdc,
ID = –3.05
3 05 Adc)
Ad )

(IS = –3.05 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.78 –
(IS = –3.05
3 05 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 18 –
dIS/dt = 100 A/µs)
tb – 16 –
IF = 100 mAdc 0.28 0.13

IF = 3.0 Adc 0.42 0.33
IF = 6.0 Adc 0.50 0.45
Maximum Instantaneous Reverse Current IR TJ = 25°C TJ = 125°C

VR = 30 Vdc
Vd
250 mA
25 mA
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NTMSD3P303R2
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
6 6
VGS = –10 V
VGS = –4.4 V VDS > = –10 V

5 VGS = –8 V 5
VGS = –4 V
VGS = –6 V
VGS = –4.6 V
4 4
TJ = 25°C VGS = –4.8 V TJ = 100°C
3 VGS = –3.6 V 3
VGS = –2.8 V
VGS = –3.2 V TJ = 25°C
2 VGS = –5 V 2
VGS = –3 V TJ = –55°C
VGS = –2.6 V
1 1
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1 2 3 4 5


0.7 0.7
ID = –3.05 A ID = –1.5 A
0.6 TJ = 25°C 0.6 TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
3 4 5 6 7 8 2 3 4 5 6 7
Voltage Voltage
0.25 1.6
ID = –3.05 A
TJ = 25°C VGS = –10 V
1.4
0.2 VGS = –4.5 V
(NORMALIZED)
1.2
0.15
1
VGS = –10 V
0.1
0.8
0.05 0.6
1 2 3 4 5 6 –50 –25 0 25 50 75 100 125 150
http://onsemi.com
201
NTMSD3P303R2
10000
1200
Ciss
C, CAPACITANCE (pF)
TJ = 150°C 1000
IDSS, LEAKAGE (nA)
1000
800
600 Crss Ciss

TJ = 125°C
100 400
Coss
200
Crss
TJ = 25°C
10 0
6 10 14 18 22 26 30 10 5 0 5 10 15 20 25 30
–VGS –VDS
VOLTAGE (VOLTS)
vs. Voltage
12 30 1000
VDS = –24 V
QT ID = –3.05 A
10 25
VGS = –10 V
VDS
8 20 100 td(off)
t, TIME (ns)
VGS
6 15 tf
Q1 tr
4 Q2 10 10
td(on)
2 5
ID = –3.05 A
TJ = 25°C
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

1000 3
VDS = –24 V VGS = 0 V
ID = –1.5 A TJ = 25°C
2.5
VGS = –4.5 V
2
t, TIME (ns)
100 1.5
tr
td(off)
tf 1
td(on)
0.5
10 0
1 10 100 0.2 0.4 0.6 0.8 1 1.2
RG, GATE RESISTANCE (Ω) –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
vs. Gate Resistance
http://onsemi.com
202
NTMSD3P303R2
100
VGS = 12 V
SINGLE PULSE
1.0 ms
TA = 25°C
10
10 ms di/dt
IS
1.0 dc
trr
ta tb
0.1 TIME
RDS(on)
PACKAGE LIMIT
0.01 IS
1 1.0 10 100
Safe Operating Area
1.0
D = 0.5
THERMAL RESPONSE
0.2
0.1
0.1
Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω 24.4 Ω
0.02
0.01 0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F

0.01
1E–03 1E–02 1E–01 1E+00 1E+01 1E+02 1E+03
t, TIME (s)
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203
NTMSD3P303R2

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204
NTMSD3P303R2
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205
NTMSD3P303R2

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206
NTMSD3P303R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
207
# "

#$%& '(
"
N–Channel TO–220
Features 60 VOLTS
• Higher Current Rating
RDS(on) = 46 mΩ
• Lower RDS(on)
• Lower VDS(on)
• Lower Capacitances N–Channel
• Lower Total Gate Charge D
• Tighter VSD Specification

• Lower Reverse Recovery Stored Charge G
• Power Supplies S
• Converters
• Power Motor Controls
• Bridge Circuits MARKING DIAGRAM
& PIN ASSIGNMENT
4
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) 4 Drain
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc TO–220AB
CASE 221A
Gate–to–Source Voltage Vdc STYLE 5 NTP27N06
– Continuous VGS ±20 LLYWW
– Non–Repetitive (tp ≤ 10 ms) VGS ±30
1 1 3
Drain Current 2 Gate Source
– Continuous @ TA = 25°C ID 27 Adc 3
– Continuous @ TA = 100°C ID 15 2
– Single Pulse (tp ≤ 10 µs) IDM 80 Apk Drain
Derate above 25°C 0.59 W/°C NTP27N06 = Device Code
LL = Location Code
Operating and Storage Temperature Range TJ, Tstg –55 to °C Y = Year
175 WW = Work Week
Single Pulse Drain–to–Source Avalanche EAS mJ
Energy – Starting TJ = 25°C 109 ORDERING INFORMATION
L = 0.3 mH, IL(pk) = 27 A, VDS = 60 Vdc) Device Package Shipping
Thermal Resistance – Junction–to–Case RθJC 1.7 °C/W NTP27N06 TO–220AB 50 Units/Rail

Purposes, 1/8″ from Case for 10 seconds


March, 2001 – Rev. 1 NTP27N06/D
NTP27N06

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 70 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0
Static Drain–to–Source On–Resistance (Note 1.) RDS(on) mW
(VGS = 10 Vdc, ID = 13.5 Adc) – 37.5 46
(VGS = 10 Vdc, ID = 27 Adc) – 1.05 1.5
(VGS = 10 Vdc, ID = 13.5 Adc, TJ = 150°C) – 2.12 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 213 300
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) (Note 1.) td(off) – 26.6 60
(VDS = 48 Vd
Vdc, ID = 27 Adc,
Ad
Q1 – 5.6 –
Q2 – 7.3 –

(IS = 27 Adc, VGS = 0 Vdc) (Note 1.) – 1.05 1.25
(IS = 27 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.93 –
(IS = 27 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 26 –
tb – 16 –
Reverse Recovery Stored Charge QRR – 0.07 – µc
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209
#
#$%& '(

N–Channel TO–220 and D2PAK
Features
45 AMPERES
• Tighter VSD Specification D

• Power Supplies 4
• Converters S
• Bridge Circuits 1 2
3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) TO–220AB D2PAK
CASE 221A CASE 418B
STYLE 5 STYLE 2
1
Drain–to–Source Voltage VDSS 60 Vdc 2
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc 3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
– Non–Repetitive (tpv10 ms) VGS "30 4
Drain 4
Drain Current Drain
NTB45N06
Total Power Dissipation @ TA = 25°C PD 125 W LLYWW
Derate above 25°C 0.83 W/°C NTP45N06
Total Power Dissipation @ TA = 25°C (Note 1.) 3.2 W LLYWW
Total Power Dissipation @ TA = 25°C (Note 2.) 2.4 W 1 2 3
1 3
Operating and Storage Temperature Range TJ, Tstg –55 to °C Gate Source
Gate Drain Source
+175
Single Pulse Drain–to–Source Avalanche EAS 240 mJ 2
NTx45N06 = Device Code
Energy – Starting TJ = 25°C Drain
LL = Location Code
(VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 Ω,
Y = Year
IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc)
WW = Work Week
pad size, (Cu Area 0.412 in2). Device Package Shipping
NTP45N06 TO–220AB 50 Units/Rail
NTB45N06 D2PAK 50 Units/Rail
NTB45N06T4 D2PAK 800/Tape & Reel

March, 2001 – Rev. 0 NTP45N06/D
NTP45N06, NTB45N06

Thermal Resistance – Junction–to–Case RθJC 1.2 °C/W
– Junction–to–Ambient (Note 3.) RθJA 46.8

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 70 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0 mV/°C
Threshold Temperature Coefficient (Negative) – 7.2 –
(VGS = 10 Vdc, ID = 22.5 Adc) – 21 26

(VGS = 10 Vdc, ID = 45 Adc) – 0.93 1.4
(VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150°C) – 0.93 –
Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) gFS – 16.6 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 345 485
f = 1.0 MHz)

Turn–Off Delay Time VGS = 10 Vdc, RG = 9.1 Ω) (Note 5.) td(off) – 33 70
(VDS = 48 Vd
Vdc, ID = 45 Adc,
Ad
Q1 – 6.4 –
Q2 – 15 –
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.93 –
(IS = 45 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 36 –
tb – 16.9 –
3. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).
4. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
http://onsemi.com
211
NTP45N06, NTB45N06
90 90
VGS = 10 V VGS = 7 V VDS > = 10 V
80 80

VGS = 9 V
70 VGS = 6.5 V 70
60 60
VGS = 8 V VGS = 6 V
50 50
VGS = 7.5 V VGS = 5.5 V
40 40
30 30
VGS = 5 V TJ = 25°C
20 20
VGS = 4.5 V TJ = 100°C
10 10
TJ = –55°C
0 0
0 1 2 3 4 5 6 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8


0.05 0.032
VGS = 10 V
0.03
0.042
0.028
0.034 TJ = 100°C
0.026
0.024 VGS = 10 V
0.026 TJ = 25°C
0.022
0.018 TJ = –55°C
0.02 VGS = 15 V
0.01 0.018
0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90
2.2 10000
VGS = 0 V
ID = 22.5 A
2 VGS = 10 V
IDSS, LEAKAGE (nA)
TJ = 150°C
1.8
(NORMALIZED)
1000
1.6
1.4 TJ = 125°C
1.2
100
1
TJ = 100°C
0.8
0.6 10
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60

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212
NTP45N06, NTB45N06

3600 12
VDS = 0 V VGS = 0 V TJ = 25°C
3200 QT
Ciss 10
2800
C, CAPACITANCE (pF)
VGS
2400 Crss 8
2000 Q1 Q2
6
1600 Ciss
1200 4
800 Coss
2 ID = 45
400 Crss TJ = 25°C
0 0
10 5 VGS 0 VDS 5 10 15 20 25 0 4 8 12 16 20 24 28 32 36
(VOLTS)
1000 50

ID = 45 A TJ = 25°C
VGS = 10 V 40
tf
100
t, TIME (ns)
tr 30
td(off)
td(on) 20
10
10
1 0
1 10 100 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04
vs. Gate Resistance
1000 280
VGS = 20 V ID = 45 A
SINGLE PULSE
240
TC = 25°C
100
200
dc
160
10 ms
10
1 ms 120
RDS(on) Limit 100 µs

80
1 Thermal Limit
Package Limit
40
0.1 0
0.10 1 10 100 25 50 75 100 125 150 175
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213
NTP45N06, NTB45N06
1
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RθJC at Steady State
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (s)
10
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.1
0.01
0.001
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
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214
#
#$%& '(

* %+%
Features
45 AMPERES
• Tighter VSD Specification D

• Power Supplies 4
• Converters S
• Bridge Circuits 1 2
3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) TO–220AB D2PAK
CASE 221A CASE 418B
STYLE 5 STYLE 2
1
Drain–to–Gate Voltage (RGS = 10 MΩ) VDGR 60 Vdc 3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
– Non–Repetitive (tpv10 ms) VGS "20 4
Drain 4
Drain Current Drain
NTB45N06L
Total Power Dissipation @ TA = 25°C PD 125 W
NTP45N06L LLYWW
Total Power Dissipation @ TA = 25°C (Note 1.) 3.2 W LLYWW
1 3 1 3
Operating and Storage Temperature Range TJ, Tstg –55 to °C Gate Source Drain
Gate Source
+175
NTx45N06L = Device Code
LL = Location Code
(VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH
Y = Year
IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 Ω)
WW = Work Week
pad size, (Cu Area 0.412 in2). Device Package Shipping
NTP45N06L TO–220AB 50 Units/Rail
NTB45N06L D2PAK 50 Units/Rail
NTB45N06LT4 D2PAK 800/Tape & Reel

March, 2001 – Rev. 0 NTP45N06L/D
NTP45N06L, NTB45N06L

Thermal Resistance – Junction–to–Case RθJC 1.2 °C/W

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 67 –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.8 2.0
(VGS = 5.0 Vdc, ID = 22.5 Adc) – 23 28

(VGS = 5.0 Vdc, ID = 45 Adc) – 1.03 1.51
(VGS = 5.0 Vdc, ID = 22.5 Adc, TJ = 150°C) – 0.93 –
Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) gFS – 22.8 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 352 480
f = 1.0 MHz)
Turn–Off Delay Time VGS = 5.0 Vdc, RG = 9.1 Ω) (Note 5.) td(off) – 36 75
(VDS = 48 Vd
Vdc, ID = 45 Adc,
Ad
Q1 – 4.6 –
VGS = 5.0 Vdc) (Note 5.)
Q2 – 14.1 –

(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.92 –
(IS = 45 Ad
Adc, VGS = 0 Vd
Vdc,
ta – 30 –
tb – 26 –
3. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).
4. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
http://onsemi.com
216
80 80
VGS = 10 V VGS = 5.5 V
VDS > = 10 V
70 70

VGS = 5 V
60 VGS = 6 V 60
50 VGS = 4.5 V 50
VGS = 7 V
40 40
VGS = 4 V
30 30
TJ = 25°C
VGS = 8 V
20 20
VGS = 3.5 V TJ = 100°C
10 VGS = 9 V 10
TJ = –55°C
0 0
0 1 2 3 4 1.8 2.6 3.4 4.2 5 5.8


0.046 0.046
VGS = 5 V
0.042 0.042
TJ = 100°C
0.038
0.038
0.034
0.034
0.03 TJ = 25°C VGS = 5 V
0.03
0.026
0.026
0.022
TJ = –55°C
0.022 VGS = 10 V
0.018
0.014 0.018
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
2 10000
ID = 22.5 A VGS = 0 V
1.8 VGS = 5 V
TJ = 150°C
IDSS, LEAKAGE (nA)
1.6
1000
(NORMALIZED)
1.4 TJ = 125°C
1.2
100
1
TJ = 100°C
0.8
0.6 10
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60

http://onsemi.com
217

4000 6
VDS = 0 V VGS = 0 V TJ = 25°C
3600 Ciss QT
5 VGS
3200
C, CAPACITANCE (pF)
Crss Q1 Q2
2800
4
2400
2000 3
1600 Ciss
2
1200
800 Coss
1 ID = 45 A
400 Crss TJ = 25°C
0 0
10 5 VGS 0 VDS 5 10 15 20 25 0 4 8 12 16 20 24
(VOLTS)
1000 48
VDS = 30 V
VGS = 0 V

ID = 45 A
40 TJ = 25°C
VGS = 5 V tr
tf 32
t, TIME (ns)
100 24
td(off)
16
8
td(on)
10 0
1 10 100 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1
vs. Gate Resistance
1000 280
VGS = 15 V
ID = 45 A
SINGLE PULSE
240
TC = 25°C
100
200
dc 160
10
10 ms
120
1 ms
1
RDS(on) Limit 100 µs 80
Thermal Limit
Package Limit
40
0.1 0
0.10 1 10 100 25 50 75 100 125 150 175
http://onsemi.com
218
1
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RθJC at Steady State
0.1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (s)
10
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.1
0.01
0.001
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
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219
#"!
"!
#$%& '(
" !
This 10 VGS gate drive vertical Power MOSFET is a general http://onsemi.com
purpose part that provides the “best of design” available today in a low
cost power package. Avalanche energy issues make this part an ideal 75 AMPERES
design in. The drain–to–source diode has a ideal fast but soft recovery. 30 VOLTS
Features
• Ultra–Low RDS(on), Single Base, Advanced Technology
RDS(on) = 6.5 mΩ
• SPICE Parameters Available N–Channel
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperatures
• ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0
• Power Supplies
• Inductive Loads 4
• PWM Motor Controls 4

• Replaces MTP1306 and MTB1306 in Many Applications
1 2
3
TO–220AB D2PAK
CASE 221A CASE 418B
1 STYLE 5 STYLE 2
2
3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4 4
Drain Drain
E75
N03–06
YWW
E75
N03–06
YWW 1 3
Gate Source
1 3 2
Gate Source Drain
2 N03–06 = Device Code

Drain Y = Year
WW = Work Week
NTP75N03–06 TO–220 50 Units/Rail
NTB75N03–06 D2PAK 50 Units/Rail

NTB75N03–06T4 D2PAK 800 Tape & Reel

December, 2000 – Rev. 0 NTP75N03–06/D
NTP75N03–06, NTB75N03–06

Drain–to–Gate Voltage VDGB 30 Vdc
(RGS = 10 MΩ)
Non–repetitive (tp ≤ 10 ms) VGS ±24 Vdc
Drain Current
– Continuous @ TA = 25_C ID 75 Adc
– Continuous @ TA = 100_C ID 59
– Single Pulse (tp ≤ 10 µs) IDM 225 Apk
Total Power Dissipation @ TC = 25°C PD 150 W
Derate above 25°C 1.0 W/_C
Operating and Storage Temperature Range TJ and Tstg –55 to 150 _C
(VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc)
Thermal Resistance
– Junction–to–Case RθJC 1.0 _C/W
– Junction–to–Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 _C
1. When surface mounted to an FR4 board using the minimum recommended pad size.
http://onsemi.com
221
NTP75N03–06, NTB75N03–06

Characteristic Symbol Min Typ. Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Note 2.) V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – – Vdc
Temperature Coefficient (Negative) –57 – mV°C
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
Gate Threshold Voltage (Note 2.) VGS(th)
(VDS = VGS, ID = 250 µAdc) 1.0 1.6 2.0 Vdc
Threshold Temperature Coefficient (Negative) – –6 – mV°C
(VGS = 10 Vdc, ID = 37.5 Adc) – 5.3 6.5
Static Drain–to–Source On Resistance (Note 2.) VDS(on) Vdc
(VGS = 10 Vdc, ID = 75 Adc) – 0.53 0.68
(VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125°C) – 0.35 0.50
Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) gFS – 58 – Mhos

(VDS = 25 Vd
Vdc, VGS = 0
0,
Output Capacitance Coss – 1160 1894
f = 1.0 MHz)

(VGS = 55.0
0 Vd
Vdc,
Rise Time tr – 510 986
VDD = 20 Vdc, ID = 75 Adc,
Gate Charge (VGS = 5.0 Vdc, QT – 52 122 nC
ID = 75 Adc,
Ad
Q1 – 6.6 28
VDS = 24 Vdc) (Note 2.)
Q2 – 28 66

Forward On–Voltage (IS = 75 Adc, VGS = 0 Vdc) VSD – 1.19 1.25 Vdc
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C) – 1.09 –
(Note 2.)
(N t 4
(Note 4.)) (IS = 75 Ad
Adc, VGS = 0 Vd
Vdc
ta – 20 –
dlS/dt = 100 A/µs) (Note 2.)
Reverse Recovery Stored tb – 17 – µC
Ch
Charge (Note
(N t 4.)
4)
QRR – 0.023 –
2. Pulse Test: Pulse Width v 300 µS, Duty Cycle v 2%.
4. From characterization test data.
http://onsemi.com
222
NTP75N03–06, NTB75N03–06
150
120 VGS = 4 V
VGS = 3.5 V 135 VDS ≥ 10 V
VGS = 4.5 V

120
90
VGS = 5 V
105
VGS = 6 V
VGS = 8 V 90
60
VGS = 10 V 75
VGS = 3 V
60
30
45 TJ = 25°C
TJ = 25°C
VGS = 2.5 V 30
0 TJ = 100°C
15 TJ = –55°C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 0.5 1 1.5 2 2.5 3 3.5 4

RDS(on), DRAIN–TO SOURCE RESISTANCE (Ω)

0.0085 0.009
VGS = 5 V TJ = 25°C
0.008
TJ = 100°C
0.0075 0.008
0.007
TJ = 25°C 0.007
0.0065 VGS = 5 V
0.006
0.006
0.0055 VGS = 10 V
TJ = –55°C
0.005 0.005
0.0045
0.004 0.004
10 20 30 40 50 60 70 80 90 100 120 0 20 40 60 80 100 120
RDS(on), DRAIN–TO SOURCE RESISTANCE (NORMALIZED)
1.6 1000
ID = 37.5 A
1.4
TJ = 125°C
IDSS, LEAKAGE (nA)
100
1.2
TJ = 100°C
1
10
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30
Figure 5. On–Resistance Variation Temperature Figure 6. Drain–to–Source Leakage Current vs.

Voltage
http://onsemi.com
223
NTP75N03–06, NTB75N03–06

1200 12 30
VGS VDS
VDS = 0 V
QT
1000 VGS = 0 V 10 25
TJ = 25°C
C, CAPACITANCE (pF)
800 8 20
VGS
600 6 15
Ciss Q1
Q2
400 4 10
Coss
200 2 ID = 75 A 5
Crss TJ = 25°C
0 0 0
10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 0 4 8 12 16 20 24 28 32 36 40 44 48 52
GATE–TO–SOURCE OR DRAIN–TO–SOURCE Qg, TOTAL GATE CHARGE (nC)
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Gate–to–Source Voltage vs. Total Charge
1000 75
70 VGS = 0 V
tr IS, SOURCE CURRENT (AMPS) 65 TJ = 25°C
60
55
50
t, TIME (ns)
tf 45
40
100
35
td(off) 30
25
20
td(on) 15
TJ = 25°C VDD = 15 V 10
ID = 75 A VGS = 5 V 5
10 0
1 2.2 4.7 6.2 9.1 10 20 0.0 0.2 0.4 0.6 0.8 1.0
vs. Gate Resistance
1600
1400 ID = 75 A
1200
1000
800
600
400
200
0
25 50 75 100 125 150

http://onsemi.com
224
#"!)
"!)
#$%& '(
" !
This Logic Level Vertical Power MOSFET is a general purpose part http://onsemi.com
that provides the “best of design” available today in a low cost power
package. Avalanche energy issues make this part an ideal design in. 75 AMPERES
The drain–to–source diode has a ideal fast but soft recovery. 30 VOLTS
Features
• Ultra–Low RDS(on), Single Base, Advanced Technology
RDS(on) = 9 mΩ
• SPICE Parameters Available N–Channel
• IDSS and VDS(on) Specified at Elevated Temperatures
• ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0
• Power Supplies
• Inductive Loads
4
• PWM Motor Controls
• Replaces MTP75N03HDL and MTB75N03HDL in Many 4
Applications 1 2
3
TO–220AB D2PAK
CASE 221A CASE 418B
STYLE 5 STYLE 2
1
2
3 MARKING DIAGRAMS
& PIN ASSIGNMENTS
4 4
Drain Drain
E75
N03L09
YWW
E75
N03L09
YWW 1 3
Gate 2 Source
1 3
Gate Source Drain
2 N03L09 = Device Code

Drain Y = Year
WW = Work Week
NTP75N03L09 TO–220 50 Units/Rail
NTB75N03L09 D2PAK 50 Units/Rail

NTB75N03L09T4 D2PAK 800 Tape & Reel

December, 2000 – Rev. 0 NTP75N03L09/D
NTP75N03L09, NTB75N03L09

Drain–to–Gate Voltage VDGB 30 Vdc
(RGS = 10 MΩ)
Non–repetitive (tp ≤ 10 ms) VGS ±24 Vdc
Drain Current
– Continuous @ TA = 25_C ID 75 Adc
– Continuous @ TA = 100_C ID 59
Total Power Dissipation @ TC = 25°C PD 150 W
Derate above 25°C 1.0 W/_C
Operating and Storage Temperature Range TJ and Tstg –55 to 150 _C
(VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc)
Thermal Resistance
– Junction–to–Case RθJC 1.0 _C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 _C
http://onsemi.com
226

Characteristic Symbol Min Typ. Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Note 2.) V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 30 34 – Vdc
Temperature Coefficient (Negative) –57 – mV°C
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
Gate Threshold Voltage (Note 2.) VGS(th)
Threshold Temperature Coefficient (Negative) – –6 – mV°C
(VGS = 5.0 Vdc, ID = 37.5 Adc) – 7.5 9
Static Drain–to–Source On Resistance (Note 2.) VDS(on) Vdc
(VGS = 10 Vdc, ID = 75 Adc) – 0.52 0.68
(VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125°C) – 0.35 0.50
Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) gFS – 58 – mΩ

(VDS = 25 Vd
Vdc, VGS = 0
0,
Output Capacitance Coss – 1160 1894
f = 1.0 MHz)

(VGS = 55.0
0 Vd
Vdc,
Rise Time tr – 510 986
VDD = 20 Vdc, ID = 75 Adc,
Gate Charge (VGS = 5.0 Vdc, QT – 52 122 nC
ID = 75 Adc,
Ad
Q1 – 6.6 28
VDS = 24 Vdc) (Note 2.)
Q2 – 28 66

Forward On–Voltage (IS = 75 Adc, VGS = 0 Vdc) VSD – 1.19 1.25 Vdc
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C) – 1.09 –
(Note 2.)
(N t 4
(Note 4.)) (IS = 75 Ad
Adc, VGS = 0 Vd
Vdc
ta – 20 –
dlS/dt = 100 A/µs) (Note 2.)
Reverse Recovery Stored tb – 17 – µC
Ch
Charge (Note
(N t 4.)
4)
QRR – 0.023 –
4. From characterization test data.
http://onsemi.com
227
150
120 VGS = 4 V
VGS = 3.5 V 135 VDS ≥ 10 V
VGS = 4.5 V

120
90
VGS = 5 V
105
VGS = 6 V
VGS = 8 V 90
60
VGS = 10 V 75
VGS = 3 V
60
30
45 TJ = 25°C
TJ = 25°C
VGS = 2.5 V 30
0 TJ = 100°C
15 TJ = –55°C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 0.5 1 1.5 2 2.5 3 3.5 4


0.0085 0.009
VGS = 5 V TJ = 25°C
0.008
TJ = 100°C
0.0075 0.008
0.007
TJ = 25°C 0.007
0.0065 VGS = 5 V
0.006
0.006
0.0055 VGS = 10 V
TJ = –55°C
0.005 0.005
0.0045
0.004 0.004
10 20 30 40 50 60 70 80 90 100 120 0 20 40 60 80 100 120
RDS(on), DRAIN–TO SOURCE RESISTANCE (NORMALIZED)
1.6 1000
ID = 37.5 A
1.4
TJ = 125°C
IDSS, LEAKAGE (nA)
100
1.2
TJ = 100°C
1
10
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30
Figure 5. On–Resistance Variation Temperature Figure 6. Drain–to–Source Leakage Current vs.

Voltage
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228

1200 12 30
VGS VDS
VDS = 0 V
QT
1000 VGS = 0 V 10 25
TJ = 25°C
C, CAPACITANCE (pF)
800 8 20
VGS
600 6 15
Ciss Q1
Q2
400 4 10
Coss
200 2 ID = 75 A 5
Crss TJ = 25°C
0 0 0
10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 0 4 8 12 16 20 24 28 32 36 40 44 48 52
GATE–TO–SOURCE OR DRAIN–TO–SOURCE Qg, TOTAL GATE CHARGE (nC)
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Gate–to–Source Voltage vs. Total Charge
1000 75
70 VGS = 0 V
tr IS, SOURCE CURRENT (AMPS) 65 TJ = 25°C
60
55
50
t, TIME (ns)
tf 45
40
100
35
td(off) 30
25
20
td(on) 15
TJ = 25°C VDD = 15 V 10
ID = 75 A VGS = 5 V 5
10 0
1 2.2 4.7 6.2 9.1 10 20 0.0 0.2 0.4 0.6 0.8 1.0
vs. Gate Resistance
1600
1400 ID = 75 A
1200
1000
800
600
400
200
0
25 50 75 100 125 150

http://onsemi.com
229
6,

#$%& '(
-,
N–Channel TSSOP–8
• New Low Profile TSSOP–8 Package
5.8 AMPERES
• Diode Exhibits High Speed, Soft Recovery RDS(on) = 30 mΩ
• IDSS and VDS(on) Specified at Elevated Temperatures N–Channel N–Channel
Applications D D
Computers, Printers, PCMCIA Cards, Cellular and Cordless
Telephones
• Note Book PC
G1 G2

S1 S2
Gate–to–Source Voltage – Continuous VGS "12 Vdc
Drain Current – Continuous ID 5.8 Adc TSSOP–8
Drain Current – Continuous @ 70°C ID TBD 8 CASE 948S
Drain Current – Single Pulse (tp ≤ 10 ms) IDM 20 PLASTIC
Total Power Dissipation PD 1.6 W 1
Operating and Storage TJ, Tstg –55 to °C
Temperature Range +150 MARKING DIAGRAM
Single Pulse Drain–to–Source Avalanche EAS 580 mJ & PIN ASSIGNMENT
(VDD = 20 Vdc, VGS = 5 Vdc, S1 1 8 D
IL = 10 Apk, L = 10 mH, RG = 25 Ω) DEVICE D
G1 2 7
Thermal Resistance – RqJA °C/W S2 3
MARKING
6 D
Junction–to–Ambient (Note 1.) TBD
G2 4 5 D
Single Channel Steady State 180
Both Channels 176
Top View
Junction–to–Ambient (Note 2.)
Both Channels 100
Thermal Resistance – Junction–to–Lead RqJL °C/W
Single Channel 27
Both Channels Steady State 24
1. Surface Mounted to Min Pad. Device Package Shipping
2. Surface Mounted to 1″ x 1″ FR4 Board.
NTQD6866 TSSOP–8 100 Units/Rail
NTQD6866R2 TSSOP–8 3000/Tape & Reel


January, 2001 – Rev. 1 NTQD6866/D
NTQD6866

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
Temperature Coefficient (Positive) – TBD – mV/°C
Zero Gate Voltage Collector Current IDSS µAdc
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current IGSS(f) – – 100 nAdc
(VGS = ±12 Vdc, VDS = 0 Vdc) IGSS(r) – – 100

(VDS = VGS, ID = 0.25 mA) 0.6 0.9 1.2
Temperature Coefficient (Negative) – TBD – mV/°C
(VGS = 4.5 Vdc, ID = 7.0 Adc) – TBD TBD
(VGS = 4.0 Vdc, ID = 7.0 Adc) – 0.026 0.030
(VGS = 2.5 Vdc, ID = 3.5 Adc) – 0.031 0.040
Forward Transconductance (VDS = 10 Vdc, ID = 7.0 Adc) gFS TBD 17 – Mhos
Input Capacitance Ciss – 930 TBD pF
Vdc, VGS = 0 Vd
Vdc,
Coss – 370 TBD
f = 1.0 MHz)
Transfer Capacitance Crss – 105 TBD
Turn–On Delay Time td(on) – 8.6 TBD ns
Rise Time (VDD = 10 Vdc, ID = 1.0 Adc, tr – 14 TBD
VGS = 44.5
5 Vdc
Vdc,
Turn–Off Delay Time RL = 10, RG = 6.0 Ω) td(off) – 57 TBD
Fall Time tf – 54 TBD
(VDS = 10 Vdc,
VGS = 4.5 Vdc, Q1 – 2.4 –
ID = 5.8
5 8 Ad
Adc))
Q2 – 2.4 –
Forward On–Voltage (Note 3.) (IS = 1.8 Adc, VGS = 0 Vdc) VSD – 0.7 1.0 Vdc
(IS = 1.8 Adc, VGS = 0 Vdc, TJ = 85°C) – TBD –
(IS = 1.5
1 5 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 14.5 –
dIS/dt = 100 A/µs)
tb – 15.5 –
http://onsemi.com
231
6!

#$%& '(
-
P–Channel TSSOP–8
• New Low Profile TSSOP–8 Package
• Ultra Low RDS(on) 6.2 AMPERES
• Diode Exhibits High Speed, Soft Recovery RDS(on) = 20 mΩ
• IDSS and VDS(on) Specified at Elevated Temperatures P–Channel
Applications
• Power Management in Portable and Battery–Powered Products, i.e.: D
Telephones
• Note Book PC G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) S
Rating Symbol 10 Steady Unit

MARKING
secs State
DIAGRAM
Drain–to–Source Voltage VDS –20 Vdc
Gate–to–Source Voltage VGS "12 8 TSSOP–8 463
Continuous Drain Current ID Adc CASE 948S YWW
– TJ = 150°C (Note 1.) PLASTIC X
– TA = 25°C "7.4 "6.2 1
– TA = 70°C "5.9 "4.9
Pulsed Drain Current (10 µs IDM "30 Apk 463 = Device Code
Pulse Width) Y = Year
Continuous Source Current IS –1.35 –0.95 Adc WW = Work Week
(Diode Conduction) (Note 1.) X = MOSFET
(Note 1.) PIN ASSIGNMENT
– TA = 25°C 1.5 1.05
– TA = 70°C 1.0 0.67 D 1 8 D
Operating Junction and Storage TJ, Tstg –55 to +150 °C S 2 7 S
Temperature Range S 3 6 S
Single Pulse Drain–to–Source EAS 1.38 J G 4 5 D
Avalanche Energy – Starting
TJ= 25°C Top View
(VDD = 50 V, IL = 16.3 Apk,
L = 10 mH)
1. Surface mounted to 1″ x 1″ FR–4 board.
NTQS6463 TSSOP–8 100 Units/Rail
NTQS6463R2 TSSOP–8 3000/Tape & Reel


January, 2001 – Rev. 0 NTQS6463/D
NTQS6463
THERMAL RESISTANCE RATINGS

Rating Symbol Typical Max Unit
Maximum Junction–to–Ambient (Note 2.) RθJA °C/W
t ≤ 10 sec 65 83
Steady State 100 120
Maximum Junction–to–Foot RθJF °C/W
Steady State 43 52

STATIC
(VDS = VGS, ID = –250 µA) –0.45 –0.9 –
Gate–Body Leakage (VGS = 0 Vdc, VGS = ±8 Vdc) IGSS – – ±100 nAdc

Zero Gate Threshold Voltage Drain Current IDSS
(VDS = –16 Vdc, VGS = 0 Vdc) – – –1.0 µΑdc
(VDS = –16 Vdc, VGS = 0 Vdc, TJ = 70_C) – – –10
On–State Drain Current (Note 3.) ID(on) Adc
(VDS = –5.0 Vdc, VGS = –4.5 Vdc) 20 – –
Drain–Source On–State Resistance (Note 3.) RDS(on) Ω

(VGS = –4.5 Vdc, ID = –7.4 Adc) – 0.018 0.020
(VGS = –2.5 Vdc, ID = –6.3 Adc) – 0.025 0.027
Forward Transconductance (VDS = –15 Vdc, ID = –7.4 Adc) (Note 3.) gFS – 21 – S
Diode Forward Voltage (IS = –1.3 Adc, VGS = 0 Vdc) (Note 3.) VSD – –0.71 –1.1 Vdc
DYNAMIC (Note 4.)
(VDS = –10 Vdc,
ID = –7.4
7 4 Ad
Adc))
(VDD = –10 Vdc RL = 15 Ω,
10 Vdc, Ω
Rise Time ID ≅ –1.0
1.0 Adc, tr – 20 50
Turn–Off Delay Time VGEN = –4.5 Vdc, td(off) – 95 120
RG = 6 0 Ω)
6.0
Source–Drain Reverse (IF = –1.3 Adc, trr – 45 80 ns
Recovery Time di/dt = 100 A/µs)
2. Surface mounted to 1″ x 1″ FR–4 board.
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233
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#$%& '(
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P–Channel Enhancement Mode
Dual Micro8 Package http://onsemi.com
Features
–1.45 AMPERES
• Logic Level Gate Drive –20 VOLTS
• Miniature Dual Micro8 Surface Mount Package 160 mW @ VGS = –4.5
• Micro8 Mounting Information Provided
Applications Dual P–Channel
• Power Management in Portable and Battery–Powered Products, i.e.: D
Telephones
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) G

Drain–to–Source Voltage VDSS –20 V S
Gate–to–Source Voltage – Continuous VGS "8.0 V
8
Pulsed Drain Current (Note 3.) IDM –10 A Micro8
Thermal Resistance – CASE 846A
Junction–to–Ambient (Note 2.) RθJA 125 °C/W STYLE 2
Continuous Drain Current @ TA = 70°C ID –1.64 A MARKING DIAGRAM
Pulsed Drain Current (Note 3.) IDM –16 A & PIN ASSIGNMENT
Operating and Storage TJ, Tstg –55 to °C
Temperature Range +150 1 Drain 1
Source 1 8
Single Pulse Drain–to–Source Avalanche EAS 35 mJ Gate 1 2 YWW 7 Drain 1
Energy – Starting TJ = 25°C Source 2 3 6 Drain 2
BC
(VDD = –20 Vdc, VGS = –4.5 Vdc, Gate 2 4 5 Drain 2
Peak IL = –3.5 Apk, L = 5.6 mH,
RG = 25 Ω) (Top View)
Maximum Lead Temperature for Soldering TL 260 °C Y = Year
Purposes for 10 seconds WW = Work Week
1. Minimum FR–4 or G–10 PCB, Steady State. BC = Device Code
sided), Steady State.
NTTD1P02R2 Micro8 4000/Tape & Reel

November, 2000 – Rev. 0 NTTD1P02R2/D
NTTD1P02R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = 0 Vdc, VDS = –20 Vdc, TJ = 125°C) – – –10
(VGS = –8 Vdc, VDS = 0 Vdc) – – –100
(VGS = +8 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.7 –0.95 –1.4
(VGS = –4.5 Vdc, ID = –1.45 Adc) – 0.130 0.160
(VGS = –2.7 Vdc, ID = –0.7 Adc) – 0.175 0.250
(VGS = –2.5 Vdc, ID = –0.7 Adc) – 0.190 –
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 100 –
f = 1.0 MHz)
16 Vdc, ID = –1.45
1.45 Adc, tr – 25 –
Turn–Off Delay Time VGS = –4.5 Vdc, RG = 6.0 Ω) td(off) – 30 –
16 Vdc, ID = –0.7
0.7 Adc, tr – 20 –
(VDS = –16 Vdc,
ID = –1.45
1 45 Adc)
Ad )
(IS = –1.45 Adc, VGS = 0 Vdc, – –0.72 –
TJ = 125°C)
(IS = –1.45
1 45 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 13 –
dIS/dt = 100 A/µs)
tb – 12 –
http://onsemi.com
235
NTTD1P02R2
3 –2.7 V 3
–2.5 V
–2.9 V –2.3 V VDS ≥ –10 V

–3.1 V
TJ = 25°C
–3.3 V
–3.7 V
–4.5 V –2.1 V
2 2
–8 V
–1.9 V TJ = –55°C
1 1
TJ = 100°C TJ = 25°C
–1.7 V
VGS = –1.5 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 0 0.5 1 1.5 2 2.5 3 3.5


0.4 0.3
TJ = 25°C
ID = –1.45 A
0.3 VGS = –2.5 V
TJ = 25°C
0.2
VGS = –2.7 V
0.2
VGS = –4.5 V
0.1
0.1
0 0
0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5
Figure 3. On–Resistance versus Figure 4. On–Resistance versus Drain Current

Gate–to–Source Voltage and Gate Voltage
1.6 100
VGS = 0 V
ID = –1.45 A
1.4 VGS = –4.5 V

TJ = 125°C
1.2
10 TJ = 100°C
1
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 4 8 12 16 20

http://onsemi.com
236
NTTD1P02R2

800 5 20
Ciss 18
TJ = 25°C 4 16
C, CAPACITANCE (pF)
600
Crss 14
–VGS
3 12
400 Q1 Q2 10
2 8
Ciss
6
200 ID = –1.45 A
1 –VDS TJ = 25°C 4
Coss
2
Crss 0
0 0
10 5 0 5 10 15 20 0 1 2 3 4 5 6
VOLTAGE (VOLTS)
Drain–to–Source Voltage versus Total Charge
100
VDD = –16 V VGS = 0 V
ID = –1.45 A –IS, SOURCE CURRENT (AMPS) 1.6
TJ = 25°C
VGS = –4.5 V
1.2
t, TIME (ns)
tr
td (off)
10 tf
0.8
td (on)
0.4
1 0
1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage
versus Gate Resistance versus Current
100
VGS = 8 V
SINGLE PULSE
TC = 25°C di/dt
10 IS
100 ms
trr
1 ms ta tb
1
10 ms TIME
tp 0.25 IS
0.1
RDS(on) LIMIT IS
THERMAL LIMIT dc
PACKAGE LIMIT
0.01
0.1 1 10 100 Figure 12. Diode Reverse Recovery Waveform
Figure 11. Maximum Rated Forward Biased

Safe Operating Area
http://onsemi.com
237
NTTD1P02R2
1000
THERMAL RESISTANCE (°C/W)
D = 0.5
100
0.2
0.1
0.05
10 *0
0.02
θ,' " ('
θ,
0.01
- .
/

/
1 '
'
'# ,*0 " *0
θ,'
SINGLE PULSE
- - " '&'#
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE

0.041
1.04
0.208 0.126
5.28 3.20
0.015 0.0256
0.38 0.65
inches
mm
http://onsemi.com
238
NTTD1P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
239
NTTD1P02R2
TAPE & REEL INFORMATION

Micro8
Dimensions are shown in millimeters (inches)
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
1. CONFORMS TO EIA–481–1.
2. CONTROLLING DIMENSION: MILLIMETER.
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.
http://onsemi.com
240
#
#$%& '(
-
Dual P–Channel Micro8
Features
• Miniature Micro–8 Surface Mount Package –2.4 AMPERES
• Micro8 Mounting Information Provided –20 VOLTS
Applications RDS(on) = 90 m
P–Channel

Gate–to–Source Voltage – Continuous VGS "8.0 V
MARKING
DIAGRAM
Continuous Drain Current @ TA = 70°C ID –2.6 A YWW
Micro8
Pulsed Drain Current (Note 3.) IDM –30 A BE
CASE 846A
Operating and Storage TJ, Tstg –55 to °C STYLE 2
Energy – Starting TJ = 25°C Y = Year
(VDD = –20 Vdc, VGS = –4.5 Vdc, WW = Work Week
Peak IL = –5.0 Apk, L = 28 mH, BE = Device Code
RG = 25 Ω)
PIN ASSIGNMENT
1. Minimum FR–4 or G–10 PCB, Steady State. Source 1 1 8 Drain 1
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single Gate 1 2 7 Drain 1
sided), Steady State. Source 2 Drain 2
3 6
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. Gate 2 Drain 2
4 5
Top View
NTTD2P02R2 Micro8 4000/Tape & Reel

December, 2000 – Rev. 0 NTTD2P02R2/D
NTTD2P02R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = –8 Vdc, VDS = 0 Vdc) – – –100
(VGS = +8 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.5 –0.90 –1.4
(VGS = –4.5 Vdc, ID = –2.4 Adc) – 0.070 0.090
(VGS = –2.7 Vdc, ID = –1.2 Adc) – 0.100 0.130
(VGS = –2.5 Vdc, ID = –1.2 Adc) – 0.110 –
Forward Transconductance (VDS = –10 Vdc, ID = –1.2 Adc) gFS 2.0 4.2 – Mhos
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 200 –
f = 1.0 MHz)
10 Vdc, ID = –2.4
2.4 Adc, tr – 31 –
10 Vdc, ID = –1.2
1.2 Adc, tr – 40 –
(VDS = –16 Vdc,
ID = –2.4
2 4 Ad
Adc))
(IS = –2.4 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.75 –
(IS = –2.4
2 4 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 16 –
dIS/dt = 100 A/µs)
tb – 21 –
http://onsemi.com
242
NTTD2P02R2
4 5
VGS = –2.1 V TJ = 25°C
VDS > = 10 V

VGS = –10 V
4
3 VGS = –4.5 V
VGS = –1.9 V
VGS = –2.5 V
3
2
VGS = –1.7 V 2 TJ = 25°C
1
VGS = –1.5 V 1
TJ = 100°C
TJ = 55°C
0 0
0 2 4 6 8 10 1 1.5 2 2.5 3


0.2 0.12
TJ = 25°C TJ = 25°C
0.15 0.1
VGS = –2.7 V
0.1 0.08
VGS = –4.5 V
0.05 0.06
0 0.04
2 4 6 8 1 1.5 2 2.5 3 3.5 4 4.5
1.6 1000
ID = –2.4 A VGS = 0 V
VGS = –4.5 V TJ = 125°C
1.4 100
TJ = 100°C
(NORMALIZED)
1.2 10
TJ = 25°C
1 1
0.8 0.1
0.6 0.01
–50 –25 0 25 50 75 100 125 150 0 4 8 12 16 20

http://onsemi.com
243
NTTD2P02R2

1500 5 20
VDS = 0 V VGS = 0 V
QT 18
1200 Ciss TJ = 25°C 4 16
C, CAPACITANCE (pF)
14
900 3 VGS 12
Crss
Q1 10
Q2
600 Ciss 2 8
6
300 ID = –2.4 A
Coss 1 VDS 4
TJ = 25°C
Crss 2
0 0 0
10 5 0 5 10 15 20 0 2 4 6 8 10 12 14
1000 100
ID = –1.2 A
t, TIME (ns)
t, TIME (ns)
td
100 10 (on)
tr
tf
ID = –2.4 A
VGS = –4.5 V
td (on)
10 1.0
1.0 10 100 1.0 10 100
2
VGS = 0 V
TJ = 25°C di/dt
1.6
IS
trr
1.2
ta tb
TIME
0.8
tp 0.25 IS
0.4 IS
0

versus Current
http://onsemi.com
244
NTTD2P02R2
D = 0.5
0.2

0.1 0.1
0.0125 Ω 0.0563 Ω 0.110 Ω 0.273 Ω 0.113 Ω 0.436 Ω
0.05
0.02
0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F
Single Pulse
0.01
1E–03 1E–02 1E–01 1E+00 1E+03 1E+02 1E+03
t, TIME (s)
Figure 13. FET Thermal Response.
INFORMATION FOR USING THE Micro–8 SURFACE MOUNT PACKAGE

0.041
1.04
0.208 0.126
5.28 3.20
0.015 0.0256
0.38 0.65
inches
mm
http://onsemi.com
245
NTTD2P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
246
NTTD2P02R2

Micro–8
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
http://onsemi.com
247
#
#$%& '(
-
Single P–Channel Micro8t
Features
• Miniature Micro–8 Surface Mount Package –2.4 AMPERES
• Micro8 Mounting Information Provided –20 VOLTS
Applications RDS(on) = 90 m
Single P–Channel

Gate–to–Source Voltage – Continuous VGS ±8.0 V
Thermal Resistance – Junction–to–Ambient
(Note 1.) RθJA 160 °C/W
MARKING
DIAGRAM
Thermal Resistance – Junction–to–Ambient 8
(Note 2.) RθJA 88 °C/W
Continuous Drain Current @ TA = 70°C ID –2.6 A YWW
Micro8
Pulsed Drain Current (Note 3.) IDM –30 A AD
CASE 846A
Operating and Storage TJ, Tstg –55 to °C STYLE 1
Energy – Starting TJ = 25°C Y = Year
(VDD = –20 Vdc, VGS = –4.5 Vdc, WW = Work Week
Peak IL = –5.0 Apk, L = 28 mH, AD = Device Code
RG = 25 Ω)
PIN ASSIGNMENT
1. Minimum FR–4 or G–10 PCB, Steady State. Source 1 8 Drain
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single Source 2 7 Drain
sided), Steady State. Source Drain
3 6
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. Gate Drain
4 5
Top View
NTTS2P02R2 Micro8 4000/Tape & Reel

December, 2000 – Rev. 4 NTTS2P02R2/D
NTTS2P02R2

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = –250 µAdc) –20 – –
(VGS = –8 Vdc, VDS = 0 Vdc) – – –100
(VGS = +8 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS
(VDS = VGS, ID = –250 µAdc) –0.5 –0.90 –1.4
(VGS = –4.5 Vdc, ID = –2.4 Adc) – 0.070 0.090
(VGS = –2.7 Vdc, ID = –1.2 Adc) – 0.100 0.130
(VGS = –2.5 Vdc, ID = –1.2 Adc) – 0.110 –
Forward Transconductance (VDS = –10 Vdc, ID = –1.2 Adc) gFS 2.0 4.2 – Mhos
16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 200 –
f = 1.0 MHz)
10 Vdc, ID = –2.4
2.4 Adc, tr – 31 –
10 Vdc, ID = –1.2
1.2 Adc, tr – 40 –
(VDS = –16 Vdc,
ID = –2.4
2 4 Ad
Adc))
(IS = –2.4 Adc, VGS = 0 Vdc, TJ = 125°C) – –0.75 –
(IS = –2.4
2 4 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 16 –
dIS/dt = 100 A/µs)
tb – 21 –
http://onsemi.com
249
NTTS2P02R2
4 5
VGS = –2.1 V TJ = 25°C
VDS > = 10 V

VGS = –10 V
4
3 VGS = –4.5 V
VGS = –1.9 V
VGS = –2.5 V
3
2
VGS = –1.7 V 2 TJ = 25°C
1
VGS = –1.5 V 1
TJ = 100°C
TJ = 55°C
0 0
0 2 4 6 8 10 1 1.5 2 2.5 3


0.2 0.12
TJ = 25°C TJ = 25°C
0.15 0.1
VGS = –2.7 V
0.1 0.08
VGS = –4.5 V
0.05 0.06
0 0.04
2 4 6 8 1 1.5 2 2.5 3 3.5 4 4.5
1.6 1000
ID = –2.4 A VGS = 0 V
VGS = –4.5 V TJ = 125°C
1.4 100
TJ = 100°C
(NORMALIZED)
1.2 10
TJ = 25°C
1 1
0.8 0.1
0.6 0.01
–50 –25 0 25 50 75 100 125 150 0 4 8 12 16 20

http://onsemi.com
250
NTTS2P02R2

1500 5 20
VDS = 0 V VGS = 0 V
QT 18
1200 Ciss TJ = 25°C 4 16
C, CAPACITANCE (pF)
14
900 3 VGS 12
Crss
Q1 10
Q2
600 Ciss 2 8
6
300 ID = –2.4 A
Coss 1 VDS 4
TJ = 25°C
Crss 2
0 0 0
10 5 0 5 10 15 20 0 2 4 6 8 10 12 14
1000 100
ID = –1.2 A
t, TIME (ns)
t, TIME (ns)
td
100 10 (on)
tr
tf
ID = –2.4 A
VGS = –4.5 V
td (on)
10 1.0
1.0 10 100 1.0 10 100
2
VGS = 0 V
TJ = 25°C di/dt
1.6
IS
trr
1.2
ta tb
TIME
0.8
tp 0.25 IS
0.4 IS
0

versus Current
http://onsemi.com
251
NTTS2P02R2
D = 0.5
0.2

0.1 0.1
0.0125 Ω 0.0563 Ω 0.110 Ω 0.273 Ω 0.113 Ω 0.436 Ω
0.05
0.02
0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F
Single Pulse
0.01
1E–03 1E–02 1E–01 1E+00 1E+03 1E+02 1E+03
t, TIME (s)
Figure 13. FET Thermal Response.
INFORMATION FOR USING THE Micro–8 SURFACE MOUNT PACKAGE

0.041
1.04
0.208 0.126
5.28 3.20
0.015 0.0256
0.38 0.65
inches
mm
http://onsemi.com
252
NTTS2P02R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
253
NTTS2P02R2

Micro–8
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
http://onsemi.com
254
#!

#$%& '(
-, !
P–Channel Enhancement Mode
Single Micro8t Package http://onsemi.com
Features
• Ultra Low RDS(on) –2.48 AMPERES
• Miniature Micro8 Surface Mount Package –30 VOLTS
• Diode Exhibits High Speed, Soft Recovery 85 mW @ VGS = –10 V
• Micro8 Mounting Information Provided
Applications Single P–Channel
Cellular and Cordless Telephones and PCMCIA Cards D

G
S
8
Total Power Dissipation @ TA = 25°C PD 1.78 W Micro8
Continuous Drain Current @ TA = 25°C ID –3.75 A CASE 846A
Continuous Drain Current @ TA = 70°C ID –3.0 A STYLE 1
Junction–to–Ambient (Note 3.) RθJA 210 °C/W MARKING DIAGRAM
Total Power Dissipation @ TA = 25°C PD 0.60 W & PIN ASSIGNMENT
Continuous Drain Current @ TA = 70°C ID –1.67 A Source 1 8 Drain
Pulsed Drain Current (Note 5.) IDM –17 A Source 2 YWW 7 Drain
Thermal Resistance – Source 3 AE 6 Drain
Junction–to–Ambient (Note 4.) RθJA 100 °C/W Gate 4 5 Drain
Continuous Drain Current @ TA = 25°C ID –3.02 A (Top View)
Pulsed Drain Current (Note 5.) IDM –24 A Y = Year
WW = Work Week
Operating and Storage TJ, Tstg –55 to °C AE = Device Code
1. Minimum FR–4 or G–10 PCB, Time ≤ 10 Seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single ORDERING INFORMATION
sided), Time ≤ 10 Seconds.
3. Minimum FR–4 or G–10 PCB, Steady State. Device Package Shipping
sided), Steady State. NTTS2P03R2 Micro8 4000/Tape & Reel


February, 2001 – Rev. 0 NTTS2P03R2/D
NTTS2P03R2

Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C EAS 292.5 mJ
(VDD = –30 Vdc, VGS = –10 Vdc, Peak IL = –3.0 Apk, L = 65 mH, RG = 25 Ω)
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = –250 µAdc) V(BR)DSS –30 – – Vdc
Gate–Body Leakage Current (VGS = –20 Vdc, VDS = 0 Vdc) IGSS – – –100 nAdc
Gate–Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc
ON CHARACTERISTICS
Gate Threshold Voltage (VDS = VGS, ID = –250 µAdc) VGS(th) –1.0 –1.7 –3.0 Vdc
(VGS = –10 Vdc, ID = –2.48 Adc) – 0.063 0.085
(VGS = –4.5 Vdc, ID = –1.24 Adc) – 0.100 0.135
24 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss – 160 –
f = 1.0 MHz)
24 Vdc, ID = –2.48
2.48 Adc, tr – 20 –
Turn–Off Delay Time VGS = –10 Vdc, RG = 6.0 Ω) td(off) – 40 –
24 Vdc, ID = –1.24
1.24 Adc, tr – 40 –
(VDS = –24 Vdc,
2 48 Adc)
ID = –2.48 Ad )
(IS = –2.48 Adc, VGS = 0 Vdc, – –0.72 –
TJ = 125°C)
(IS = –1.45
1 45 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
dIS/dt = 100 A/µs)
tb – 18 –
7. Indicates Pulse Test: Pulse Width = 300 µsec max, Duty Cycle = 2%.
http://onsemi.com
256
NTTS2P03R2
3 5
–10 V –3.5 V
–3.3 V TJ = 25°C VDS ≥ –10 V

–3.7 V 4
–3.9 V –3.1 V
2 –4.1 V
–4.5 V 3
–4.9 V –2.9 V
–6 V TJ = 25°C
2
1
–2.7 V
1 TJ = 100°C
–2.5 V
TJ = –55°C
VGS = –2.3 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 1 2 3 4 5


0.3 0.15
TJ = 25°C
ID = –2.48 A
0.25
TJ = 25°C
0.2 0.1 VGS = –4.5 V
0.15
VGS = –10 V
0.1 0.05
0.05
0 0
0 2 4 6 8 10 0.5 1.5 2.5 3.5 4.5 5.5

1.6 10,000
VGS = 0 V
ID = –2.48 A
1.4
VGS = –10 V 1000 TJ = 150°C

(NORMALIZED)
1.2
100
1
TJ = 100°C
10
0.8
0.6 1
–50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30

http://onsemi.com
257
NTTS2P03R2

6 30
1200 VDS = 0 V VGS = 0 V
Ciss TJ = 25°C 5 25
C, CAPACITANCE (pF)
1000 QT
4 VGS 20
800 Q1 Q2
Crss
3 15
600 Ciss
400 2 10
ID = –2.48 A
200 Coss 1 5
TJ = 25°C
Crss VDS
0 0 0
–10 –5 0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16
100 3
2.5 VGS = 0 V
td (off)
TJ = 25°C
tf 2
t, TIME (ns)
tr
10 1.5
td (on)
1
VDD = –24 V
ID = –2.48 A 0.5
VGS = –10 V
1 0
1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1
100
VGS = 30 V
SINGLE PULSE
di/dt
TC = 25°C
10 IS
1 ms
trr
10 ms ta tb
1 TIME
tp 0.25 IS
0.1 RDS(on) LIMIT IS

dc
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 1 10 100 Figure 12. Diode Reverse Recovery Waveform

Safe Operating Area
http://onsemi.com
258
NTTS2P03R2
1000
THERMAL RESISTANCE (°C/W)
100 D = 0.5
0.2
0.1
10 0.05 *0

θ,' " ('
θ,
0.02

- .
/
0.01
/
1 '
'
'# ,*0 " *0
θ,'
- - " '&'#
SINGLE PULSE
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE

0.041
1.04
0.208 0.126
5.28 3.20
0.015 0.0256
0.38 0.65
inches
mm
http://onsemi.com
259
NTTS2P03R2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
260
NTTS2P03R2

Micro–8
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
http://onsemi.com
261
7

#$%& '(

Dual N–Channel SC–88
• 2.5 V Gate Drive with Low On–Resistance http://onsemi.com
• Low Threshold Voltage: Vth = 0.5 to 1.5 V, Ideal for Portable
• High Speed 100 mAMPS
• Enhancement Mode 20 VOLTS
• Small Package RDS(on) = 10
• Easily Designed Drive Circuits
N–Channel

Drain–to–Source Voltage VDS 20 Vdc
Gate–to–Source Voltage – Continuous VGSS 10 Vdc

Drain Current mAdc
Total Power Dissipation @ TA = 25°C PD 150 mW
Channel Temperature Tch 150 °C MARKING

Operating and Storage Temperature Tstg – 55 to °C DIAGRAM
Range 150
4
5 SC–88/SOT–363
6 N02
CASE 419B
D
STYLE 1
2 3
1
N02 = Device Code

D = Date Code
PIN ASSIGNMENT
Gate–1 2 5 Gate–2
Drain–2 3 4 Source–2
Top View
NTUD01N02 SC–88 3000 Tape & Reel


January, 2001 – Rev. 0 NTUD01N02/D
NTUD01N02

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS 20 – – Vdc
(VGS = 0 Vdc, ID = 100 µA)
Drain Cut–off Current IDSS µAdc
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = 10 Vdc, VDS = 0) IGSS – – 1.0 µAdc
ON CHARACTERISTICS
Gate Threshold Voltage Vth Vdc
(VDS = 3.0 Vdc, ID = 0.1 mAdc) 0.5 – 1.5
Drain–to–Source On–Resistance RDS(on) Ω
(VGS = 2.5 Vdc, ID = 10 mAdc) – 5.0 10
Forward Transfer Admittance (VDS = 3.0 Vdc, ID = 10 mAdc) YFS 20 – – mS
Input Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, Ciss – 5.5 – pF
f = 1.0 MHz)
Output Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, Coss – 25 –
f = 1.0 MHz)
Reverse Transfer Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, Crss – 1.6 –
f = 1.0 MHz)
Turn–On Delay Time (VDD = 3.0 Vdc, ID = 10 mAdc, ton – 0.14 – µs
Turn–Off Delay Time VGS = 0 to 2.5 Vdc) toff – 0.14 –
http://onsemi.com
263
"
Preferred Device
0
0 '(

N–Channel TO–92
MAXIMUM RATINGS http://onsemi.com

200 mAMPS
Drain Source Voltage VDSS 60 Vdc
60 VOLTS
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc
RDS(on) = 5 Ω
Gate–Source Voltage
– Continuous VGS ±?20 Vdc N–Channel
– Non–repetitive (tp ≤ 50 µs) VGSM ±?40 Vpk

Drain Current mAdc
– Continuous ID 200
– Pulsed IDM 500
Total Power Dissipation @ TC = 25°C PD 350 mW
Derate above 25°C 2.8 mW/°C

Range +150
Characteristic Symbol Max Unit
TO–92
Thermal Resistance, Junction to RθJA 357 °C/W
CASE 29
Ambient
Style 22
Maximum Lead Temperature for TL 300 °C
Soldering Purposes, 1/16″ from case 12
3
for 10 seconds
MARKING DIAGRAM
& PIN ASSIGNMENT
2N7000
YWW
1 3
Source Drain
2
Gate
Y = Year
WW = Work Week
See detailed ordering and shipping information in the package
dimensions section on page 266 of this data sheet.


November, 2000 – Rev. 5 2N7000/D
2N7000

Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS 60 – Vdc
(VGS = 0, ID = 10 µAdc)
(VDS = 48 Vdc, VGS = 0) – 1.0 µAdc
(VDS = 48 Vdc, VGS = 0, TJ = 125°C) – 1.0 mAdc
Gate–Body Leakage Current, Forward IGSSF – –10 nAdc
(VGSF = 15 Vdc, VDS = 0)

Gate Threshold Voltage VGS(th) 0.8 3.0 Vdc
(VDS = VGS, ID = 1.0 mAdc)
Static Drain–Source On–Resistance rDS(on) Ohm
(VGS = 10 Vdc, ID = 0.5 Adc) – 5.0
(VGS = 4.5 Vdc, ID = 75 mAdc) – 6.0
Drain–Source On–Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 0.5 Adc) – 2.5
(VGS = 4.5 Vdc, ID = 75 mAdc) – 0.45
On–State Drain Current Id(on) 75 – mAdc
(VGS = 4.5 Vdc, VDS = 10 Vdc)
Forward Transconductance gfs 100 – µmhos
(VDS = 10 Vdc, ID = 200 mAdc)
Input Capacitance Ciss – 60 pF
Output Capacitance ((VDS = 25 V,, VGS = 0,, Coss – 25
f=11.0
0 MH
MHz))
Reverse Transfer Crss – 5.0
Capacitance

Turn–On Delay Time (VDD = 15 V, ID = 500 mA, ton – 10 ns
Turn–Off Delay Time RG = 25 W, RL = 30 W, Vgen = 10 V) toff – 10
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
http://onsemi.com
265
2N7000
#
8 " #$° "
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9 " 8

#$°
6 7
# 9
8

:
8 6
9
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Drain–Source On–Resistance Threshold Voltage

2N7000 TO–92 1000 Unit/Box
2N7000RLRA TO–92 2000 Tape & Reel
2N7000RLRM TO–92 2000 Ammo Pack
2N7000RLRP TO–92 2000 Ammo Pack
2N7000ZL1 TO–92 2000 Ammo Pack
http://onsemi.com
266
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Preferred Device
0
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N–Channel SOT–23
MAXIMUM RATINGS
http://onsemi.com
Drain–Source Voltage VDSS 60 Vdc 115 mAMPS
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc 60 VOLTS
Drain Current ID ±?115 mAdc RDS(on) = 7.5
– Continuous TC = 25°C (Note 1.) ID ±?75
– Continuous TC = 100°C (Note 1.) IDM ±?800 N–Channel
– Pulsed (Note 2.) 4
– Continuous VGS ±?20 Vdc
– Non–repetitive (tp ≤ 50 µs) VGSM ±?40 Vpk

Total Device Dissipation FR–5 Board PD 225 mW
(Note 3.) TA = 25°C 1.8 mW/°C
#
Derate above 25°C
Thermal Resistance, Junction to Ambient RθJA 556 °C/W
3
Total Device Dissipation PD 300 mW
Alumina Substrate,(Note 4.) TA = 25°C mW/°C
Derate above 25°C 2.4 1
2
Thermal Resistance, Junction to Ambient RθJA 417 °C/W
SOT–23
Junction and Storage Temperature TJ, Tstg –?55 to °C
CASE 318
+150
STYLE 21
1. The Power Dissipation of the package may result in a lower continuous drain
current. MARKING DIAGRAM
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. & PIN ASSIGNMENT
3. FR–5 = 1.0 x 0.75 x 0.062 in.
4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina. ()%
3
702
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W = Work Week
2N7002LT1 SOT–23 3000 Tape & Reel
2N7002LT3 SOT–23 10,000 Tape & Reel


December, 2000 – Rev. 4 2N7002LT1/D
2N7002LT1

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS 60 – – Vdc
(VGS = 0, ID = 10 µAdc)
Zero Gate Voltage Drain Current TJ = 25°C IDSS – – 1.0 µAdc
(VGS = 0, VDS = 60 Vdc) TJ = 125°C – – 500
Gate–Body Leakage Current, Forward IGSSF – – 100 nAdc
(VGS = 20 Vdc)
Gate–Body Leakage Current, Reverse IGSSR – – –100 nAdc
(VGS = –?20 Vdc)

Gate Threshold Voltage VGS(th) 1.0 – 2.5 Vdc
(VDS = VGS, ID = 250 µAdc)
On–State Drain Current ID(on) 500 – – mA
(VDS ≥ 2.0 VDS(on), VGS = 10 Vdc)
Static Drain–Source On–State Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 500 mAdc) – – 3.75
(VGS = 5.0 Vdc, ID = 50 mAdc) – – 0.375
Static Drain–Source On–State Resistance rDS(on) Ohms
(VGS = 10 V, ID = 500 mAdc) TC = 25°C – – 7.5
TC = 125°C – – 13.5
(VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25°C – – 7.5
TC = 125°C – – 13.5
Forward Transconductance gFS 80 – – mmhos
(VDS ≥ 2.0 VDS(on), ID = 200 mAdc)
Input Capacitance Ciss – – 50 pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Output Capacitance Coss – – 25 pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance Crss – – 5.0 pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)

Turn–On Delay Time (VDD = 25 Vdc, ID ^ 500 mAdc, td(on) – – 20 ns
Turn–Off Delay Time RG = 25 Ω, RL = 50 Ω, Vgen = 10 V) td(off) – – 40 ns

Diode Forward On–Voltage VSD – – –1.5 Vdc
(IS = 11.5 mAdc, VGS = 0 V)
Source Current Continuous IS – – –115 mAdc
(Body Diode)
Source Current Pulsed ISM – – –800 mAdc
http://onsemi.com
268
2N7002LT1
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269
2N7002LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

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SOT–23 POWER DISSIPATION

The power dissipation of the SOT–23 is a function of the one can calculate the power dissipation of the device which
pad size. This can vary from the minimum pad size for in this case is 225 milliwatts.
soldering to a pad size given for maximum power 150°C – 25°C
PD = = 225 milliwatts
dissipation. Power dissipation for a surface mount device is 556°C/W
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from The 556°C/W for the SOT–23 package assumes the use
the device junction to ambient, and the operating of the recommended footprint on a glass epoxy printed
temperature, TA. Using the values provided on the data circuit board to achieve a power dissipation of 225
sheet for the SOT–23 package, PD can be calculated as milliwatts. There are other alternatives to achieving higher
follows: power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
TJ(max) – TA
PD = aluminum core board such as Thermal Cladt. Using a
RθJA board material such as Thermal Clad, an aluminum core
The values for the equation are found in the maximum board, the power dissipation can be doubled using the same
ratings table on the data sheet. Substituting these values footprint.
into the equation for an ambient temperature TA of 25°C,
http://onsemi.com
270
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Preferred Device
0
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N–Channel TO–92

250 mAMPS
Drain–Source Voltage VDS 200 Vdc
200 VOLTS
– Continuous VGS ±20 Vdc RDS(on) = 14 Ω (BS107)
– Non–repetitive (tp ≤ 50 µs) ±30
VGSM Vpk
RDS(on) = 6.4 Ω (BS107A)
Drain Current mAdc
Continuous (Note 1.) ID 250 N–Channel
Pulsed (Note 2.) IDM 500

Total Device Dissipation @ TA = 25°C PD 350 mW
Derate above 25°C
Operating and Storage Junction TJ, Tstg –55 to °C
Temperature Range 150
current.
2. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2.0%.
TO–92
CASE 29
Style 30
12
3
MARKING DIAGRAM
& PIN ASSIGNMENT
BS107
YWW
1 3
Drain Source
2
Gate
Y = Year
WW = Work Week


November, 2000 – Rev. 2 BS107/D
BS107, BS107A

OFF CHARACTERISTICS
Zero–Gate–Voltage Drain Current (VDS = 130 Vdc, VGS = 0) IDSS – – 30 nAdc
Drain–Source Breakdown Voltage (VGS = 0, ID = 100 µAdc) V(BR)DSX 200 – – Vdc
Gate Reverse Current (VGS = 15 Vdc, VDS = 0) IGSS – 0.01 10 nAdc
Gate Threshold Voltage (ID = 1.0 mAdc, VDS = VGS) VGS(Th) 1.0 – 3.0 Vdc
Static Drain–Source On Resistance rDS(on) Ohms
BS107 (VGS = 2.6 Vdc, ID = 20 mAdc) – – 28
(VGS = 10 Vdc, ID = 200 mAdc) – – 14
BS107A (VGS = 10 Vdc)
(ID = 100 mAdc) – 4.5 6.0
(ID = 250 mAdc) – 4.8 6.4
SMALL–SIGNAL CHARACTERISTICS
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 6.0 – pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Forward Transconductance gfs 200 400 – mmhos
Turn–On Time ton – 6.0 15 ns
Turn–Off Time toff – 12 15 ns
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http://onsemi.com
272
BS107, BS107A
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Figure 5. Transfer Characteristic Figure 6. Output Characteristic
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Figure 7. Saturation Characteristic
http://onsemi.com
273
BS107, BS107A

BS107 TO–92 1000 Unit/Box
BS107RLRA TO–92 2000 Tape & Reel
BS107RL1 TO–92 2000 Tape & Reel
BS107A TO–92 1000 Units/Box
BS107ARLRM TO–92 2000 Ammo Pack
BS107ARLRP TO–92 2000 Ammo Pack
BS107ARL1 TO–92 2000 Tape & Reel
http://onsemi.com
274
,
Preferred Device
0
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*
%+%
N–Channel TO–92
http://onsemi.com
This MOSFET is designed for high voltage, high speed switching
applications such as line drivers, relay drivers, CMOS logic, 250 mAMPS
microprocessor or TTL to high voltage interface and high voltage 200 VOLTS
display drivers.
• Low Drive Requirement, VGS = 3.0 V max RDS(on) = 8 Ω
• Inherent Current Sharing Capability Permits Easy Paralleling of N–Channel
many Devices
MAXIMUM RATINGS
Drain–Source Voltage VDSS 200 Vdc
Gate–Source Voltage VGS ±20 Vdc

Drain Current mAdc
Continuous (Note 1.) ID 250
Pulsed (Note 2.) IDM 500
Total Power Dissipation PD TO–92
@ TA = 25°C 350 mW CASE 29
Derate above TA = 25°C 6.4 mW/°C Style 30
Range +150 12
3
1. The Power Dissipation of the package may result in a lower continuous drain MARKING DIAGRAM
current. & PIN ASSIGNMENT
BS108
YWW
1 3
Drain Source
2
Gate
BS108 = Device Code
Y = Year
WW = Work Week
BS108 TO–92 1000 Units/Box
BS108ZL1 TO–92 2000 Ammo Pack


BS108

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DS – Vdc
(VGS = 0, ID = 10 µA) 200 – –
Zero Gate Voltage Drain Current IDSS nAdc
(VDSS = 130 Vdc, VGS = 0) – – 30
Gate–Body Leakage Current IGSSF nAdc
(VGS = 15 Vdc, VDS = 0) – – 10
(ID = 1.0 mA, VDS = VGS) 0.5 – 1.5
Static Drain–to–Source On–Resistance rDS(on) Ohms
(VGS = 2.0 Vdc, ID = 50 mA) – – 10
(VGS = 2.8 Vdc, ID = 100 mA) – – 8.0
Drain Cutoff Current IDSX mA
(VGS = 0.2 V, VDS = 70 V) – – 25
Input Capacitance Ciss pF
(VDS = 25 V, VGS = 0, f = 1.0 MHz) – – 150
Output Capacitance Coss pF
(VDS = 25 V, VGS = 0, f = 1.0 MHz) – – 30
Reverse Transfer Capacitance Crss pF
(VDS = 25 V, VGS = 0, f = 1.0 MHz) – – 10
Turn–On Time (See Figure 1) td(on) – – 15 ns
Turn–Off Time (See Figure 1) td(off) – – 15 ns
3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle = 2.0%.
RESISTIVE SWITCHING
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276
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Preferred Device
0
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N–Channel TO–92

500 mAMPS
Drain–Source Voltage VDS 60 Vdc
60 VOLTS
– Continuous VGS ±20 Vdc RDS(on) = 5 Ω
– Non–repetitive (tp ≤ 50 µs) VGSM ±40 Vpk
N–Channel
Drain Current (Note 1.) ID 0.5 Adc

Total Device Dissipation @ TA = 25°C PD 350 mW
Operating and Storage Junction TJ, Tstg –55 to °C
current.
TO–92
CASE 29
Style 30
12
3
MARKING DIAGRAM
& PIN ASSIGNMENT
BS170
YWW
1 3
Drain Source
2
Gate
Y = Year
WW = Work Week


BS170

OFF CHARACTERISTICS
Gate Reverse Current IGSS – 0.01 10 nAdc
(VGS = 15 Vdc, VDS = 0)
Drain–Source Breakdown Voltage V(BR)DSS 60 90 – Vdc
(VGS = 0, ID = 100 µAdc)

Gate Threshold Voltage VGS(Th) 0.8 2.0 3.0 Vdc
Static Drain–Source On Resistance rDS(on) – 1.8 5.0 Ω
(VGS = 10 Vdc, ID = 200 mAdc)
Drain Cutoff Current ID(off) – – 0.5 µA
(VDS = 25 Vdc, VGS = 0 Vdc)
Forward Transconductance gfs – 200 – mmhos
Input Capacitance Ciss – – 60 pF
(VDS = 10 Vdc, VGS = 0, f = 1.0 MHz)
(ID = 0.2 Adc) See Figure 1
Turn–Off Time toff – 4.0 10 ns
(ID = 0.2 Adc) See Figure 1

BS170 TO–92 1000 Unit/Box
BS170RLRA TO–92 2000 Tape & Reel
BS170RLRM TO–92 2000 Ammo Pack
BS170RLRP TO–92 2000 Ammo Pack
BS170RL1 TO–92 2000 Tape & Reel
BS170ZL1 TO–92 2000 Ammo Pack
http://onsemi.com
278
BS170
RESISTIVE SWITCHING
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Figure 3. VGS(th) Normalized versus Temperature Figure 4. On–Region Characteristics
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Figure 5. Output Characteristics Figure 6. Capacitance versus

Drain–To–Source Voltage
http://onsemi.com
279
!
Preferred Device
#$%& '(
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MAXIMUM RATINGS
http://onsemi.com
Drain–Source Voltage VDSS 100 Vdc 170 mAMPS
Gate–Source Voltage 100 VOLTS
– Continuous VGS ±20 Vdc
– Non–repetitive (tp ≤ 50 µs) VGSM ±40 Vpk RDS(on) = 6
Drain Current Adc N–Channel
Continuous (Note 1.) ID 0.17 4
Pulsed (Note 2.) IDM 0.68
Total Device Dissipation FR–5 PD 225 mW
Board (Note 3.)
TA = 25°C 1.8 mW/°C
Derate above 25°C
#
Thermal Resistance, Junction to RqJA 556 °C/W
Ambient MARKING
Junction and Storage Temperature TJ, Tstg –55 to +150 °C DIAGRAM
current. 3
2. Pulse Width v 300 ms, Duty Cycle v 2.0%. SOT–23 SA
3. FR–5 = 1.0 0.75 0.062 in. CASE 318 W
1 STYLE 21
2
SA = Device Code
W = Work Week
PIN ASSIGNMENT
()%
3
1 2
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BSS123LT1 SOT–23 3000 Tape & Reel
BSS123LT3 SOT–23 10,000 Tape & Reel


February, 2001 – Rev. 3 BSS123LT1/D
BSS123LT1

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS 100 – – Vdc
(VGS = 0, ID = 250 µAdc)
(VGS = 0, VDS = 100 Vdc) TJ = 25°C – – 15
TJ = 125°C – – 60
Gate–Body Leakage Current IGSS – – 50 nAdc
(VGS = 20 Vdc, VDS = 0)

Static Drain–Source On–Resistance rDS(on) – 5.0 6.0 Ω
(VGS = 10 Vdc, ID = 100 mAdc)
Forward Transconductance gfs 80 – – mmhos
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Output Capacitance Coss – 9.0 – pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 4.0 – pF
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
SWITCHING CHARACTERISTICS(4)
Turn–On Delay Time (VCC = 30 Vdc, IC = 0.28 Adc, td(on) – 20 – ns
Turn–Off Delay Time VGS = 10 Vdc, RGS = 50 Ω) td(off) – 40 – ns
REVERSE DIODE
Diode Forward On–Voltage VSD – – 1.3 V
(ID = 0.34 Adc, VGS = 0 Vdc)
4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
http://onsemi.com
281
BSS123LT1
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282
BSS123LT1

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TJ(max) – TA
http://onsemi.com
283
!,
Preferred Device
#$%& '(

Typical applications are dc–dc converters, power management in
portable and battery–powered products such as computers, printers,
PCMCIA cards, cellular and cordless telephones. http://onsemi.com
• Low Threshold Voltage (VGS(th): 0.5V...1.5V) makes it ideal for low
voltage applications 200 mAMPS
• Miniature SOT–23 Surface Mount Package saves board space 50 VOLTS
RDS(on) = 3.5
Rating Symbol Value Unit N–Channel
4
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc
Drain Current mA
– Pulsed Drain Current (tp ≤ 10 µs) IDM 800

Operating and Storage Temperature TJ, Tstg – 55 to °C
#
Range 150
Thermal Resistance – Junction–to–Ambient RθJA 556 °C/W MARKING

Maximum Lead Temperature for Soldering TL 260 °C DIAGRAM
Purposes, for 10 seconds
3
SOT–23 J1
CASE 318 W
1 STYLE 21
2
J1 = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
BSS138LT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 2 BSS138LT1/D
BSS138LT1

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc)
(VDS = 25 Vdc, VGS = 0 Vdc) – – 0.1
(VDS = 50 Vdc, VGS = 0 Vdc) – – 0.5
Gate–Source Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS – – ±0.1 µAdc
Gate–Source Threshold Voltage VGS(th) 0.5 – 1.5 Vdc
(VGS = 2.75 Vdc, ID < 200 mAdc, TA = –40°C to +85°C) – 5.6 10
(VGS = 5.0 Vdc, ID = 200 mAdc) – – 3.5
Forward Transconductance gfs 100 – – mmhos
(VDS = 25 Vdc, ID = 200 mAdc, f = 1.0 kHz)
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1 MHz) Ciss – 40 50 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1 MHz) Coss – 12 25
Transfer Capacitance (VDG = 25 Vdc, VGS = 0, f = 1 MHz) Crss – 3.5 5.0

Turn–On Delay Time td(on) – – 20 ns
(VDD = 30 Vdc
Vdc, ID = 0.2
0 2 Adc,)
Adc )
Turn–Off Delay Time td(off) – – 20
http://onsemi.com
285
BSS138LT1
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http://onsemi.com
287
BSS138LT1

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drain pad size. This can vary from the minimum pad size in this case is 225 milliwatts.
for soldering to a pad size given for maximum power 150°C – 25°C
TJ(max) – TA
http://onsemi.com
288
,
Preferred Device
#$%& '(
!
P–Channel SOT–23
These miniature surface mount MOSFETs reduce power loss
conserve energy, making this device ideal for use in small power
management circuitry. Typical applications are dc–dc converters, load http://onsemi.com
switching, power management in portable and battery–powered
products such as computers, printers, cellular and cordless telephones. 130 mAMPS
• Energy Efficient 50 VOLTS
• Miniature SOT–23 Surface Mount Package Saves Board Space RDS(on) = 10

Drain Current mA
ID 130
– Continuous @ TA = 25°C
#
Range 150
MARKING
Thermal Resistance – Junction–to–Ambient RθJA 556 °C/W DIAGRAM
Purposes, for 10 seconds 3
SOT–23 PD
CASE 318 W
1 STYLE 21
2
PD = Device Code
W = Work Week
PIN ASSIGNMENT
3
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November, 2000 – Rev. 2 BSS84LT1/D
BSS84LT1

OFF CHARACTERISTICS
(VDS = 25 Vdc, VGS = 0 Vdc) – – 0.1
(VDS = 50 Vdc, VGS = 0 Vdc) – – 15
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS – – ±60 µAdc
Gate–Source Threaded Voltage VGS(th) 0.8 – 2.0 Vdc
Static Drain–to–Source On–Resistance rDS(on) – 5.0 10 Ohms
(VGS = 5.0 Vdc, ID = 100 mAdc)
Transfer Admittance |yfs| 50 – – mS
(VDS = 25 Vdc, ID = 100 mAdc, f = 1.0 kHz)
Input Capacitance (VDS = 5.0 Vdc) Ciss – 30 – pF
Output Capacitance (VDS = 5.0 Vdc) Coss – 10 –
Transfer Capacitance (VDG = 5.0 Vdc) Crss – 5.0 –

15 Vdc, ID = –2.5
2.5 Adc, tr – 1.0 –
Turn–Off Delay Time RL = 50 Ω) td(off) – 16 –
Gate Charge QT – 6000 – pC
Continuous Current IS – – 0.130 A
Pulsed Current ISM – – 0.520
Forward Voltage (Note 2.) VSD – 2.5 – V

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Figure 1. Transfer Characteristics Figure 2. On–Region Characteristics
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290
BSS84LT1

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Figure 7. Body Diode Forward Voltage
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291
BSS84LT1

4:
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7$
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#
4$
7
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8

TJ(max) – TA
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292
#!
!
Preferred Device

!
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features http://onsemi.com
protection for use in inductive coil drivers applications. Primary uses 15 AMPERES
include Ignition, Direct Fuel Injection, or wherever high voltage and 350 VOLTS (Clamped)
VCE(on) @ 10 A = 1.8 V Max
• Ideal for Coil–On–Plug, IGBT–On–Coil, or Distributorless Ignition
System Applications N–Channel
• High Pulsed Current Capability up to 50 A C
• Gate–Emitter ESD Protection
G RG
Stress Applied to Load
• Integrated ESD Diode Protection RGE
Microprocessor Devices 4
• Low Saturation Voltage E
• Optional Gate Resistor (RG) 4
1 2
3
TO–220AB D2PAK
Collector–Emitter Voltage VCES 380 VDC CASE 221A CASE 418B
STYLE 9 STYLE 4
Collector–Gate Voltage VCER 380 VDC 1
2
Gate–Emitter Voltage VGE 22 VDC 3 MARKING DIAGRAMS
& PIN ASSIGNMENTS
4 4
@ TC = 25°C – Pulsed 50 AAC
Collector Collector
ESD (Human Body Model) ESD kV
R = 1500 Ω, C = 100 pF 8.0
ESD (Machine Model) R = 0 Ω, C = 200 pF ESD 800 V G15N35CL
YWW
Total Power Dissipation @ TC = 25°C PD 150 Watts G15N35CL
Derate above 25°C 1.0 W/°C YWW
1 3
Operating and Storage Temperature Range TJ, Tstg –55 to °C Gate Emitter
1 3 2
175
Gate Emitter Collector
UNCLAMPED COLLECTOR–TO–EMITTER AVALANCHE
CHARACTERISTICS (–55°C ≤ TJ ≤ 175°C) 2
G15N35CL = Device Code
Collector
Y = Year
WW = Work Week
Single Pulse Collector–to–Emitter Avalanche EAS mJ
Energy ORDERING INFORMATION
VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L 300
= 2.0 mH, Starting TJ = 25°C Device Package Shipping
VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L 200
MGP15N35CL TO–220 50 Units/Rail
= 2.0 mH, Starting TJ = 150°C
MGB15N35CLT4 D2PAK 800 Tape & Reel
Reverse Avalanche Energy EAS(R) mJ
VCC = 100 V, VGE = 20 V, L = 3.0 mH, 1000
Pk IL = 25.8 A, Starting TJ = 25°C Preferred devices are recommended choices for future use

March, 2001 – Rev. 4 MGP15N35CL/D
MGP15N35CL, MGB15N35CL
Thermal Resistance, Junction to Case RθJC 1.0 °C/W
Thermal Resistance, Junction to Ambient TO–220 RθJA 62.5
D2PAK (Note 1.) RθJA 50

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter
Collector Emitter Clamp
Clam Voltage BVCES IC = 2.0 mA TJ = –40°C
40 C to 320 350 380 VDC
150°C
IC = 10 mA TJ = –40°C to 330 360 380
150°C
Zero Gate Voltage

g Collector Current ICES TJ = 25°C – 1.5 20 µADC
µ
VCE = 300 V,
V
TJ = 150°C – 10 40*
VGE = 0 V
TJ = –40°C – 0.7 1.5
Reverse Collector–Emitter Leakage
g Current IECS TJ = 25°C – 0.35 1.0 mA
VCE = –24
24 V
TJ = 150°C – 8.0 15*
TJ = –40°C – 0.05 0.5
Reverse Collector–Emitter Clamp Voltage
g BVCES(R) TJ = 25°C 25 33 50 VDC
IC = –75
75 mA
A
TJ = 150°C 25 36 50
TJ = –40°C 25 30 50
Gate–Emitter Clamp Voltage BVGES IG = 5.0 mA TJ = –40°C to 17 20 22 VDC
150°C
Gate–Emitter Leakage Current IGES VGE = 10 V TJ = –40°C to 384 600 1000 µADC
150°C
Gate Resistor (Optional) RG – TJ = –40°C to – 70 – Ω
150°C
Gate Emitter Resistor RGE – TJ = –40°C to 10 16 26 kΩ
150°C
g
Gate Threshold Voltage VGE(th) TJ = 25°C 1.4 1.7 2.0 VDC
IC = 1.0
1 0 mA,
A
TJ = 150°C 0.75 1.1 1.4
VGE = VCE
TJ = –40°C 1.6 1.9 2.1*
Threshold Temperature Coefficient – – – – 4.4 – mV/°C
(Negative)
*Maximum Value of Characteristic across Temperature Range.
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ELECTRICAL CHARACTERISTICS (continued)

ON CHARACTERISTICS (continued) (Note 3.)
g
Collector–to–Emitter On–Voltage VCE(on) TJ = 25°C 1.0 1.3 1.6 VDC
IC = 6.0
6 0 A,
A
TJ = 150°C 0.9 1.2 1.5
VGE = 4.0 V
TJ = –40°C 1.1 1.4 1.7*
TJ = 25°C 1.3 1.6 1.9
IC = 10 A,
A
TJ = 150°C 1.2 1.5 1.8
VGE = 4.0 V
TJ = –40°C 1.3 1.6 1.9*
TJ = 25°C 1.6 1.95 2.25
IC = 15 A,
A
TJ = 150°C 1.7 2.0 2.3*
VGE = 4.0 V
TJ = –40°C 1.6 1.9 2.2
TJ = 25°C 1.9 2.2 2.5
IC = 20 A,
A
TJ = 150°C 2.1 2.4 2.7*
VGE = 4.0 V
TJ = –40°C 1.85 2.15 2.45
TJ = 25°C 2.1 2.5 2.9
IC = 25 A,
A
TJ = 150°C 2.5 2.9 3.3*
VGE = 4.0 V
TJ = –40°C 2.0 2.4 2.8
Collector–to–Emitter On–Voltage VCE(on) IC = 10 A, VGE = 4.5 V TJ = 150°C – 1.5 1.8 VDC
Forward Transconductance gfs VCE = 5.0 V, IC = 6.0 A TJ = –40°C to 8.0 15 25 Mhos
150°C
Input Capacitance CISS – 1000 1300 pF
VCC = 25 VV, VGE = 0 V TJ = –40°C
40°C to
Output Capacitance COSS – 100 130
f = 1.0 MHz 150°C
Transfer Capacitance CRSS – 5.0 8.0
Turn–Off Delayy Time (Inductive)
( ) td(off) VCC = 300 V,, IC = 6.5 A TJ = 25°C – 4.0 10 µSec
µ
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 4.5 10
Fall Time ((Inductive)) tf VCC = 300 V,, IC = 6.5 A TJ = 25°C – 7.0 10
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 10 15*
Turn–Off Delay
y Time ((Resistive)) td(off) VCC = 300 V,, IC = 6.5 A TJ = 25°C – 4.0 10 µSec
µ
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ Ω,
TJ = 150°C – 4.5 10
Fall Time ((Resistive)) tf VCC = 300 V,, IC = 6.5 A TJ = 25°C – 13 20
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ Ω,
TJ = 150°C – 16 20
Turn–On Delay
y Time td(on) VCC = 10 V,, IC = 6.5 A TJ = 25°C – 1.0 1.5 µSec
µ
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 1.0 1.5
Rise Time tr VCC = 10 V,, IC = 6.5 A TJ = 25°C – 4.5 6.0
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 5.0 6.0
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295
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60 60
IC, COLLECTOR CURRENT (AMPS)

VGE = 10.0 V VGE = 4.5 V VGE = 10.0 V VGE = 4.5 V
50 50
VGE = 5.0 V VGE = 5.0 V
40 VGE = 4.0 V 40
VGE = 4.0 V
30 TJ = 25°C 30 TJ = 150°C
VGE = 3.5 V VGE = 3.5 V
20 20
VGE = 3.0 V
VGE = 3.0 V
10 10 VGE = 2.5 V
VGE = 2.5 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
Figure 1. Output Characteristics Figure 2. Output Characteristics
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

30 4.0
3.5 VGE = 5.0 V

25 VCE = 10 V
3.0 IC = 25 A
IC = 20 A
20
2.5
15 2.0
TJ = 150°C
1.5
10
TJ = 25°C 1.0 IC = 15 A IC = 5 A
5 TJ = –40°C
0.5
IC = 10 A
0 0.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –50 –25 0 25 50 75 100 125 150
VGE, GATE TO EMITTER VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Transfer Characteristics Figure 4. Collector–to–Emitter Saturation

Voltage vs. Junction Temperature
10000 2.5
Mean + 4 σ
THRESHOLD VOLTAGE (VOLTS)
IC = 1 mA
Mean
Ciss 2.0
C, CAPACITANCE (pF)
1000
1.5
Coss
100 Mean – 4 σ
1.0
10
Crss
0.5
1 0.0
0 20 40 60 80 100 120 140 160 180 200 –50 –25 0 25 50 75 100 125 150
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TEMPERATURE (°C)
Figure 5. Capacitance Variation Figure 6. Threshold Voltage vs. Temperature
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296
30 30
VCC = 50 V VCC = 50 V
IL, LATCH CURRENT (AMPS)

25 VGE = 5.0 V 25 VGE = 5.0 V
RG = 1000 Ω RG = 1000 Ω
20 20 L = 2.0 mH
T = 25°C
15 15
L = 3.0 mH
10 10
T = 150°C L = 6.0 mH
5 5
0 0
0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 150 175
INDUCTOR (mH) TEMPERATURE (°C)
Figure 7. Minimum Open Secondary Latch Figure 8. Minimum Open Secondary Latch
Current vs. Inductor Current vs. Temperature
30 30
VCC = 50 V
VCC = 50 V
T = 25°C VGE = 5.0 V
25 VGE = 5.0 V IL, LATCH CURRENT (AMPS) 25 L = 2.0 mH

RG = 1000 Ω
RG = 1000 Ω
20 20
L = 3.0 mH
15 T = 150°C 15
L = 6.0 mH
10 10
5 5
0 0
0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 150 175
Figure 9. Typical Open Secondary Latch Figure 10. Typical Open Secondary Latch
12 14
VCC = 300 V
VGE = 5.0 V 12 tf
10
RG = 1000 Ω
SWITCHING TIME (µS)
tf
IC = 10 A 10 VCC = 300 V
8 L = 300 µH VGE = 5.0 V
8 RG = 1000 Ω
6 td(off) TJ = 150°C td(off)
6 L = 300 µH
4
4
2 2
0 0
–50 –25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 16
TC, CASE TEMPERATURE (°C) IC, COLLECTOR CURRENT (AMPS)
Figure 11. Switching Speed vs. Case Figure 12. Switching Speed vs. Collector
Temperature Current
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297
14 14
VCC = 300 V
12 VGE = 5.0 V 12 tf
TJ = 25°C

10 IC = 10 A 10
L = 300 µH VCC = 300 V
8 8 VGE = 5.0 V
tf TJ = 150°C
6 6 IC = 10 A
L = 300 µH td(off)
4 td(off) 4
2 2
0 0
250 500 750 1000 250 500 750 1000
RG, EXTERNAL GATE RESISTANCE (Ω) RG, EXTERNAL GATE RESISTANCE (Ω)
Figure 13. Switching Speed vs. External Gate Figure 14. Switching Speed vs. External Gate
Resistance Resistance
10
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt)
Duty Cycle = 0.5
1 0.2
0.1
0.05
0.02
0.1
D CURVES APPLY FOR POWER
0.01 P(pk)
PULSE TRAIN SHOWN
t1 READ TIME AT T1
Single Pulse
t2 TJ(pk) – TA = P(pk) RθJA(t)
RθJC ≅ R(t) for t ≤ 0.2 s
DUTY CYCLE, D = t1/t2
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t,TIME (S)
Figure 15. Transient Thermal Resistance

(Non–normalized Junction–to–Ambient mounted on
fixture in Figure 16)
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298
1.5″
4″
4″
0.125″
4″
Figure 16. Test Fixture for Transient Thermal Curve

(48 square inches of 1/8, thick aluminum)
100 100
COLLECTOR CURRENT (AMPS)
DC DC
10 100 µs 10
100 µs
1 ms
1 10 ms 1 1 ms
100 ms 10 ms
100 ms
0.1 0.1
0.01 0.01
1 10 100 1000 1 10 100 1000
COLLECTOR–EMITTER VOLTAGE (VOLTS) COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 17. Single Pulse Safe Operating Area Figure 18. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 255C) (Mounted on an Infinite Heatsink at TC = 1255C)
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299
100 100

t1 = 1 ms, D = 0.05 t1 = 1 ms, D = 0.05

DC DC
t1 = 2 ms, D = 0.10 t1 = 2 ms, D = 0.10
10 10
t1 = 3 ms, D = 0.30
t1 = 3 ms, D = 0.30
1 1
P(pk) P(pk)
t1 t1
0.1 0.1
t2 t2
DUTY CYCLE, D = t1/t2 DUTY CYCLE, D = t1/t2
0.01 0.01
1 10 100 1000 1 10 100 1000
Figure 19. Pulse Train Safe Operating Area Figure 20. Pulse Train Safe Operating Area
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300
#

Preferred Device

VCE(on) @ 10 A = 1.8 V Max
• Ideal for Coil–On–Plug, IGBT–On–Coil, or Distributorless Ignition
System Applications N–Channel
Stress Applied to Load G RG
• Integrated ESD Diode Protection

RGE
Microprocessor Devices
4
• Optional Gate Resistor (RG) 4
1 2
3
TO–220AB D2PAK
STYLE 9 STYLE 4
2
& PIN ASSIGNMENTS
@ TC = 25°C – Pulsed 50 AAC 4 4
Collector Collector
R = 1500 Ω, C = 100 pF 8.0
YWW
Total Power Dissipation @ TC = 25°C PD 150 Watts G15N40CL
Derate above 25°C 1.0 W/°C YWW
1 3
Gate 2 Emitter
175 1 3
CHARACTERISTICS (–55°C ≤ TJ ≤ 175°C) 2 G15N40CL = Device Code
Collector Y = Year
WW = Work Week
Energy ORDERING INFORMATION
VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L 300
= 2.0 mH, Starting TJ = 25°C Device Package Shipping
VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L 200
MGP15N40CL TO–220 50 Units/Rail
= 2.0 mH, Starting TJ = 150°C
Reverse Avalanche Energy EAS(R) mJ MGB15N40CLT4 D2PAK 800 Tape & Reel
VCC = 100 V, VGE = 20 V, L = 3.0 mH, 1000
Pk IL = 25.8 A, Starting TJ = 25°C Preferred devices are recommended choices for future use

OFF CHARACTERISTICS
Collector–Emitter
Collector Emitter Clamp
Clam Voltage BVCES IC = 2.0 mA TJ = –40°C
40 C to 320 350 380 VDC
150°C
IC = 10 mA TJ = –40°C to 330 360 380
150°C
Zero Gate Voltage

µ
VCE = 300 V,
V
TJ = 150°C – 10 40*
VGE = 0 V
TJ = –40°C – 0.7 1.5
VCE = –24
24 V
TJ = 150°C – 8.0 15*
TJ = –40°C – 0.05 0.5
g BVCES(R) TJ = 25°C 25 33 50 VDC
IC = –75
75 mA
A
TJ = 150°C 25 36 50
TJ = –40°C 25 30 50
150°C
150°C
150°C
150°C
g
IC = 1.0
1 0 mA,
A
TJ = 150°C 0.75 1.1 1.4
VGE = VCE
TJ = –40°C 1.6 1.9 2.1*
(Negative)
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302

g
IC = 6.0
6 0 A,
A
TJ = 150°C 0.9 1.2 1.5
VGE = 4.0 V
TJ = –40°C 1.1 1.4 1.7*
TJ = 25°C 1.3 1.6 1.9
IC = 10 A,
A
TJ = 150°C 1.2 1.5 1.8
VGE = 4.0 V
TJ = –40°C 1.3 1.6 1.9*
TJ = 25°C 1.6 1.95 2.25
IC = 15 A,
A
TJ = 150°C 1.7 2.0 2.3*
VGE = 4.0 V
TJ = –40°C 1.6 1.9 2.2
TJ = 25°C 1.9 2.2 2.5
IC = 20 A,
A
TJ = 150°C 2.1 2.4 2.7*
VGE = 4.0 V
TJ = –40°C 1.85 2.15 2.45
TJ = 25°C 2.1 2.5 2.9
IC = 25 A,
A
TJ = 150°C 2.5 2.9 3.3*
VGE = 4.0 V
TJ = –40°C 2.0 2.4 2.8
150°C
VCC = 25 VV, VGE = 0 V TJ = –40°C
40°C to
f = 1.0 MHz 150°C
( ) td(off) VCC = 300 V,, IC = 6.5 A TJ = 25°C – 4.0 10 µSec
µ
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 4.5 10
Fall Time ((Inductive)) tf VCC = 300 V,, IC = 6.5 A TJ = 25°C – 7.0 10
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 10 15*
Turn–Off Delay
µ
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ Ω,
TJ = 150°C – 4.5 10
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ Ω,
TJ = 150°C – 16 20
Turn–On Delay
µ
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 1.0 1.5
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 5.0 6.0
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303
60 60

VGE = 10.0 V VGE = 4.5 V VGE = 10.0 V VGE = 4.5 V
50 50
VGE = 5.0 V VGE = 5.0 V
40 VGE = 4.0 V 40
VGE = 4.0 V
30 TJ = 25°C 30 TJ = 150°C
VGE = 3.5 V VGE = 3.5 V
20 20
VGE = 3.0 V
VGE = 3.0 V
10 10 VGE = 2.5 V
VGE = 2.5 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

30 4.0
3.5 VGE = 5.0 V

25 VCE = 10 V
3.0 IC = 25 A
IC = 20 A
20
2.5
15 2.0
TJ = 150°C
1.5
10
TJ = 25°C 1.0 IC = 15 A IC = 5 A
5 TJ = –40°C
0.5
IC = 10 A
0 0.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –50 –25 0 25 50 75 100 125 150

10000 2.5
Mean + 4 σ
IC = 1 mA
Mean
Ciss 2.0
C, CAPACITANCE (pF)
1000
1.5
Coss
100 Mean – 4 σ
1.0
10
Crss
0.5
1 0.0
0 20 40 60 80 100 120 140 160 180 200 –50 –25 0 25 50 75 100 125 150
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304
30 30
VCC = 50 V VCC = 50 V

25 VGE = 5.0 V 25 VGE = 5.0 V
RG = 1000 Ω RG = 1000 Ω
20 20 L = 2.0 mH
T = 25°C
15 15
L = 3.0 mH
10 10
T = 150°C L = 6.0 mH
5 5
0 0
0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 150 175
30 30
VCC = 50 V
VCC = 50 V
T = 25°C VGE = 5.0 V
25 VGE = 5.0 V IL, LATCH CURRENT (AMPS) 25 L = 2.0 mH

RG = 1000 Ω
RG = 1000 Ω
20 20
L = 3.0 mH
15 T = 150°C 15
L = 6.0 mH
10 10
5 5
0 0
0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 150 175
Figure 9. Typical Open Secondary Latch Figure 10. Typical Open Secondary Latch
12 14
VCC = 300 V
VGE = 5.0 V 12 tf
10
RG = 1000 Ω
tf
IC = 10 A 10 VCC = 300 V
8 L = 300 µH VGE = 5.0 V
8 RG = 1000 Ω
6 td(off) TJ = 150°C td(off)
6 L = 300 µH
4
4
2 2
0 0
–50 –25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 16
Temperature Current
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305
14 14
VCC = 300 V
12 VGE = 5.0 V 12 tf
TJ = 25°C

10 IC = 10 A 10
L = 300 µH VCC = 300 V
8 8 VGE = 5.0 V
tf TJ = 150°C
6 6 IC = 10 A
L = 300 µH td(off)
4 td(off) 4
2 2
0 0
250 500 750 1000 250 500 750 1000
RG, EXTERNAL GATE RESISTANCE (Ω) RG, EXTERNAL GATE RESISTANCE (Ω)
Figure 13. Switching Speed vs. External Gate Figure 14. Switching Speed vs. External Gate
Resistance Resistance
10
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt)
Duty Cycle = 0.5
1 0.2
0.1
0.05
0.02
0.1 D CURVES APPLY FOR POWER
0.01 P(pk)
PULSE TRAIN SHOWN
t1 READ TIME AT T1
Single Pulse
RθJC ≅ R(t) for t ≤ 0.2 s
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t,TIME (S)

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306
1.5″
4″
4″
0.125″
4″

100 100
DC DC
10 100 µs 10
100 µs
1 ms
1 10 ms 1 1 ms
100 ms 10 ms
100 ms
0.1 0.1
0.01 0.01
1 10 100 1000 1 10 100 1000
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307
100 100

t1 = 1 ms, D = 0.05 t1 = 1 ms, D = 0.05

DC DC
t1 = 2 ms, D = 0.10 t1 = 2 ms, D = 0.10
10 10
t1 = 3 ms, D = 0.30
t1 = 3 ms, D = 0.30
1 1
P(pk) P(pk)
t1 t1
0.1 0.1
t2 t2
0.01 0.01
1 10 100 1000 1 10 100 1000
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#)!
)!
Preferred Device

) !
VCE(on) @ 10 A = 1.8 V Max
• Ideal for IGBT–On–Coil or Distributorless Ignition System
Applications N–Channel
Stress Applied to Load G
• Integrated ESD Diode Protection RGE
Microprocessor Devices 4
4
• Optional Gate Resistor (RG)
1 2
3
TO–220AB D2PAK
STYLE 9 STYLE 4
2
& PIN ASSIGNMENTS
Collector Current – Continuous IC 19 ADC
@ TC = 25°C – Pulsed 50 AAC 4 4
Collector Collector
R = 1500 Ω, C = 100 pF 8.0
YWW
Total Power Dissipation @ TC = 25°C PD 165 Watts
G19N35CL
YWW
Operating and Storage Temperature Range TJ, Tstg –55 to °C 1 3
175 Gate 2 Emitter
1 3
CHARACTERISTICS (–55°C ≤ TJ ≤ 175°C) 2
G19N35CL = Device Code
Collector
Characteristic Symbol Value Unit Y = Year
WW = Work Week
Energy
VCC = 50 V, VGE = 5.0 V, Pk IL = 22.4 A, 500
L = 2.0 mH, Starting TJ = 25°C Device Package Shipping
VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, 300
L = 2.0 mH, Starting TJ = 150°C MGP19N35CL TO–220 50 Units/Rail
Reverse Avalanche Energy EAS(R) mJ MGB19N35CLT4 D2PAK 800 Tape & Reel
VCC = 100 V, VGE = 20 V, L = 3.0 mH, 1000
Pk IL = 25.8 A, Starting TJ = 25_C Preferred devices are recommended choices for future use

OFF CHARACTERISTICS
Collector–Emitter Clamp Voltage BVCES IC = 2.0 mA TJ = –40°C to 320 350 380 VDC
150°C
IC = 10 mA TJ = –40°C to 330 360 380
150°C
Zero Gate Voltage

µ
VCE = 300 V,
V
TJ = 150°C – 15 40*
VGE = 0 V
TJ = –40°C – 0.7 1.5
VCE = –24
24 V
TJ = 150°C – 10 20*
TJ = –40°C – 0.05 0.5
g BVCES(R) TJ = 25°C 25 33 50 VDC
IC = –75
75 mA
A
TJ = 150°C 25 36 50
TJ = –40°C 25 30 50
150°C
150°C
150°C
150°C
g
IC = 1.0
1 0 mA,
A
TJ = 150°C 0.75 1.1 1.4
VGE = VCE
TJ = –40°C 1.6 1.9 2.1*
(Negative)
http://onsemi.com
310

g
IC = 6.0
6 0 A,
A
TJ = 150°C 0.8 1.05 1.4
VGE = 4.0 V
TJ = –40°C 1.15 1.4 1.75*
TJ = 25°C 1.2 1.5 1.8
IC = 10 A,
A
TJ = 150°C 1.0 1.3 1.6
VGE = 4.0 V
TJ = –40°C 1.3 1.6 1.9*
TJ = 25°C 1.5 1.75 2.1
IC = 15 A,
A
TJ = 150°C 1.35 1.65 1.95
VGE = 4.0 V
TJ = –40°C 1.5 1.8 2.1*
TJ = 25°C 1.7 2.0 2.3
IC = 20 A,
A
TJ = 150°C 1.6 1.9 2.2
VGE = 4.0 V
TJ = –40°C 1.7 2.0 2.3*
TJ = 25°C 2.0 2.25 2.6
IC = 25 A,
A
TJ = 150°C 2.0 2.3 2.7*
VGE = 4.0 V
TJ = –40°C 2.0 2.2 2.6
150°C
VCC = 25 VV, VGE = 0 V TJ = –40°C
40°C to
f = 1.0 MHz 150°C
( ) td(off) VCC = 300 V,, IC = 10 A TJ = 25°C – 5.0 10 µSec
µ
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 6.0 10
Fall Time ((Inductive)) tf VCC = 300 V,, IC = 10 A TJ = 25°C – 6.0 10
RG = 1
1.0 kΩ, L = 300 µH
0 kΩ H
TJ = 150°C – 11 15*
Turn–Off Delay
µ
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ
TJ = 150°C – 7.0 10
RG = 1
1.0 kΩ, RL = 46 Ω
0 kΩ
TJ = 150°C – 18 22*
Turn–On Delay
µ
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 1.5 2.0
RG = 1
1.0
0 kΩ
kΩ, RL = 1 5Ω
1.5
TJ = 150°C – 5.0 6.0
http://onsemi.com
311
60 60
VGE = 4.5 V

VGE = 10.0 V VGE = 10.0 V
VGE = 4.0 V
50 50
VGE = 5.0 V VGE = 5.0 V VGE = 4.0 V
40 40
TJ = 25°C VGE = 4.5 V VGE = 3.5 V TJ = 150°C VGE = 3.5 V
30 30
VGE = 3.0 V
20 VGE = 3.0 V 20
VGE = 2.5 V
10 VGE = 2.5 V 10
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

60 3.0
55 VCE = 10 V VGE = 5.0 V

50 2.5
IC = 20 A IC = 25 A
45
40 2.0
35
30 1.5
25
20 TJ = 25°C 1.0
IC = 15 A
15 IC = 5 A
10 TJ = 150°C 0.5 IC = 10 A
5 TJ = –40°C
0 0.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –50 –25 0 25 50 75 100 125 150

10000 2.5
Ciss IC = 1 mA
Mean + 4 σ
1000 2.0 Mean
C, CAPACITANCE (pF)
Coss
100 1.5
Mean – 4 σ
10 Crss 1.0
1 0.5
0 0.0
0 20 40 60 80 100 120 140 160 180 –50 –25 0 25 50 75 100 125 150
http://onsemi.com
312
14 14
VCC = 300 V
12 VGE = 5.0 V 12 tf
RG = 1000 Ω

10 IC = 10 A 10
L = 300 µH tf
8 8
td(off)
6 td(off) 6
VCC = 300 V
4 4 VGE = 5.0 V
RG = 1000 Ω
2 2 TJ = 150°C
L = 300 µH
0 0
–50 –25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 16
Temperature Current
30 30
VCC = 50 V
25 VGE = 5.0 V IL, LATCH CURRENT (AMPS) 25

RG = 1000 Ω L = 2.0 mH
T = 25°C
20 20
15 15 L = 3.0 mH
T = 150°C
10 10 L = 6.0 mH
VCC = 50 V
5 5 VGE = 5.0 V
RG = 1000 Ω
0 0
0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 150 175
30 30
VCC = 50 V L = 2.0 mH
25 T = 25°C VGE = 5.0 V 25

RG = 1000 Ω
L = 3.0 mH
20 20
L = 6.0 mH
15 T = 150°C 15
10 10
VCC = 50 V
5 5 VGE = 5.0 V
RG = 1000 Ω
0 0
0 1 2 3 4 5 6 7 8 9 10 –50 –25 0 25 50 75 100 125 150 175
Figure 11. Typical Open Secondary Latch vs. Figure 12. Typical Open Secondary Latch vs.
Inductor Temperature
http://onsemi.com
313
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt) 10
Duty Cycle = 0.5
1 0.2
0.1
0.05
0.02
0.1 D CURVES APPLY FOR POWER
P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT T1

Single Pulse RθJC ≅ R(t) for t ≤ 0.2 s
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t,TIME (S)

1.5″
4″
4″
0.125″
4″

http://onsemi.com
314
100 100

DC DC
100 µs
10 10 100 µs
1 ms
1 10 ms 1
1 ms
100 ms 10 ms
0.1 0.1 100 ms
0.01 0.01
1 10 100 1000 1 10 100 1000
100 100
t1 = 1 ms
DC D = 0.05 DC
t1 = 1 ms
10 t1 = 2 ms 10 D = 0.05
D = 0.10
t1 = 3 ms t1 = 3 ms t1 = 2 ms
D = 0.30 D = 0.30 D = 0.10
1 1
P(pk) P(pk)
t1 t1
0.1 0.1
t2 t2

0.01 0.01
1 10 100 1000 1 10 100 1000
http://onsemi.com
315
(
Preferred Device
#$%& '(
"
These miniature surface mount MOSFETs low RDS(on) assure
minimal power loss and conserve energy, making these devices ideal
for use in space sensitive power management circuitry. Typical http://onsemi.com
applications are dc–dc converters and power management in portable
and battery–powered products such as computers, printers, PCMCIA 750 mAMPS
cards, cellular and cordless telephones. 20 VOLTS
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 85 m
• Miniature SOT–23 Surface Mount Package Saves Board Space
N–Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 4
Gate–to–Source Voltage – Continuous VGS ± 8.0 Vdc

Drain Current mA
Total Power Dissipation @ TA = 25°C PD 400 mW #
Operating and Storage Temperature TJ, Tstg – 55 to °C MARKING

Range 150
DIAGRAM
Thermal Resistance – Junction–to–Ambient RθJA 300 °C/W
Maximum Lead Temperature for Soldering TL 260 °C 3
Purposes, 1/8″ from case for 10 SOT–23 NE
seconds CASE 318 W
1 STYLE 21
2
NE = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
MGSF1N02ELT1 SOT–23 3000 Tape & Reel
MGSF1N02ELT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 1 MGSF1N02ELT1/D
MGSF1N02ELT1

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 10 µA)
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Source Leakage Current (VGS = ± 8.0 Vdc, VDS = 0 Vdc) IGSS – – ±0.1 µAdc
Gate–Source Threshold Voltage VGS(th) 0.5 – 1.0 Vdc
(VGS = 4.5 Vdc, ID = 1.0 A) – – 0.085
(VGS = 2.5 Vdc, ID = 0.75 A) – – 0.115
Input Capacitance (VDS = 5.0 Vdc, VGS = 0 Ciss – 160 – pF
V, f = 1.0 Mhz)
Output Capacitance (VDS = 5.0 Vdc, VGS = 0 Coss – 130 –
V, f = 1.0 Mhz)
Transfer Capacitance (VDG = 5.0 Vdc, VGS = 0 Crss – 60 –
V, f = 1.0 Mhz)

Turn–Off Delay Time RL = 5 Ω, RG = 6 Ω) td(off) – 117 –
Total Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, QT – 6500 – pC
VGS = 4.0 Vdc)

Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) VSD – – 1.2 V
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http://onsemi.com
318
MGSF1N02ELT1

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319
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N–Channel

Drain Current
– Continuous @ TA = 25°C ID 750 mA

Range 150
DIAGRAM
Purposes, 1/8″ from case for 10 SOT–23 N2
seconds CASE 318 W
1 STYLE 21
2
N2 = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
MGSF1N02LT1 SOT–23 3000 Tape & Reel
MGSF1N02LT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 3 MGSF1N02LT1/D
MGSF1N02LT1

OFF CHARACTERISTICS
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS – – ±100 nAdc
Gate Threshold Voltage VGS(th) 1.0 1.7 2.4 Vdc
(VGS = 10 Vdc, ID = 1.2 Adc) – 0.075 0.090
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.115 0.130
Transfer Capacitance (VDG = 5.0 Vdc) Crss – 45 –

Rise Time (VDD = 15 Vdc, ID = 1.0 Adc, tr – 1.0 –
Gate Charge (See Figure 6) QT – 6000 – pC
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323
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N–Channel

Drain Current mA

Range 150
DIAGRAM
Purposes, 1/8″ from case for 10 SOT–23 N3
seconds CASE 318 W
1 STYLE 21
2
N3 = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
MGSF1N03LT1 SOT–23 3000 Tape & Reel
MGSF1N03LT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 5 MGSF1N03LT1/D
MGSF1N03LT1

OFF CHARACTERISTICS
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 1.2 Adc) – 0.08 0.10
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.125 0.145

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http://onsemi.com
327
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Preferred Device
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P–Channel

Drain Current mA

Range 150
DIAGRAM
Purposes, 1/8″ from case for 10 SOT–23 PE
seconds CASE 318 W
1 STYLE 21
2
PE = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
MGSF1P02ELT1 SOT–23 3000 Tape & Reel
MGSF1P02ELT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 2 MGSF1P02ELT1/D
MGSF1P02ELT1

OFF CHARACTERISTICS
(VDS = 16 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0 Vdc) IGSS – – ±100 nAdc
(VGS = 4.5 Vdc, ID = 0.75 Adc) – 0.22 0.26
(VGS = 2.5 Vdc, ID = 0.5 Adc) – 0.40 0.50

Turn–Off Delay Time RL = 5 Ω, RG = 6 Ω) td(off) – 200 –
Total Gate Charge (VDS = 16 Vdc, ID = 1.5 Adc, QT – 5500 – pC
VGS = 4.0 Vdc)

Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) VSD – – 1.0 V
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http://onsemi.com
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MGSF1P02ELT1

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P–Channel

Drain Current mA

Range 150
DIAGRAM
Purposes, 1/8″ from case for 10 SOT–23 PC
seconds CASE 318 W
1 STYLE 21
2
PC = Device Code
W = Work Week
PIN ASSIGNMENT
3
()%
1 2
)'1 ;(1
MGSF1P02LT1 SOT–23 3000 Tape & Reel
MGSF1P02LT3 SOT–23 10,000 Tape & Reel


November, 2000 – Rev. 3 MGSF1P02LT1/D
MGSF1P02LT1

OFF CHARACTERISTICS
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 1.5 Adc) – 0.235 0.350
(VGS = 4.5 Vdc, ID = 0.75 Adc) – 0.375 0.500

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http://onsemi.com
335
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This device represents a series of Power MOSFETs which are http://onsemi.com
capable of withstanding high energy in the avalanche and
commutation modes and the drain–to–source diode has a very low 2 AMPERES
reverse recovery time. These devices are designed for use in low
20 VOLTS
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc–dc converters, and power RDS(on) = 175 m
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be P–Channel
used for low voltage motor controls in mass storage products such as
# $ 9
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
transients. 4
• Miniature TSOP–6 Surface Mount Package – Saves Board Space
• Low Profile for Thin Applications such as PCMCIA Cards
• Very Low RDS(on) Provides Higher Efficiency and Expands 6
Battery Life
• Logic Level Gate Drive – Can Be Driven by Logic ICs
MARKING
• Diode is Characterized for Use in Bridge Circuits DIAGRAM
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperatures 3
2
1 TSOP–6 3V
CASE 318G W
• Package Mounting Information Provided 4 STYLE 1
5
6
3V = Device Code
W = Work Week
PIN ASSIGNMENT
()% ()% ;(1
6 5 4
1 2 3
()% ()% )'1
MGSF2P02HDT1 TSOP–6 3000 Tape & Reel
MGSF2P02HDT3 TSOP–6 10,000 Tape & Reel


November, 2000 – Rev. 1 MGSF2P02HD/D
MGSF2P02HD

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 20 V
Gate–to–Source Voltage VGS ±9 V
Drain Current – Continuous ID 1.3 A
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 10
Thermal Resistance – Junction to Ambient (Note 1.) RqJA 312 °C/W
Drain Current – Continuous ID 2.9 A
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 15
Total Power Dissipation @ TC = 25°C PD 2.0 W
Total Power Dissipation @ TC = 85°C PD 1.0 W
Thermal Resistance – Junction to Ambient (Note 2.) RqJA 62.5 °C/W
Operating and Storage Temperature Range TJ, Tstg – 55 to °C
150
Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk, EAS mJ
IL = 3.6 Apk, L = 25 mH, RG = 25 W 160
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 seconds TL 260 °C
1. Minimum FR–4 or G–10 PCB, Operating to Steady State.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Operating time ≤5 seconds.
http://onsemi.com
337
MGSF2P02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
Zero Gate Voltage Drain Current IDSS µA
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–to–Source Leakage Current IGSS nAdc
(VGS = ±9.0 Vdc, VDS = 0 Vdc) – – ±100
ON CHARACTERISTICS
(VDS = VGS, ID = 0.25 mAdc) 0.7 0.95 1.4
Drain–to–Source On–Voltage RDS(on) mW
(VGS = 4.5 Vdc, ID = 1.3 Adc) – 145 175
(VGS = 2.7 Vdc, ID = 0.8 Adc) – 220 280
(VDS = 10 Vdc, ID = 0.6 Adc) 1.3 2.0 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 150 –
f = 1.0 MHz)
Turn–On Delay Time td(on) – 15 – nsec
Rise Time (VDS = 10 Vdc, ID = 1.2 Adc, tr – 27 –
VGS = 4
4.55 Vdc
Vdc,
Turn–On Delay Time td(on) – 20 –
VGS = 2
2.77 Vdc
Vdc,
(VDS = 16 Vdc, ID = 1.2 Adc, Q1 – 0.7 –

VGS = 4.5 Vdc) Q2 – 2.6 –
Q3 – 1.9 –
(IS = 1.2 Adc, VGS = 0 Vdc) – 0.89 1.1
– 0.72 –
Reverse Recovery Time trr – 86 – nsec
(IS = 1.2 Adc, VGS = 0 Vdc, ta – 27 –
dIS/dt = 100 A/µs)
tb – 59 –
QRR – 0.115 – µC
NOTE: Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
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POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off–state condition when
controlled. The lengths of various switching intervals (∆t) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on–state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain–gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
t = Q/IG(AV) complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG – VGSP) resistance (Figure 9) shows how typical switching
tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If
where the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG
The circuit used to obtain the data is constructed to minimize
RG = the gate drive resistance
common inductance in the drain and gate circuit loops and
and Q2 and VGSP are read from the gate charge curve.
is believed readily achievable with board mounted
During the turn–on and turn–off delay times, gate current is components. Most power electronic loads are inductive; the
not constant. The simplest calculation uses appropriate data in the figure is taken with a resistive load, which
values from the capacitance curves in a standard equation for approximates an optimally snubbed inductive load. Power
voltage change in an RC network. The equations are: MOSFETs may be safely operated into an inductive load;
td(on) = RG Ciss In [VGG/(VGG – VGSP)] however, snubbing reduces switching losses.
td(off) = RG Ciss In (VGG/VGSP)
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Voltage versus Total Charge Variation versus Gate Resistance
The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 11. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by
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TSOP–6 POWER DISSIPATION

The power dissipation of the TSOP–6 is a function of the one can calculate the power dissipation of the device which
temperature of the die, RθJA, the thermal resistance from The 312°C/W for the TSOP–6 package assumes the use
sheet for the TSOP–6 package, PD can be calculated as milliwatts. There are other alternatives to achieving higher
follows: power dissipation from the TSOP–6 package. Another
TJ(max) – TA
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for use in small power management circuitry. Typical applications are http://onsemi.com
dc–dc converters, power management in portable and
battery–powered products such as computers, printers, PCMCIA 4 AMPERES
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 70 mΩ
• Miniature TSOP–6 Surface Mount Package Saves Board Space
N–Channel
# $ 9
Drain Current A 4
– Continuous @ TA = 25°C ID 4.0
Mounted on FR4 t 5 sec
MARKING
Range 150
DIAGRAM
Thermal Resistance – Junction–to–Ambient RθJA 62.5 °C/W
3
1 TSOP–6 442
CASE 318G W
4 STYLE 1
5
6
442 = Device Code

W = Work Week
PIN ASSIGNMENT
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November, 2000 – Rev. 1 MGSF3442VT1/D
MGSF3442VT1

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 10 µA) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS – – ±100 nAdc
(VDS = VGS, ID = 250 µAdc) 0.6 – –
(VGS = 4.5 Vdc, ID = 4.0 A) – 0.058 0.070
(VGS = 2.5 Vdc, ID = 3.4 A) – 0.072 0.095
Input Capacitance (VDS = 5.0 V) Ciss – 90 – pF
Output Capacitance (VDS = 5.0 V) Coss – 50 –
Transfer Capacitance (VDG = 5.0 V) Crss – 10 –

Rise Time (VDD = 10 Vdc, ID = 1.0 A, tr – 24 40
Turn–Off Delay Time VGEN = 10 V, RL = 10 Ω) td(off) – 36 60
Gate Charge QT – – – nC
Pulsed Current ISM – – 5.0 A
Forward Voltage (Note 2.) VSD – – 1.2 V
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The power dissipation of the TSOP–6 is a function of the into the equation for an ambient temperature TA of 25°C,
drain pad size. This can vary from the minimum pad size one can calculate the power dissipation of the device which
for soldering to a pad size given for maximum power in this case is 2.0 watts.
dissipation. Power dissipation for a surface mount device is 150°C – 25°C
PD = = 2.0 watts
determined by TJ(max), the maximum rated junction 62.5°C/W
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating The 62.5°C/W for the TSOP–6 package assumes the use
temperature, TA. Using the values provided on the data of the recommended footprint on a glass epoxy printed
sheet for the TSOP–6 package, PD can be calculated as circuit board to achieve a power dissipation of 2.0 watts.
follows: There are other alternatives to achieving higher power
dissipation from the TSOP–6 package. Another alternative
TJ(max) – TA
PD = would be to use a ceramic substrate or an aluminum core
RθJA board such as Thermal Cladt. Using a board material such
The values for the equation are found in the maximum as Thermal Clad, an aluminum core board, the power
ratings table on the data sheet. Substituting these values dissipation can be doubled using the same footprint.
http://onsemi.com
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battery–powered products such as computers, printers, PCMCIA 4 AMPERES
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 65 mΩ
• Miniature TSOP–6 Surface Mount Package Saves Board Space
N–Channel
# $ 9
Drain Current A 4
Mounted on FR4 t ≤ 5 sec
MARKING
Range 150
DIAGRAM
3
1 TSOP–6 3P
CASE 318G W
4 STYLE 1
5
6
3P = Device Code
W = Work Week
PIN ASSIGNMENT
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November, 2000 – Rev. 1 MGSF3454VT1/D
MGSF3454VT1

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 10 µA) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – ±100 nAdc
(VDS = VGS, ID = 250 µAdc) 1.0 – –
(VGS = 10 Vdc, ID = 4.2 A) – 0.05 0.065
(VGS = 4.5 Vdc, ID = 3.4 A) – 0.07 0.095

Rise Time (VDD = 10 Vdc, ID = 1.0 A, tr – 15 30
Turn–Off Delay Time VGEN = 10 V, RL = 10 Ω) td(off) – 20 35
Gate Charge QT – – 15 nC
Pulsed Current ISM – – 5.0 A
Forward Voltage (Note 2.) VSD – – 1.2 V
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drain pad size. This can vary from the minimum pad size one can calculate the power dissipation of the device which
for soldering to a pad size given for maximum power in this case is 2.0 watts.
PD = = 2.0 watts
the device junction to ambient, and the operating The 62.5°C/W for the TSOP–6 package assumes the use
temperature, TA. Using the values provided on the data of the recommended footprint on a glass epoxy printed
sheet for the TSOP–6 package, PD can be calculated as circuit board to achieve a power dissipation of 2.0 watts.
follows: There are other alternatives to achieving higher power
dissipation from the TSOP–6 package. Another alternative
TJ(max) – TA
PD = would be to use a ceramic substrate or an aluminum core
RθJA board such as Thermal Cladt. Using a board material such
The values for the equation are found in the maximum as Thermal Clad, an aluminum core board, the power
ratings table on the data sheet. Substituting these values dissipation can be doubled using the same footprint.
http://onsemi.com
353

Preferred Device
t '(

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N–Channel DPAK
The MLD1N06CL is designed for applications that require a rugged
power switching device with short circuit protection that can be
directly interfaced to a microcontrol unit (MCU). Ideal applications http://onsemi.com
include automotive fuel injector driver, incandescent lamp driver or
other applications where a high in–rush current or a shorted load 1 AMPERE
condition could occur. 62 VOLTS (Clamped)
This Logic Level Power MOSFET features current limiting for
RDS(on) = 750 mΩ
short circuit protection, integrated Gate–Source clamping for ESD
protection and integral Gate–Drain clamping for over–voltage N–Channel
protection and Sensefet technology for low on–resistance. No
additional gate series resistance is required when interfacing to the
output of a MCU, but a 40 kΩ gate pulldown resistor is recommended
to avoid a floating gate condition.
The internal Gate–Source and Gate–Drain clamps allow the device

to be applied without use of external transient suppression
components. The Gate–Source clamp protects the MOSFET input
from electrostatic voltage stress up to 2.0 kV. The Gate–Drain clamp
protects the MOSFET drain from the avalanche stress that occurs with
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inductive loads. Their unique design provides voltage clamping that is
essentially independent of operating temperature.

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) MARKING

DIAGRAM
Drain–to–Source Voltage VDSS Clamped Vdc
4
CASE 369A YWW
Drain–to–Gate Voltage VDGR Clamped Vdc L1N
(RGS = 1.0 MΩ) DPAK
1 2 STYLE 2 06C
Gate–to–Source Voltage 3
– Continuous VGS ±10 Vdc L1N06C = Device Code
Y = Year
Drain Current – Continuous ID Self–limited Adc
WW = Work Week
– Single Pulse IDM 1.8 Apk
T = MOSFET
Total Power Dissipation PD 40 Watts
Operating and Storage Temperature TJ, Tstg –50 to 150 °C
PIN ASSIGNMENT
Range 4
Drain
Electrostatic Discharge Voltage ESD 2.0 kV
(Human Model)
– Junction to Case RθJC 3.12 1 2 3
– Junction to Ambient RθJA 100 Gate Drain Source
– Junction to Ambient (Note 1.) RθJA 71.4
Soldering Purposes, Device Package Shipping
1/8″ from case for 5 sec.
1. When surface mounted to an FR4 board using the minimum recommended MLD1N06CLT4 DPAK 2500 Tape & Reel
pad size.

November, 2000 – Rev. 1 MLD1N06CL/D
MLD1N06CL
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

Single Pulse Drain–to–Source Avalanche Energy EAS 80 mJ
Starting TJ = 25°C

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Internally Clamped) V(BR)DSS Vdc
(ID = 20 mAdc, VGS = 0 Vdc) 59 62 65
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150°C) 59 62 65
(VDS = 45 Vdc, VGS = 0 Vdc) – 0.6 5.0
Gate–Source Leakage Current IGSS µAdc
(VG = 5.0 Vdc, VDS = 0 Vdc) – 0.5 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) – 1.0 20

(ID = 250 µAdc, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µAdc, VDS = VGS, TJ = 150°C) 0.6 – 1.6
Static Drain–to–Source On–Resistance RDS(on) Ohms
(ID = 1.0 Adc, VGS = 4.0 Vdc) – 0.63 0.75
(ID = 1.0 Adc, VGS = 5.0 Vdc) – 0.59 0.75
(ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150°C) – 1.1 1.9
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) – 1.0 1.8
Static Source–to–Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) VSD – 1.1 1.5 Vdc
Static Drain Current Limit ID(lim) Adc
(VGS = 5.0 Vdc, VDS = 10 Vdc) 2.0 2.3 2.75
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150°C) 1.1 1.3 1.8
Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) gFS 1.0 1.4 – mhos
RESISTIVE SWITCHING CHARACTERISTICS (Note 3.)
Turn–On Delay Time td(on) – 1.2 2.0 ns
Rise Time (VDD = 25 Vdc, ID = 1.0 Adc, tr – 4.0 6.0
Turn–Off Delay Time VGS(on) = 5.0 Vdc, RGS = 50 Ohms) td(off) – 4.0 6.0
Fall Time tf – 3.0 5.0
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from drain lead 0.25″ from package to center of die) – 4.5 –
Internal Source Inductance LS nH
(Measured from the source lead 0.25″ from package to source bond – 7.5 –
pad)
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Figure 1. Output Characteristics Figure 2. Transfer Function
THE SMARTDISCRETES CONCEPT SHORT CIRCUIT PROTECTION AND THE EFFECT OF

From a standard power MOSFET process, several active TEMPERATURE
and passive elements can be obtained that provide on–chip The on–chip circuitry of the MLD1N06CL offers an
protection to the basic power device. Such elements require integrated means of protecting the MOSFET component from
only a small increase in silicon area and/or the addition of one high in–rush current or a shorted load. As shown in the
masking layer to the process. The resulting device exhibits schematic diagram, the current limiting feature is provided by an
significant improvements in ruggedness and reliability as NPN transistor and integral resistors R1 and R2. R2 senses the
well as system cost reduction. The SMARTDISCRETES current through the MOSFET and forward biases the NPN
device functions can now provide an economical alternative transistor’s base as the current increases. As the NPN turns on,
to smart power ICs for power applications requiring low it begins to pull gate drive current through R1, dropping the gate
on–resistance, high voltage and high current. drive voltage across it, and thus lowering the voltage across the
These devices are designed for applications that require a gate–to–source of the power MOSFET and limiting the current.
rugged power switching device with short circuit protection The current limit is temperature dependent as shown in Figure
that can be directly interfaced to a microcontroller unit 3, and decreases from about 2.3 Amps at 25°C to about 1.3
(MCU). Ideal applications include automotive fuel injector Amps at 150°C.
driver, incandescent lamp driver or other applications where Since the MLD1N06CL continues to conduct current and
a high in–rush current or a shorted load condition could occur. dissipate power during a shorted load condition, it is important
to provide sufficient heatsinking to limit the device junction
OPERATION IN THE CURRENT LIMIT MODE temperature to a maximum of 150°C.
The amount of time that an unprotected device can The metal current sense resistor R2 adds about 0.4 ohms to
withstand the current stress resulting from a shorted load the power MOSFET’s on–resistance, but the effect of
before its maximum junction temperature is exceeded is temperature on the combination is less than on a standard
dependent upon a number of factors that include the amount MOSFET due to the lower temperature coefficient of R2. The
of heatsinking that is provided, the size or rating of the device, on–resistance variation with temperature for gate voltages of 4
its initial junction temperature, and the supply voltage. and 5 Volts is shown in Figure 5.
Without some form of current limiting, a shorted load can Back–to–back polysilicon diodes between gate and source
raise a device’s junction temperature beyond the maximum provide ESD protection to greater than 2 kV, HBM. This
rated operating temperature in only a few milliseconds. on–chip protection feature eliminates the need for an external
Even with no heatsink, the MLD1N06CL can withstand a Zener diode for systems with potentially heavy line transients.
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature
is under 100°C. For longer periods of operation in the
current–limited mode, device heatsinking can extend
operation from several seconds to indefinitely depending on
the amount of heatsinking provided.
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Figure 3. ID(lim) Variation Gate–To–Source Voltage
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MLD1N06CL
FORWARD BIASED SAFE OPERATING AREA (1.8 A at 150°C) and not the RDS(on). The maximum voltage
The FBSOA curves define the maximum drain–to–source can be calculated by the following equation:
voltage and drain current that a device can safely handle (150 – TA)
when it is forward biased, or when it is on, or being turned Vsupply =
ID(lim) (RθJC + RθCA)
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating where the value of RθCA is determined by the heatsink that
of the device, they are especially useful to designers of linear is being used in the application.
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations DUTY CYCLE OPERATION
for repetitive pulses at various case temperatures can be When operating in the duty cycle mode, the maximum
determined by using the thermal response curves. ON drain voltage can be increased. The maximum operating
Semiconductor Application Note, AN569, “Transient temperature is related to the duty cycle (DC) by the
Thermal Resistance – General Data and Its Use” provides following equation:
detailed instructions. TC = (VDS x ID x DC x RθCA) + TA
MAXIMUM DC VOLTAGE CONSIDERATIONS The maximum value of VDS applied when operating in a
The maximum drain–to–source voltage that can be duty cycle mode can be approximated by:
continuously applied across the MLD1N06CL when it is in 150 – TC
current limit is a function of the power that must be VDS =
ID(lim) x DC x RθJC
dissipated. This power is determined by the maximum
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SMARTDISCRETES technology can provide on–chip elements provide greater than 2.0 kV electrostatic voltage
realization of the popular gate–to–source and gate–to–drain protection.
Zener diode clamp elements. Until recently, such features The avalanche voltage of the gate–to–drain voltage clamp
have been implemented only with discrete components is set less than that of the power MOSFET device. As soon
which consume board space and add system cost. The as the drain–to–source voltage exceeds this avalanche
SMARTDISCRETES technology approach economically voltage, the resulting gate–to–drain Zener current builds a
melds these features and the power chip with only a slight gate voltage across the gate–to–source impedance, turning
increase in chip area. on the power device which then conducts the current. Since
In practice, back–to–back diode elements are formed in a virtually all of the current is carried by the power device, the
polysilicon region monolithicly integrated with, but gate–to–drain voltage clamp element may be small in size.
electrically isolated from, the main device structure. Each This technique of establishing a temperature compensated
back–to–back diode element provides a temperature drain–to–source sustaining voltage (Figure 7) effectively
compensated voltage element of about 7.2 volts. As the removes the possibility of drain–to–source avalanche in the
polysilicon region is formed on top of silicon dioxide, the power device.
diode elements are free from direct interaction with the The gate–to–drain voltage clamp technique is particularly
conduction regions of the power device, thus eliminating useful for snubbing loads where the inductive energy would
parasitic electrical effects while maintaining excellent otherwise avalanche the power device. An improvement in
thermal coupling. ruggedness of at least four times has been observed when
To achieve high gate–to–drain clamp voltages, several inductive energy is dissipated in the gate–to–drain clamped
voltage elements are strung together; the MLD1N06CL uses conduction mode rather than in the more stressful
8 such elements. Customarily, two voltage elements are used gate–to–source avalanche mode.
to provide a 14.4 volt gate–to–source voltage clamp. For the
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD1N06CL has been designed to allow direct =

interface to the output of a microcontrol unit to control an
isolated load. No additional series gate resistance is
required, but a 40 kΩ gate pulldown resistor is
recommended to avoid a floating gate condition in the event
of an MCU failure. The internal clamps allow the device to
be used without any external transistent suppressing
9
components.

http://onsemi.com
359
#
Preferred Device
t '(

* %+%
These SMARTDISCRETES devices feature current limiting for
short circuit protection, an integral gate–to–source clamp for ESD http://onsemi.com
protection and gate–to–drain clamp for over–voltage protection. No
additional gate series resistance is required when interfacing to the 1 AMPERE
output of a MCU, but a 40 kΩ gate pulldown resistor is recommended
to avoid a floating gate condition. 62 VOLTS (Clamped)
The internal gate–to–source and gate–to–drain clamps allow the RDS(on) = 750 mΩ
devices to be applied without use of external transient suppression
components. The gate–to–source clamp protects the MOSFET input N–Channel

from electrostatic gate voltage stresses up to 2.0 kV. The gate–to–drain
clamp protects the MOSFET drain from drain avalanche stresses that
occur with inductive loads. This unique design provides voltage
clamping that is essentially independent of operating temperature.
• Temperature Compensated Gate–to–Drain Clamp Limits Voltage

Stress Applied to the Device and Protects the Load From
Overvoltage
• Integrated ESD Diode Protection
• Controlled Switching Minimizes RFI
#
• Low Threshold Voltage Enables Interfacing Power Loads to

Microprocessors
MARKING DIAGRAM
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) & PIN ASSIGNMENT
4
Drain
Drain–to–Gate Voltage VDGR Clamped Vdc
(RGS = 1.0 MΩ)
TO–220AB
Gate–to–Source Voltage – Continuous VGS ±10 Vdc CASE 221A
STYLE 5 L1N06CL
Drain Current – Continuous ID Self–limited Adc
Drain Current – Single Pulse IDM 1.8 LLYWW
1
Total Power Dissipation PD 40 Watts 2
3 1 3
Electrostatic Discharge Voltage ESD 2.0 kV Gate Source
(Human Body Model)
2
Operating and Storage Junction TJ, Tstg –50 to 150 °C Drain
Temperature Range
L1N06CL = Device Code
LL = Location Code
Thermal Resistance, Junction to Case
θ, 3.12 °C/W Y = Year
Thermal Resistance, Junction to
θ, 62.5 WW = Work Week
Ambient
Soldering Purposes, 1/8″ from case Device Package Shipping
MLP1N06CL TO–220AB 50 Units/Rail


November, 2000 – Rev. 2 MLP1N06CL/D
MLP1N06CL
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

Single Pulse Drain–to–Source Avalanche Energy EAS 80 mJ
(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6)

OFF CHARACTERISTICS
Drain–to–Source Sustaining Voltage (Internally Clamped) V(BR)DSS Vdc
(ID = 20 mA, VGS = 0) 59 62 65
(ID = 20 mA, VGS = 0, TJ = 150°C) 59 62 65
(VDS = 45 V, VGS = 0) – 0.6 5.0
(VDS = 45 V, VGS = 0, TJ = 150°C) – 6.0 20
Gate–Body Leakage Current IGSS µAdc
(VG = 5.0 V, VDS = 0) – 0.5 5.0
(VG = 5.0 V, VDS = 0, TJ = 150°C) – 1.0 20

(ID = 250 µA, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µA, VDS = VGS, TJ = 150°C) 0.6 – 1.6
(ID = 1.0 A, VGS = 4.0 V) – 0.63 0.75
(ID = 1.0 A, VGS = 5.0 V) – 0.59 0.75
(ID = 1.0 A, VGS = 4.0 V, TJ = 150°C) – 1.1 1.9
(ID = 1.0 A, VGS = 5.0 V, TJ = 150°C) – 1.0 1.8
Forward Transconductance (ID = 1.0 A, VDS = 10 V) gFS 1.0 1.4 – mhos
Static Source–to–Drain Diode Voltage (IS = 1.0 A, VGS = 0) VSD – 1.1 1.5 Vdc
Static Drain Current Limit ID(lim) A
(VGS = 5.0 V, VDS = 10 V) 2.0 2.3 2.75
(VGS = 5.0 V, VDS = 10 V, TJ = 150°C) 1.1 1.3 1.8
RESISTIVE SWITCHING CHARACTERISTICS (Note 1.)

Turn–On Delay Time td(on) – 1.2 2.0 µs
Rise Time (VDD = 25 V, ID = 1.0 A, tr – 4.0 6.0
Turn–Off Delay Time VGS = 5.0 V, RG = 50 Ohms) td(off) – 4.0 6.0
1. Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
http://onsemi.com
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protection to the basic power device. Such elements require integrated means of protecting the MOSFET component
only a small increase in silicon area and/or the addition of one from high in–rush current or a shorted load. As shown in the
masking layer to the process. The resulting device exhibits schematic diagram, the current limiting feature is provided
significant improvements in ruggedness and reliability as by an NPN transistor and integral resistors R1 and R2. R2
well as system cost reduction. The SMARTDISCRETES senses the current through the MOSFET and forward biases
device functions can now provide an economical alternative the NPN transistor’s base as the current increases. As the
to smart power ICs for power applications requiring low NPN turns on, it begins to pull gate drive current through R1,
on–resistance, high voltage and high current. dropping the gate drive voltage across it, and thus lowering
These devices are designed for applications that require a the voltage across the gate–to–source of the power
rugged power switching device with short circuit protection MOSFET and limiting the current. The current limit is
that can be directly interfaced to a microcontroller unit temperature dependent as shown in Figure 3, and decreases
(MCU). Ideal applications include automotive fuel injector from about 2.3 Amps at 25°C to about 1.3 Amps at 150°C.
driver, incandescent lamp driver or other applications where Since the MLP1N06CL continues to conduct current and
a high in–rush current or a shorted load condition could occur. dissipate power during a shorted load condition, it is
important to provide sufficient heatsinking to limit the
OPERATION IN THE CURRENT LIMIT MODE device junction temperature to a maximum of 150°C.
The amount of time that an unprotected device can The metal current sense resistor R2 adds about 0.4 ohms
withstand the current stress resulting from a shorted load to the power MOSFET’s on–resistance, but the effect of
dependent upon a number of factors that include the amount MOSFET due to the lower temperature coefficient of R2.
of heatsinking that is provided, the size or rating of the The on–resistance variation with temperature for gate
device, its initial junction temperature, and the supply voltages of 4 and 5 Volts is shown in Figure 5.
voltage. Without some form of current limiting, a shorted Back–to–back polysilicon diodes between gate and
load can raise a device’s junction temperature beyond the source provide ESD protection to greater than 2 kV, HBM.
maximum rated operating temperature in only a few This on–chip protection feature eliminates the need for an
milliseconds. external Zener diode for systems with potentially heavy line
Even with no heatsink, the MLP1N06CL can withstand a transients.
http://onsemi.com
362
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voltage elements are strung together; the MLP1N06CL uses conduction mode rather than in the more stressful
The MLP1N06CL has been designed to allow direct =

9
components.

http://onsemi.com
365
#
Preferred Device
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This logic level power MOSFET features current limiting for short
circuit protection, integrated Gate–Source clamping for ESD http://onsemi.com
protection and integral Gate–Drain clamping for over–voltage
protection and Sensefet technology for low on–resistance. No 2 AMPERES
additional gate series resistance is required when interfacing to the
output of a MCU, but a 40 kΩ gate pulldown resistor is recommended 62 VOLTS (Clamped)
to avoid a floating gate condition. RDS(on) = 400 mΩ
The internal Gate–Source and Gate–Drain clamps allow the device
to be applied without use of external transient suppression N–Channel

components. The Gate–Source clamp protects the MOSFET input
from electrostatic voltage stress up to 2.0 kV. The Gate–Drain clamp
protects the MOSFET drain from the avalanche stress that occurs with
inductive loads. Their unique design provides voltage clamping that is
essentially independent of operating temperature.


#
Drain–to–Gate Voltage VDGR Clamped Vdc
(RGS = 1.0 MΩ)
Gate–to–Source Voltage – Continuous VGS ±10 Vdc MARKING DIAGRAM

Drain Current & PIN ASSIGNMENT
– Continuous @ TC = 25°C ID Self–limited Adc 4
4
Drain
Total Power Dissipation @ TC = 25°C PD 40 Watts
Electrostatic Voltage ESD 2.0 kV
Operating and Storage Temperature TJ, Tstg –50 to 150 °C TO–220AB
Range CASE 221A
STYLE 5 L2N06CL
THERMAL CHARACTERISTICS LLYWW
Maximum Junction Temperature TJ(max) 150 °C 1
2 1 3
Thermal Resistance – Junction to RθJC 3.12 °C/W 3
Case Gate Source
Maximum Lead Temperature for TL 260 °C 2

Soldering Purposes, 1/8″ from case Drain
for 5 sec.
L2N06CL = Device Code
DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS LL = Location Code
Single Pulse Drain–to–Source EAS 80 mJ Y = Year
Avalanche Energy (Starting WW = Work Week
TJ = 25°C, ID = 2.0 A, L = 40 mH)
MLP2N06CL TO–220AB 50 Units/Rail


November, 2000 – Rev. 1 MLP2N06CL/D
MLP2N06CL

OFF CHARACTERISTICS
(ID = 20 mAdc, VGS = 0 Vdc) 58 62 66
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150°C) 58 62 66
(VDS = 40 Vdc, VGS = 0 Vdc) – 0.6 5.0
Gate–Source Leakage Current IGSS µAdc
(VG = 5.0 Vdc, VDS = 0 Vdc) – 0.5 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) – 1.0 20

(ID = 250 µAdc, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µAdc, VDS = VGS, TJ = 150°C) 0.6 1 1.6
Static Drain Current Limit ID(lim) Adc
(VGS = 5.0 Vdc, VDS = 10 Vdc) 3.8 4.4 5.2
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150°C) 1.6 2.4 2.9
(ID = 1.0 Adc, VGS = 5.0 Vdc) – 0.3 0.4
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) – 0.53 0.7
Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) gFS 1.0 1.4 – mhos
Static Source–to–Drain Diode Voltage VSD Vdc
(IS = 1.0 Adc, VGS = 0 Vdc) – 1.1 1.5

Turn–On Delay Time td(on) – 1.0 1.5 µs
Turn–Off Delay Time VGS(on) = 5.0 Vdc, RGS = 25 Ohms) td(off) – 5.0 8.0
http://onsemi.com
367
MLP2N06CL
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and passive elements can be obtained that provide on–chip The on–chip circuitry of the MLP2N06CL offers an
protection to the basic power device. Such elements require integrated means of protecting the MOSFET component from
only a small increase in silicon area and/or the addition of one high in–rush current or a shorted load. As shown in the
masking layer to the process. The resulting device exhibits schematic diagram, the current limiting feature is provided by an
significant improvements in ruggedness and reliability as NPN transistor and integral resistors R1 and R2. R2 senses the
well as system cost reduction. The SMARTDISCRETES current through the MOSFET and forward biases the NPN
device functions can now provide an economical alternative transistor’s base as the current increases. As the NPN turns on,
to smart power ICs for power applications requiring low it begins to pull gate drive current through R1, dropping the gate
on–resistance, high voltage and high current. drive voltage across it, and thus lowering the voltage across the
These devices are designed for applications that require a gate–to–source of the power MOSFET and limiting the current.
rugged power switching device with short circuit protection The current limit is temperature dependent as shown in Figure
that can be directly interfaced to a microcontroller unit 3, and decreases from about 2.3 Amps at 25°C to about 1.3
(MCU). Ideal applications include automotive fuel injector Amps at 150°C.
driver, incandescent lamp driver or other applications where Since the MLP2N06CL continues to conduct current and
a high in–rush current or a shorted load condition could occur. dissipate power during a shorted load condition, it is important
to provide sufficient heatsinking to limit the device junction
OPERATION IN THE CURRENT LIMIT MODE temperature to a maximum of 150°C.
The amount of time that an unprotected device can The metal current sense resistor R2 adds about 0.4 ohms to
withstand the current stress resulting from a shorted load the power MOSFET’s on–resistance, but the effect of
dependent upon a number of factors that include the amount MOSFET due to the lower temperature coefficient of R2. The
of heatsinking that is provided, the size or rating of the device, on–resistance variation with temperature for gate voltages of 4
its initial junction temperature, and the supply voltage. and 5 Volts is shown in Figure 5.
Without some form of current limiting, a shorted load can Back–to–back polysilicon diodes between gate and source
raise a device’s junction temperature beyond the maximum provide ESD protection to greater than 2 kV, HBM. This
rated operating temperature in only a few milliseconds. on–chip protection feature eliminates the need for an external
Even with no heatsink, the MLP2N06CL can withstand a Zener diode for systems with potentially heavy line transients.
http://onsemi.com
368
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The MLP2N06CL has been designed to allow direct =

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371
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Preferred Device
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battery–powered products such as computers, printers, PCMCIA 300 mAMPS
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 1
N–Channel

Drain Current mAdc
– Pulsed Drain Current (tp ≤ 10 µs) IDM 750 #
Total Power Dissipation @ TA = 25°C(1) PD 225 mW
MARKING
Range 150
DIAGRAM
Thermal Resistance – Junction–to–Ambient RθJA 556 °C/W 3

Maximum Lead Temperature for Soldering TL 260 °C SOT–23 N1
Purposes, 1/8″ from case for 10 CASE 318 W
1 STYLE 21
seconds
2
N1 = Device Code
W = Work Week
PIN ASSIGNMENT
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MMBF0201NLT1 SOT–23 3000 Tape & Reel


November, 2000 – Rev. 2 MMBF0201NLT1/D
MMBF0201NLT1

OFF CHARACTERISTICS
(VDS = 16 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 300 mAdc) – 0.75 1.0
(VGS = 4.5 Vdc, ID = 100 mAdc) – 1.0 1.4
Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) gFS – 450 – mMhos
Transfer Capacitance (VDG = 5.0 V) Crss – 5.0 –

Rise Time (VDD = 15 Vdc, ID = 300 mAdc, tr – 2.5 –
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The melting temperature of solder is higher than the rated • The soldering temperature and time should not exceed
a short time could result in device failure. Therefore, the maximum temperature gradient should be 5°C or less.
• When preheating and soldering, the temperature of the during cooling
method, the difference should be a maximum of 10°C. damage to the device.
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376
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• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 1.4
P–Channel

Drain Current mAdc
– Pulsed Drain Current (tp ≤ 10 µs) IDM 750 #
(Note 1.) MARKING
DIAGRAM
Range 150
3
Thermal Resistance – Junction–to–Ambient RθJA 625 °C/W SOT–23 P3
Maximum Lead Temperature for Soldering TL 260 °C CASE 318 W
1 STYLE 21
Purposes, 1/8″ from case for 10
seconds 2

P3 = Device Code
W = Work Week
PIN ASSIGNMENT
3
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MMBF0202PLT1 SOT–23 3000 Tape & Reel


November, 2000 – Rev. 1 MMBF0202PLT1/D
MMBF0202PLT1

OFF CHARACTERISTICS
(VDS = 16 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 200 mAdc) – 0.9 1.4
(VGS = 4.5 Vdc, ID = 50 mAdc) – 2.0 3.5

Rise Time (VDD = –15 Vdc, tr – 1.0 –
RL = 75 Ω,
Ω ID = 200 mAdc,
mAdc
Turn–Off Delay Time 10 V, RG = 6.0 Ω)
VGEN = –10 td(off) – 16 –
Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, QT – 2700 – pC
ID = 200 mA)

http://onsemi.com
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N–Channel SC–70/SOT–323
• Miniature SC–70/SOT–323 Surface Mount Package Saves
Board Space N–Channel

Gate–to–Source Voltage – Pulse VGS ± 20 Vdc
Drain Current – Continuous @ TA = 25°C ID 50 mAdc

Total Power Dissipation @ TA = 25°C PD
(Note 1.) Derate above 25°C 100 mW
MARKING
Operating and Storage Temperature TJ, Tstg – 55 to °C DIAGRAM
Range 150

Purposes, for 10 seconds SC–70/SOT–323 F1
CASE 419 W
1. Mounted on G10/FR4 glass epoxy board using minimum recommended STYLE 8
footprint. 1
2
F1 = Device Code
W = Work Week
PIN ASSIGNMENT
3
Drain
Gate 1 2 Source
Top View
MMBF1374T1 SC–70/ 3000 Tape & Reel

SOT–323


January, 2001 – Rev. 0 MMBF1374T1/D
MMBF1374T1

OFF CHARACTERISTICS
Zero Gate Voltage Drain Current IDSS – – 1.0 µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 1.0 µAdc
Gate Threshold Voltage VGS(th) – 2 2.8 Vdc
Static Drain–to–Source On–Resistance rDS(on) – 27 50 Ω
(VGS = 4.5 Vdc, ID = 10 mAdc)

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383
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MAXIMUM RATINGS
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500 mAMPS
Drain–Gate Voltage VDGS 60 Vdc
60 VOLTS
RDS(on) = 5
– Non–repetitive (tp ≤ 50 ms) VGSM ±40 Vpk
N–Channel
Drain Current – Continuous ID 0.5 Adc
– Pulsed IDM 0.8 4
Total Device Dissipation FR–5 Board PD
(Note 1.) TA = 25°C 225 mW
Thermal Resistance, Junction to Ambient RqJA 556 °C/W
#
Junction and Storage Temperature TJ, Tstg –55 to °C
+150
1. FR–5 = 1.0 0.75 0.062 in. MARKING
DIAGRAM
3
SOT–23 6Z
CASE 318 W
1 STYLE 21
2
6Z = Device Code
W = Work Week
PIN ASSIGNMENT
3
Drain
Gate 1 2 Source
MMBF170LT1 SOT–23 3000 Tape & Reel
MMBF170LT3 SOT–23 10,000 Tape & Reel

November, 2000 – Rev. 3 MMBF170LT1/D
MMBF170LT1

Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (VGS = 0, ID = 100 mA) V(BR)DSS 60 – Vdc
Gate–Body Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) IGSS – 10 nAdc

Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) VGS(th) 0.8 3.0 Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 200 mA) rDS(on) – 5.0 W
On–State Drain Current (VDS = 25 Vdc, VGS = 0) ID(off) – 0.5 mA
(VDS = 10 Vdc, VGS = 0 V, f = 1.0 MHz)

Turn–On Delay Time (VDD = 25 Vdc, ID = 500 mA, Rgen = 50 W) td(on) – 10 ns
Turn–Off Delay Time Figure 1 td(off) – 10
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
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Figure 1. Switching Test Circuit Figure 2. Switching Waveform
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TJ(max) – TA
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N–Channel SC–70/SOT–323
Board Space N–Channel
4
Drain Current mAdc

– Continuous @ TA = 70°C ID 240 #
MARKING
Total Power Dissipation @ TA = 25°C PD DIAGRAM
(Note 1.) 150 mW
3
Operating and Storage Temperature TJ, Tstg – 55 to °C SC–70/SOT–323 N1
Range 150 CASE 419 W
STYLE 8
2
Purposes, for 10 seconds N1 = Device Code
1. Mounted on G10/FR4 glass epoxy board using minimum recommended W = Work Week
footprint.
PIN ASSIGNMENT
3 Drain
Gate 1 2 Source
Top View
MMBF2201NT1 SC–70/ 3000 Tape & Reel

SOT–323


November, 2000 – Rev. 3 MMBF2201NT1/D
MMBF2201NT1

OFF CHARACTERISTICS
(VDS = 16 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 300 mAdc) – 0.75 1.0
(VGS = 4.5 Vdc, ID = 100 mAdc) – 1.0 1.4

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Figure 1. Typical Drain Characteristics Figure 2. On Resistance versus Temperature
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Figure 3. On Resistance versus Gate–Source Figure 4. On Resistance versus Drain Current

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Figure 7. Transfer Characteristics
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MMBF2201NT1
INFORMATION FOR USING THE SC–70/SOT–323 SURFACE MOUNT PACKAGE

0.025
0.025
0.65
0.65
0.075
1.9
0.035
0.9
0.028
0.7 inches
mm
SC–70/SOT–323 POWER DISSIPATION

The power dissipation of the SC–70/SOT–323 is a one can calculate the power dissipation of the device which
function of the drain pad size. This can vary from the in this case is 150 milliwatts.
minimum pad size for soldering to a pad size given for 150°C – 25°C
maximum power dissipation. Power dissipation for a 833°C/W
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RθJA, the The 833°C/W for the SC–70/SOT–323 package assumes
thermal resistance from the device junction to ambient, and the use of the recommended footprint on a glass epoxy
the operating temperature, TA. Using the values provided printed circuit board to achieve a power dissipation of 150
on the data sheet for the SC–70 package, PD can be milliwatts. There are other alternatives to achieving higher
calculated as follows: power dissipation from the SC–70/SOT–323 package.
Another alternative would be to use a ceramic substrate or
TJ(max) – TA
PD = an aluminum core board such as Thermal Cladt. Using a
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391
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Preferred Device
#$%& '(
!
P–Channel SC–70/SOT–323
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life RDS(on) = 2.2
Board Space P–Channel
4

Drain Current mAdc
– Continuous @ TA = 70°C ID 240 #
MARKING
Total Power Dissipation @ TA = 25°C PD DIAGRAM
(Note 1.) 150 mW
3
Operating and Storage Temperature TJ, Tstg – 55 to °C SC–70/SOT–323 P3
Range 150 CASE 419 W
STYLE 8
2
Purposes, for 10 seconds P3 = Device Code
W = Work Week
1. Mounted on G10/FR4 glass epoxy board using minimum recommended
footprint.
PIN ASSIGNMENT
3 Drain
Gate 1 2 Source
Top View
MMBF2202PT1 SC–70/ 3000 Tape & Reel

SOT–323


November, 2000 – Rev. 3 MMBF2202PT1/D
MMBF2202PT1

OFF CHARACTERISTICS
(VDS = 16 Vdc, VGS = 0 Vdc) – – 1.0
(VGS = 10 Vdc, ID = 200 mAdc) – 1.5 2.2
(VGS = 4.5 Vdc, ID = 50 mAdc) – 2.0 3.5

Rise Time (VDD = –15 Vdc, tr – 1.0 –
RL = 75 Ω,
Ω ID = 200 mAdc,
mAdc
Turn–Off Delay Time 10 V, RG = 6.0 Ω)
VGEN = –10 td(off) – 16 –
Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, QT – 2700 – pC
ID = 200 mA)

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Figure 1. On Resistance versus Gate–Source Voltage Figure 2. On Resistance versus Temperature
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MMBF2202PT1
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MMBF2202PT1
INFORMATION FOR USING THE SC–70/SOT–323 SURFACE MOUNT PACKAGE

0.025
0.025
0.65
0.65
0.075
1.9
0.035
0.9
0.028
0.7 inches
mm
SC–70/SOT–323 POWER DISSIPATION

The power dissipation of the SC–70/SOT–323 is a one can calculate the power dissipation of the device which
function of the drain pad size. This can vary from the in this case is 150 milliwatts.
minimum pad size for soldering to a pad size given for 150°C – 25°C
maximum power dissipation. Power dissipation for a 833°C/W
maximum rated junction temperature of the die, RθJA, the The 833°C/W for the SC–70/SOT–323 package assumes
thermal resistance from the device junction to ambient, and the use of the recommended footprint on a glass epoxy
the operating temperature, TA. Using the values provided printed circuit board to achieve a power dissipation of 150
on the data sheet for the SC–70/SOT–323 package, PD can milliwatts. There are other alternatives to achieving higher
be calculated as follows: power dissipation from the SC–70/SOT–323 package.
Another alternative would be to use a ceramic substrate or
TJ(max) – TA
PD = an aluminum core board such as Thermal Cladt. Using a
http://onsemi.com
395
(!
#$%& '(
!
Complementary SO–8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding http://onsemi.com
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time. 3 AMPERES
MiniMOSt devices are designed for use in low voltage, high speed
25 VOLTS
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable RDS(on) = 100 mW (N–Channel)
and battery powered products such as computers, printers, cellular and RDS(on) = 210 mW (P–Channel)
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The N–Channel P–Channel
avalanche energy is specified to eliminate the guesswork in designs
D D
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive – Can be Driven by Logic ICs G G
• Miniature SO–8 Surface Mount Package – Saves Board Space
• Diode Exhibits High Speed, with Soft Recovery S S

Rating Symbol Value Unit MARKING
Drain–to–Source Voltage VDSS 25 Vdc DIAGRAM
Gate–to–Source Voltage VGS ± 20 Vdc
Drain Current – Continuous ID Adc SO–8, Dual
N–Channel 3.0 1300
8 CASE 751 LYWW
P–Channel 2.0 STYLE 11
Drain Current – Pulsed IDM Apk
1
N–Channel 9.0
P–Channel 6.0 1300 = Device Code
Operating and Storage Temperature Range TJ, Tstg –65 to °C L = Location Code
+150 Y = Year
Total Power Dissipation @ TA = 25°C PD 1.8 Watts WW = Work Week

Energy – Starting TJ = 25°C PIN ASSIGNMENT
(VDD = 20 Vdc, VGS = 10 Vdc, 113
IL = 3.0 Apk, L = 25 mH, RG = 25 W) Source–1 1 8 Drain–1
Thermal Resistance – Junction–to–Ambient RθJA 66.3 °C/W Gate–1 2 7 Drain–1
(Note 1.) Source–2 3 6 Drain–2
Maximum Lead Temperature for Soldering TL 260 °C Gate–2 4 5 Drain–2
Purposes, 1/8″ from Case for 10 sec.
Top View
1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.

MMDF1300R2 SO–8 2500 Tape & Reel

March, 2001 – Rev. 1 MMDF1300/D
MMDF1300

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) – 30 – –
Zero Gate Voltage Drain Current IDSS (N) – – 1.0 µAdc
(VDS = 25 Vdc, VGS = 0 Vdc) (P) – – 1.0
Gate–Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS – – – ±100 nAdc
ON CHARACTERISTICS (Notes 2. & 3.)
Gate Threshold Voltage VGS(th) (N) 1.0 1.5 2.0 Vdc
(VDS = VGS, ID = 250 µAdc) (P) 1.0 2.0 3.0
Drain–to–Source On–Resistance RDS(on) (N) – 0.09 0.10 Ohms
(VGS = 10 Vdc, ID = 2.0 Adc) (P) – 0.16 0.21
Drain–to–Source On–Resistance RDS(on) Ohms
(VGS = 4.5 Vdc, ID = 1.0 Adc) (N) – 0.13 0.16
(P) – 0.30 0.375
Forward Transconductance gFS (N) 1.0 – – mhos
(VDS = 3.0 Vdc, ID = 1.5 Adc) (P) 1.0 – –
(P) – 200 300
Vdc,
Coss (N) – 111 158
VGS = 0 Vdc,
(P) – 100 160
f = 1.0 MHz)
(P) – 40 75
(P) – 14 28
Rise Time (VDD = 10 Vdc, tr (N) – 98 196
ID = 2.0 Adc, (P) – 95 180
Turn–Off Delay Time VGS = 4.5 Vdc, td(off) (N) – 16 32
RG = 6.0 Ω) (P) – 22 45
Fall Time tf (N) – 30 60
(P) – 40 80
Total Gate Charge QT (N) – 3.3 5.0 nC
(P) – 7.0 10
Q1 (N) – 1.2 –
(VDS = 16 Vdc, (P) – 1.2 –
ID = 2
2.0
0 Adc
Adc,
VGS = 4.5 Vdc) Q2 (N) – 2.0 –
(P) – 2.5 –
Q3 (N) – 1.9 –
(P) – 3.5 –
3. Negative signs for P–Channel device omitted for clarity.
http://onsemi.com
397
MMDF1300
ELECTRICAL CHARACTERISTICS – continued (TA = 25°C unless otherwise noted)

SOURCE–DRAIN DIODE CHARACTERISTICS (Note 5.)
Forward On–Voltage (IS = 3.0 Adc, VGS = 0 Vdc) VSD (N) – 1.0 1.4 Vdc
(Note 6.) (IS = 2.0 Adc, VGS = 0 Vdc) (P) – 1.3 1.7
Reverse Recovery Time trr (N) – 23 – ns
(P) – 20 –
(N) ta (N) – 18 –
(ID = 2.0 Adc, (P) – 13 –
VGS = 0 Vdc tb (N) – 5.0 –
dIS/dt = 100 A/µs) (P) – 7.0 –
Reverse Recovery Stored QRR (N) – 0.02 – µC
Charge (P) – 0.02 –
http://onsemi.com
398
(
#$%& '(

and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the http://onsemi.com
drain–to–source diode has a low reverse recovery time. MiniMOSt
devices are designed for use in low voltage, high speed switching 1 AMPERE
applications where power efficiency is important. Typical applications 50 VOLTS
are dc–dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
RDS(on) = 300 m
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche N–Channel
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
Life

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed MARKING
• Mounting Information for SO–8 Package Provided

• IDSS Specified at Elevated Temperature SO–8, Dual
F1N05
8 CASE 751
LYWW
STYLE 11
1
Drain–to–Source Voltage VDS 50 Volts F1N05 = Device Code
L = Location Code
Gate–to–Source Voltage – Continuous VGS ±20 Volts
Y = Year
Drain Current – Continuous ID 2.0 Amps WW = Work Week
Drain Current – Pulsed IDM 10
Single Pulse Drain–to–Source Avalanche EAS 300 mJ PIN ASSIGNMENT

(VDD = 25 V, VGS = 10 V, IL = 2 Apk)
Operating and Storage Temperature Range TJ, Tstg –55 to °C Gate–1 2 7 Drain–1
150
Total Power Dissipation @ TA = 25°C PD 2.0 Watts 4 5
Gate–2 Drain–2
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W Top View
(Note 1.)
Maximum Temperature for Soldering, TL 260 °C

Time in Solder Bath 10 Sec ORDERING INFORMATION
1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with Device Package Shipping
one die operating, 10 sec. max.
MMDF1N05ER2 SO–8 2500 Tape & Reel

November, 2000 – Rev. 6 MMDF1N05E/D
MMDF1N05E

OFF CHARACTERISTICS
(VGS = 0, ID = 250 µA)
Zero Gate Voltage Drain Current IDSS – – 250 µAdc
(VDS = 50 V, VGS = 0)
(VGS = 20 Vdc, VDS = 0)

Drain–to–Source On–Resistance Ohms
(VGS = 10 Vdc, ID = 1.5 Adc) RDS(on) – – 0.30
(VGS = 4.5 Vdc, ID = 0.6 Adc) RDS(on) – – 0.50
Forward Transconductance (VDS = 15 V, ID = 1.5 A) gFS – 1.5 – mhos
(VDS = 25 VV, VGS = 0
0,
f = 1.0 MHz)
Turn–On Delay Time td(on) – – 20 ns
Rise Time (VDD = 10 V, ID = 1.5 A, RL = 10 Ω, tr – – 30
Turn–Off Delay Time VG = 10 V, RG = 50 Ω) td(off) – – 40
Fall Time tf – – 25
Total Gate Charge Qg – 12.5 – nC
(VDS = 10 V
V, ID = 1.5
15A A,
VGS = 10 V)
SOURCE–DRAIN DIODE CHARACTERISTICS (TC = 25°C)

Forward Voltage (Note 2.) (IS = 1.5 A, VGS = 0 V) VSD – – 1.6 V
Reverse Recovery Time (dIS/dt = 100 A/µs) trr – 45 – ns
http://onsemi.com
400
MMDF1N05E

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Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance Variation with Temperature
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Figure 5. On Resistance versus Figure 6. Gate Threshold Voltage Variation

Gate–To–Source Voltage with Temperature
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Figure 7. Capacitance Variation Figure 8. Gate Charge versus

Gate–To–Source Voltage
SAFE OPERATING AREA INFORMATION

" # ;'1 #″ !J .
6 +)( ″ !J # A ; 9″
'2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L

Forward Biased Safe Operating Area " #$°

The FBSOA curves define the maximum drain–to–source
µ!
voltage and drain current that a device can safely handle µ!
when it is forward biased, or when it is on, or being turned !

simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear

and a maximum junction temperature of 150°C. Limitations

for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. ON

Semiconductor Application Note, AN569, “Transient

Thermal Resistance – General Data and Its Use” provides
detailed instructions. Figure 9. Maximum Rated Forward Biased
Safe Operating Area

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total design. The footprint for the semiconductor packages correct pad geometry, the packages will self–align when
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SO–8 POWER DISSIPATION

The power dissipation of the SO–8 is a function of the into the equation for an ambient temperature TA of 25°C,
input pad size. These can vary from the minimum pad size one can calculate the power dissipation of the device which
for soldering to the pad size given for maximum power in this case is 2.0 Watts.
determined by TJ(max), the maximum rated junction PD = = 2.0 Watts
62.5°C/W
the device junction to ambient; and the operating The 62.5°C/W for the SO–8 package assumes the
temperature, TA. Using the values provided on the data recommended footprint on a glass epoxy printed circuit
sheet for the SO–8 package, PD can be calculated as board to achieve a power dissipation of 2.0 Watts using the
follows: footprint shown. Another alternative would be to use a
TJ(max) – TA
ceramic substrate or an aluminum core board such as
PD = Thermal Cladt. Using board material such as Thermal
RθJA
Clad, the power dissipation can be doubled using the same
The values for the equation are found in the maximum footprint.
ratings table on the data sheet. Substituting these values
http://onsemi.com
403
( .
Preferred Device
#$%& '(

http://onsemi.com
2 AMPERES
drain–to–source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed 12 VOLTS
switching applications where power efficiency is important. Typical RDS(on) = 45 m (N–Channel)
applications are dc–dc converters, and power management in portable RDS(on) = 180 m (P–Channel)
and battery powered products such as computers, printers, cellular and
in mass storage products such as disk drives and tape drives. N–Channel P–Channel
• Ultra Low RDS(on) Provides Higher Efficiency and Extends D D
Battery Life
G
• Diode Is Characterized for Use In Bridge Circuits G
• Diode Exhibits High Speed, With Soft Recovery S

• IDSS Specified at Elevated Temperature S

MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.)
SO–8, Dual
Drain–to–Source Voltage VDSS Vdc CASE 751 D2C01
N–Channel 20 8 LYWW
STYLE 14
P–Channel 12
1
Gate–to–Source Voltage VGS ± 8.0 Vdc
Drain Current – Continuous N–Channel ID 5.2 A D2C01 = Device Code
P–Channel 3.4 L = Location Code
– Pulsed N–Channel IDM 48 Y = Year
P–Channel 17 WW = Work Week
Operating and Storage Temperature Range TJ and –55 to °C
Tstg 150 PIN ASSIGNMENT
Total Power Dissipation @ TA= 25°C PD 2.0 Watts
(Note 2.) N–Source 1 8 N–Drain
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W N–Gate 2 7 N–Drain

(Note 2.) P–Source 3 6 P–Drain
Maximum Lead Temperature for Soldering TL 260 °C P–Gate 4 5 P–Drain
Purposes, 1/8″ from case for 10 seconds. Top View
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with ORDERING INFORMATION
MMDF2C01HDR2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 6 MMDF2C01HD/D
MMDF2C01HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3.)

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS (N) 20 – – Vdc
(VGS = 0 Vdc, ID = 250 µAdc) (P) 12 – –
(VGS = 0 Vdc, VDS = 20 Vdc) (N) – – 1.0
(VGS = 0 Vdc, VDS = 12 Vdc) (P) – – 1.0
(VGS = ±8.0 Vdc, VDS = 0) – – – 100
(VDS = VGS, ID = 250 µAdc) (P) 0.7 1.0 1.1
Drain–to–Source On–Resistance RDS(on) Ohm
(VGS = 4.5 Vdc, ID = 4.0 Adc) (N) – 0.035 0.045
(VGS = 4.5 Vdc, ID = 2.0 Adc) (P) – 0.16 0.18
(VGS = 2.7 Vdc, ID = 2.0 Adc) (N) – 0.043 0.055
(VGS = 2.7 Vdc, ID = 1.0 Adc) (P) – 0.2 0.22
(VDS = 2.5 Adc, ID = 2.0 Adc) (N) 3.0 6.0 –
(VDS = 2.5 Adc, ID = 1.0 Adc) (P) 3.0 4.75 –
(P) – 530 740
Output Capacitance (VDS = 10 Vdc, VGS = 0 Vdc, Coss (N) – 270 378
f = 1.0 MHz)) (P) – 410 570
(P) – 177 250
(VDD = 6.0 Vdc, ID = 4.0 Adc, (P) – 21 45
Rise Time VGS = 2.7 Vdc, tr (N) – 60 120
RG = 2.3 Ω) (P) – 156 315
Turn–Off Delay Time (VDD = 6.0 Vdc, ID = 2.0 Adc, td(off) (N) – 20 40
VGS = 2.7 Vdc, (P) – 38 75
Fall Time RG = 6.0 Ω) tf (N) – 29 58
(P) – 68 135
Turn–On Delay Time td(on) (N) – 10 20
(VDS = 6.0 Vdc, ID = 4.0 Adc, (P) – 16 35
RG = 2.3 Ω) (P) – 44 90
Turn–Off Delay Time (VDS = 6.0 Vdc, ID = 2.0 Adc, td(off) (N) – 24 48
VGS = 4.5 Vdc, (P) – 68 135
Fall Time RG = 6.0 Ω) tf (N) – 28 56
(P) – 54 110
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405
MMDF2C01HD
ELECTRICAL CHARACTERISTICS – continued (TA = 25°C unless otherwise noted) (Note 6.)
SWITCHING CHARACTERISTICS – continued (Note 8.)

Total Gate Charge QT (N) – 9.2 13 nC
(P) – 9.3 13
Gate–Source Charge (VDS = 10 Vdc, ID = 4.0 Adc, Q1 (N) – 1.3 –
VGS = 4.5 Vdc) (P) – 0.8 –
Gate–Drain Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, Q2 (N) – 3.5 –
VGS = 4.5 Vdc) (P) – 4.0 –
Q3 (N) – 3.0 –
(P) – 3.0 –
Forward Voltage (Note 7.) (IS = 4.0 Adc, VGS = 0 Vdc) VSD (N) – 0.95 1.1 Vdc
(IS = 2.0 Adc, VGS = 0 Vdc) (P) – 1.69 2.0
(P) – 48 –
ta (N) – 17 –
(IF = IS, (P) – 23 –
dIS/dt = 100 A/µs) tb (N) – 22 –
(P) – 25 –
Charge (P) – 0.05 –
http://onsemi.com
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SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define total power averaged over a complete switching cycle must
the maximum simultaneous drain–to–source voltage and not exceed (TJ(MAX) – TC)/(RθJC).
drain current that a transistor can handle safely when it is A power MOSFET designated E–FET can be safely used
forward biased. Curves are based upon maximum peak in switching circuits with unclamped inductive loads. For
junction temperature and a case temperature (TC) of 25°C. reliable operation, the stored energy from circuit inductance
Peak repetitive pulsed power limits are determined by using dissipated in the transistor while in avalanche must be less
the thermal response data in conjunction with the procedures than the rated limit and must be adjusted for operating
discussed in AN569, “Transient Thermal Resistance – conditions differing from those specified. Although industry
General Data and Its Use.” practice is to rate in terms of energy, avalanche energy
Switching between the off–state and the on–state may capability is not a constant. The energy rating decreases
traverse any load line provided neither rated peak current non–linearly with an increase of peak current in avalanche
(IDM) nor rated voltage (VDSS) is exceeded, and that the and peak junction temperature.
transition time (tr, tf) does not exceed 10 µs. In addition the

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414
MMDF2C01HD


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150°C
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drain–to–source diode has a low reverse recovery time. MiniMOSt 2.5 AMPERES
devices are designed for use in low voltage, high speed switching 25 VOLTS
applications where power efficiency is important. Typical applications
RDS(on) = 100 m (N–Channel)
powered products such as computers, printers, cellular and cordless RDS(on) = 250 m (P–Channel)
storage products such as disk drives and tape drives. The avalanche N–Channel P–Channel
D D
Life G
G
• Miniature SO–8 Surface Mount Package – Saves Board Space S
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• Diode Exhibits High Speed, with Soft Recovery MARKING
SO–8, Dual
Rating Symbol Value Unit F2C02
8 CASE 751
LYWW
Drain–to–Source Voltage VDSS 25 Vdc STYLE 14
Gate–to–Source Voltage VGS ± 20 Vdc 1
Drain Current – Continuous N–Channel ID 3.6 Adc
P–Channel 2.5 F2C02 = Device Code
– Pulsed N–Channel IDM 18 L = Location Code
P–Channel 13 Y = Year
WW = Work Week
Operating and Storage Temperature Range TJ and – 55 °C
Tstg to 150
Total Power Dissipation @ TA= 25°C (Note 2.) PD 2.0 Watts PIN ASSIGNMENT
N–Source 1 8 N–Drain
(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, N–Gate 2 7 N–Drain
L = 6.0 mH, RG = 25 Ω) N–Channel 245 P–Source 3 6 P–Drain
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A,
L = 10 mH, RG = 25 Ω) P–Channel 245 P–Gate 4 5 P–Drain
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W Top View
(Note 2.)
Maximum Lead Temperature for Soldering, TL 260 °C ORDERING INFORMATION
0.0625″ from case. Time in Solder Bath is
10 seconds.
1. Negative signs for P–Channel device omitted for clarity. MMDF2C02ER2 SO–8 2500 Tape & Reel
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with

November, 2000 – Rev. 6 MMDF2C02E/D
MMDF2C02E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) – 25 – –
(VDS = 20 Vdc, VGS = 0 Vdc) (P) – – 1.0
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS – – – 100 nAdc
(VDS = VGS, ID = 250 µAdc) – 1.0 2.0 3.0
(VGS = 10 Vdc, ID = 2.2 Adc) (N) – – 0.100
(VGS = 10 Vdc, ID = 2.0 Adc) (P) – – 0.250
(VGS = 4.5 Vdc, ID = 1.0 Adc) (N) – – 0.200
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) – – 0.400
On–State Drain Current ID(on) (N) 2.0 – – Adc
(VDS = 5.0 Vdc, VGS = 4.5 Vdc) (P) 2.0 – –
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 1.0 2.6 –
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 1.0 2.8 –
(P) – 340 475
f = 1.0 MHz) (P) – 220 300
(P) – 75 150
(VDD = 10 Vdc, ID = 2.0 Adc, (P) – 20 40
RG = 9.1 Ω) (P) – 40 80
Turn–Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, td(off) (N) – 19 38
VGS = 5.0 Vdc, (P) – 53 106
Fall Time RG = 25 Ω) tf (N) – 25 50
(P) – 41 82
Turn–On Delay Time td(on) (N) – 7.0 21
(VDD = 10 Vdc, ID = 2.0 Adc, (P) – 13 26
Rise Time VGS = 10 Vdc, tr (N) – 17 30
RG = 6.0 Ω) (P) – 29 58
VGS = 10 Vdc, (P) – 30 60
Fall Time RG = 6.0 Ω) tf (N) – 18 30
(P) – 28 56
http://onsemi.com
417
MMDF2C02E
(P) – 10 15
Gate–Source Charge Q1 (N) – 1.3 –
(VDS = 16 Vdc, ID = 2.0 Adc, (P) – 1.0 –
Gate–Drain Charge VGS = 10 Vdc) Q2 (N) – 2.9 –
(P) – 3.5 –
Q3 (N) – 2.7 –
(P) – 3.0 –
(IS = 2.0 Adc, VGS = 0 Vdc) (P) – 1.5 2.0
Reverse Recovery Time trr (N) – 34 66 ns
see Figure 7 (P) – 32 64
ta (N) – 17 –
(IF = IS, (P) – 19 –
dIS/dt = 100 A/µs) tb (N) – 17 –
(P) – 12 –
QRR (N) – 0.025 – µC
(P) – 0.035 –
http://onsemi.com
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versus Voltage versus Voltage
Switching behavior is most easily modeled and predicted During the turn–on and turn–off delay times, gate current is
by recognizing that the power MOSFET is charge not constant. The simplest calculation uses appropriate
controlled. The lengths of various switching intervals (∆t) values from the capacitance curves in a standard equation for
are determined by how fast the FET input capacitance can voltage change in an RC network. The equations are:
be charged by current from the generator. td(on) = RG Ciss In [VGG/(VGG – VGSP)]
The published capacitance data is difficult to use for td(off) = RG Ciss In (VGG/VGSP)
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate The capacitance (Ciss) is read from the capacitance curve at
charge data is used. In most cases, a satisfactory estimate of a voltage corresponding to the off–state condition when
average input current (IG(AV)) can be made from a calculating td(on) and is read at a voltage corresponding to the
rudimentary analysis of the drive circuit so that on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
t = Q/IG(AV) complicate the analysis. The inductance of the MOSFET
During the rise and fall time interval when switching a source lead, inside the package and in the circuit wiring
resistive load, VGS remains virtually constant at a level which is common to both the drain and gate current paths,
known as the plateau voltage, VSGP. Therefore, rise and fall produces a voltage at the source which reduces the gate drive
times may be approximated by the following: current. The voltage is determined by Ldi/dt, but since di/dt
tr = Q2 x RG/(VGG – VGSP) is a function of drain current, the mathematical solution is
tf = Q2 x RG/VGSP complex. The MOSFET output capacitance also
where finite internal gate resistance which effectively adds to the
VGG = the gate drive voltage, which varies from zero to VGG resistance of the driving source, but the internal resistance
RG = the gate drive resistance is difficult to measure and, consequently, is not specified.
http://onsemi.com
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SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain–to–source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and must be adjusted for operating
forward biased. Curves are based upon maximum peak conditions differing from those specified. Although industry
junction temperature and a case temperature (TC) of 25°C. practice is to rate in terms of energy, avalanche energy
Peak repetitive pulsed power limits are determined by using capability is not a constant. The energy rating decreases
the thermal response data in conjunction with the procedures non–linearly with an increase of peak current in avalanche
discussed in AN569, “Transient Thermal Resistance – and peak junction temperature.
General Data and Its Use.” Although many E–FETs can withstand the stress of
Switching between the off–state and the on–state may drain–to–source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded, and that the continuous current (ID), in accordance with industry
transition time (tr, tf) does not exceed 10 µs. In addition the custom. The energy rating must be derated for temperature
total power averaged over a complete switching cycle must as shown in the accompanying graph (Figure 9). Maximum
not exceed (TJ(MAX) – TC)/(RθJC). energy at currents below rated continuous ID can safely be
A power MOSFET designated E–FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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drain–to–source diode has a very low reverse recovery time. 2 AMPERES
MiniMOSt devices are designed for use in low voltage, high speed 20 VOLTS
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable
RDS(on) = 90 m (N–Channel)
and battery powered products such as computers, printers, cellular and RDS(on) = 160 m (P–Channel)
in mass storage products such as disk drives and tape drives. The N–Channel P–Channel
where inductive loads are switched and offer additional safety margin D D
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life G
• Logic Level Gate Drive – Can Be Driven by Logic ICs G

S
• Diode Exhibits High Speed, With Soft Recovery MARKING
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) SO–8, Dual
CASE 751 D2C02
Rating Symbol Value Unit 8 LYWW
STYLE 14
1
Gate–to–Source Voltage VGS ± 20 Vdc
Drain–to–Gate Voltage (RGS = 1.0 mΩ) VDGR 20 Vdc D2C02 = Device Code
Drain Current – Continuous N–Channel ID 3.8 A L = Location Code
P–Channel 3.3 Y = Year
– Pulsed N–Channel IDM 19 WW = Work Week
P–Channel 20
Operating and Storage Temperature Range TJ, Tstg – 55 °C PIN ASSIGNMENT
to 150
Total Power Dissipation @ TA= 25°C (Note 2.) PD 2.0 Watts N–Source 1 8 N–Drain
Single Pulse Drain–to–Source Avalanche EAS mJ N–Gate 2 7 N–Drain
Energy – Starting TJ = 25°C P–Source 3 6 P–Drain
(VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A,
L = 10 mH, RG = 25 Ω) N–Channel 405 P–Gate 4 5 P–Drain
(VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, Top View
L = 18 mH, RG = 25 Ω) P–Channel 324
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W ORDERING INFORMATION
(Note 2.)
Maximum Lead Temperature for Soldering, TL 260 °C Device Package Shipping
0.0625″ from case. Time in Solder Bath is
MMDF2C02HDR2 SO–8 2500 Tape & Reel
10 seconds.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with Preferred devices are recommended choices for future use
one die operating, 10 sec. max. and best overall value.

MMDF2C02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) – 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) (P) – – 1.0
(VDS = VGS, ID = 250 µAdc) – 1.0 1.5 2.0
(VGS = 4.5 Vdc, ID = 1.5 Adc) (N) – 0.074 0.100
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) – 0.152 0.180
(VGS = 10 Vdc, ID = 3.0 Adc) (N) – 0.058 0.090
(VGS = 10 Vdc, ID = 2.0 Adc) (P) – 0.118 0.160
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 2.0 3.88 –
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 2.0 3.0 –
(P) – 420 588
f = 1.0 MHz)) (P) – 290 406
(P) – 116 232
(VDD = 10 Vdc, ID = 3.0 Adc, (P) – 19 38
RG = 6.0 Ω) (P) – 66 132
VGS = 4.5 Vdc, (P) – 25 50
Fall Time RG = 6.0 Ω) tf (N) – 20 40
(P) – 37 74
(VDD = 10 Vdc, ID = 3.0 Adc, (P) – 11 22
RG = 6.0 Ω) (P) – 21 42
VGS = 10 Vdc, (P) – 45 90
Fall Time RG = 6.0 Ω) tf (N) – 21 42
(P) – 36 72
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428
MMDF2C02HD
(P) – 15 20
VGS = 10 Vdc) (P) – 1.2 –
Gate–Drain Charge (VDS = 16 Vdc, ID = 2.0 Adc, Q2 (N) – 2.8 –
VGS = 10 Vdc) (P) – 5.0 –
Q3 (N) – 2.4 –
(P) – 4.0 –
(IS = 2.0 Adc, VGS = 0 Vdc) (P) – 1.5 2.1
(P) – 38 –
(IS = 3.0 Adc, VAS = 0 Vdc, ta (N) – 18 –
dIS/dt = 100 A/µs) (P) – 17 –
(IS = 2.0 Adc, VAS = 0 Vdc, tb (N) – 5.0 –

dIS/dt = 100 A/µs) (P) – 21 –
Charge (P) – 0.034 –
http://onsemi.com
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150°C
150°C
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drain-to-source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed 2 AMPERES
switching applications where power efficiency is important. Typical 30 VOLTS
applications are dc-dc converters, and power management in portable RDS(on) = 70 m (N-Channel)
cordless phones. They can also be used for low voltage motor controls RDS(on) = 200 m (P-Channel)
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs N–Channel P–Channel
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life

• Miniature SO-8 Surface Mount Package – Saves Board Space
• IDSS Specified at Elevated Temperature DIAGRAM
• Mounting Information for SO-8 Package Provided SO–8, Dual
D2C03
8 CASE 751
LYWW
STYLE 14
1
Drain–to–Source Voltage VDSS 30 Vdc D2C03 = Device Code
Gate–to–Source Voltage VGS ± 20 Vdc L = Location Code
Drain Current – Continuous N–Channel ID 4.1 A Y = Year
P–Channel 3.0 WW = Work Week
Drain Current – Pulsed N–Channel IDM 21
P–Channel 15
PIN ASSIGNMENT
Operating and Storage Temperature Range TJ, Tstg – 55 °C
to 150
Total Power Dissipation @ TA= 25°C (Note 2.) PD 2.0 Watts
N–Gate 2 7 N–Drain
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W
P–Source 3 6 P–Drain
(Note 2.)
P–Gate 4 5 P–Drain
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0
Apk, L = 8.0 mH, RG = 25 Ω) N–Channel 324
(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 ORDERING INFORMATION
Apk, L = 18 mH, RG = 25 Ω) P–Channel 324
Maximum Lead Temperature for Soldering, TL 260 °C
0.0625″ from case. Time in Solder Bath is MMDF2C03HDR2 SO–8 2500 Tape & Reel
10 seconds.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with Preferred devices are recommended choices for future use
one die operating, 10 sec. max. and best overall value.

MMDF2C03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) – 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) (P) – – 1.0
(VDS = VGS, ID = 250 µAdc) (P) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 3.0 Adc) (N) – 0.06 0.070
(VGS = 10 Vdc, ID = 2.0 Adc) (P) – 0.17 0.200
(VGS = 4.5 Vdc, ID = 1.5 Adc) (N) – 0.065 0.075
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) – 0.225 0.300
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 2.0 3.6 –
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 2.0 3.4 –
(P) – 397 550
f = 1.0 MHz) (P) – 189 250
(P) – 64 126
(VDD = 15 Vdc, ID = 3.0 Adc, (P) – 16 32
RG = 9.1 Ω) (P) – 18 36
VGS = 4.5 Vdc, (P) – 63 126
Fall Time RG = 6.0 Ω) tf (N) – 19 38
(P) – 194 390
(VDD = 15 Vdc, ID = 3.0 Adc, (P) – 9.0 18
RG = 9.1 Ω) (P) – 10 20
VGS = 10 Vdc, (P) – 81 162
Fall Time RG = 6.0 Ω) tf (N) – 23 46
(P) – 192 384
http://onsemi.com
440
MMDF2C03HD
(P) – 14.2 19
VGS = 10 Vdc) (P) – 1.1 –
Gate–Drain Charge (VDS = 24 Vdc, ID = 2.0 Adc, Q2 (N) – 3.5 –
VGS = 10 Vdc) (P) – 4.5 –
Q3 (N) – 2.8 –
(P) – 3.5 –
(IS = 2.0 Adc, VGS = 0 Vdc) (P) – 1.82 2.0
(P) – 42 –
ta (N) – 17 –
(P) – 16 –
(IF = IS,
dIS/dt = 100 A/µs) tb (N) – 7.0 –
(P) – 26 –
Reverse Recovery Storage QRR (N) – 0.025 – µC
Charge (P) – 0.043 –

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449
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150°C
150°C
40 TO 80 SECONDS
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100°C

MASS ASSEMBLIES
5°C

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450
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devices are designed for use in low voltage, high speed switching 2 AMPERES
powered products such as computers, printers, cellular and cordless RDS(on) = 100 m
storage products such as disk drives and tape drives. The avalanche N–Channel
Life

• IDSS Specified at Elevated Temperatures MARKING
SO–8, Dual
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) CASE 751 F2N02
8 LYWW
Rating Symbol Value Unit STYLE 11
F2N02 = Device Code
Drain Current – Continuous @ TA = 25°C ID 3.6 Adc
L = Location Code
Drain Current – Continuous @ TA = 100°C ID 2.5
Y = Year
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 18 Apk
WW = Work Week
(Note 1.)
Operating and Storage Temperature Range TJ, Tstg –55 to °C PIN ASSIGNMENT
150
Single Pulse Drain–to–Source Avalanche EAS mJ Source–1 1 8 Drain–1
Energy – Starting TJ = 25°C 245 Gate–1 2 7 Drain–1
(VDD = 20 Vdc, VGS = 10 Vdc, Peak Source–2 3 6 Drain–2
IL = 9.0 Apk, L = 6.0 mH, RG = 25 Ω)
Thermal Resistance, Junction to Ambient RθJA 62.5 °C/W
(Note 1.) Top View
Purposes, 0.0625″ from case for 10
seconds
1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with Device Package Shipping
MMDF2N02ER2 SO–8 2500 Tape & Reel

November, 2000 – Rev. 6 MMDFN02E/D
MMDF2N02E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 25 – –

(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc
(VDS = VGS, ID = 250 µAdc 1.0 2.0 3.0
Static Drain–to–Source On–Resistance RDS(on) Ohm

(VGS = 10 Vdc, ID = 2.2 Adc) – 0.083 0.100
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.110 0.200
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) gFS 1.0 2.6 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 235 329
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Turn–On Delay Time td(on) – 10 30
VGS = 4
4.55 Vdc
Vdc,
(VDS = 16 Vdc, ID = 2.0 Adc, Q1 – 1.3 –

VGS = 10 Vdc) Q2 – 2.9 –
Q3 – 2.7 –
S Fi
See Figure 11
(IS = 2.0 Adc, VGS = 0 Vdc, ta – 17 –
dIS/dt = 100 A/µs) tb – 17 –
Reverse Recovery Storage Charge QRR – 0.03 – µC
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input pad size. These can vary from the minimum pad size one can calculate the power dissipation of the device which
62.5°C/W
TJ(max) – TA
RθJA
to a high temperature, failure to complete soldering within a • When shifting from preheating to soldering, the
short time could result in device failure. Therefore, the maximum temperature gradient shall be 5°C or less.
following items should always be observed in order to
• After soldering has been completed, the device should
minimize the thermal stress to which the devices are
subjected.
be allowed to cool naturally for at least three minutes.
• Always preheat the device. Gradual cooling should be used as the use of forced
• The delta temperature between the preheat and cooling will increase the temperature gradient and
soldering should be 100°C or less.* result in latent failure due to mechanical stress.
• When preheating and soldering, the temperature of the • Mechanical stress or shock should not be applied
leads and the case must not exceed the maximum during cooling
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering * Soldering a device without preheating can cause
method, the difference shall be a maximum of 10°C. excessive thermal shock and stress which can result in
damage to the device.
http://onsemi.com
457
MMDF2N02E


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
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100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
458
( 8
Preferred Device
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EZFETst are an advanced series of power MOSFETs which
contain monolithic back–to–back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These http://onsemi.com
miniature surface mount MOSFETs feature ultra low RDS(on) and true
logic level performance. They are capable of withstanding high energy 2 AMPERES
in the avalanche and commutation modes and the drain–to–source 50 VOLTS
diode has a very low reverse recovery time. EZFET devices are
designed for use in low voltage, high speed switching applications
RDS(on) = 300 m
where power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery powered N–Channel
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives.

Life

• Diode Exhibits High Speed, With Soft Recovery
MARKING
DIAGRAM
SO–8, Dual
F2N05Z
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 8 CASE 751
LYWW
STYLE 11
1
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 50 Vdc F2N05Z = Device Code
Gate–to–Source Voltage – Continuous VGS ± 15 Vdc L = Location Code
Y = Year
WW = Work Week
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 8.0 Apk
Total Power Dissipation @ TA = 25°C PD 2.0 Watts PIN ASSIGNMENT
(Note 1.)
Operating and Storage Temperature Range TJ, Tstg – 55 to °C Source–1 1 8 Drain–1
150 Gate–1 2 7 Drain–1
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W Source–2 3 6 Drain–2
Maximum Temperature for Soldering TL 260 °C
Purposes
Top View
1. When mounted on G10/FR–4 glass epoxy board using minimum
recommended footprint.
MMDF2N05ZR2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 2 MMDF2N05ZR2/D
MMDF2N05ZR2

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Note 4.) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 50 56 –
(VDS = 15 Vdc, VGS = 0 Vdc) – – 2.0
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS – 0.14 0.5
Gate Threshold Voltage (Cpk ≥ 2.0) (Note 4.) VGS(th) Vdc
(VDS = VGS, ID = 0.25 mAdc) 2.0 3.0 4.0
Threshold Temperature Coefficient (Negative) – –5.0 – mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Note 4.) RDS(on) mΩ
(VGS = 10 Vdc, ID = 1.5 Adc) – 200 300
(VGS = 5.0 Vdc, ID = 0.6 Adc) – 350 500
Forward Transconductance gFS mMhos
(VDS = 15 Vdc, ID = 2.5 Adc) – 2.0 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 58 –
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 25 Ω) td(off) – 130 260
(
(see fifigure 8)
(VDS = 25 Vdc, ID = 1.3 Adc, Q1 – 0.7 –
VGS = 10 Vdc) Q2 – 1.3 –
Q3 – 1.4 –

(IS = 2.0 Adc, VGS = 0 Vdc)
– 0.82 1.4
(IS = 2.0
2 0 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 23 –
dIS/dt = 100 A/µs)
tb – 43 –
4. Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA
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dissipation. Power dissipation for a surface mount device is
PD = 150°C – 25°C = 2.0 Watts
TJ(max) – TA
RθJA
http://onsemi.com
466
MMDF2N05ZR2


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
467
( #.
Preferred Device
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and battery powered products such as computers, printers, cellular and RDS(on) = 180 m
in mass storage products such as disk drives and tape drives. P–Channel
Life
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) SO–8, Dual
CASE 751 D2P01
8 LYWW
STYLE 11
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 12 Vdc 1
D2P01 = Device Code
Drain Current – Continuous @ TA = 25°C ID 3.4 Adc L = Location Code
Drain Current – Continuous @ TA = 100°C ID 2.1 Y = Year
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 17 Apk WW = Work Week
(Note 2.)
PIN ASSIGNMENT
Operating and Storage Temperature Range – 55 to 150 °C
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W Source–1 1 8 Drain–1
(Note 2.) Gate–1 2 7 Drain–1
Maximum Lead Temperature for Soldering TL 260 °C Source–2 3 6 Drain–2
1. Negative sign for P–Channel device omitted for clarity.
Top View
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
MMDF2P01HDR2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 6 MMDF2P01HD/D
MMDF2P01HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 12 – –
(VDS = 12 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS – – 100 nAdc
(VDS = VGS, ID = 250 µAdc) 0.7 1.0 1.1
(VGS = 4.5 Vdc, ID = 2.0 Adc) – 0.16 0.180
(VGS = 2.7 Vdc, ID = 1.0 Adc) – 0.2 0.220
Forward Transconductance (VDS = 2.5 Vdc, ID = 1.0 Adc) gFS 3.0 4.75 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 410 570
f = 1.0 MHz)
Rise Time (VDD = 6.0 Vdc, ID = 2.0 Adc, tr – 156 315
VGS = 22.7
7 Vdc
Vdc,
Rise Time (VDS = 6.0 Vdc, ID = 2.0 Adc, tr – 44 90
VGS = 44.5
5 Vdc
Vdc,
(VDS = 10 Vdc, ID = 2.0 Adc, Q1 – 0.8 –

VGS = 4.5 Vdc) Q2 – 4.0 –
Q3 – 3.0 –

– 1.69 2.0
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
– 1.2 –
(IS = 2.0 Adc, VGS = 0 Vdc, ta – 23 –

dIS/dt = 100 A/µs) tb – 25 –
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• Diode Exhibits High Speed, with Soft Recovery MARKING
• IDSS Specified at Elevated Temperatures DIAGRAM
• Mounting Information for SO–8 Package Provided SO–8, Dual
CASE 751 F2P02
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) 8 LYWW
STYLE 11
1
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc L = Location Code
Drain Current – Continuous @ TA = 25°C ID 2.5 Adc Y = Year
Drain Current – Continuous @ TA = 100°C ID 1.7 WW = Work Week
Derate above 25°C 16 mW/°C
Operating and Storage Temperature Range TJ, Tstg –55 to °C Source–1 1 8 Drain–1
150 Gate–1 2 7 Drain–1
Single Pulse Drain–to–Source Avalanche EAS mJ Source–2 3 6 Drain–2
Energy – Starting TJ = 25°C 245 4 5
Gate–2 Drain–2
(VDD = 20 Vdc, VGS = 10 Vdc, Peak
IL = 7.0 Apk, L = 10 mH, RG = 25 Ω) Top View
(Note 2.)
Purposes, 0.0625″ from case for 10 Device Package Shipping
seconds
MMDF2P02ER2 SO–8 2500 Tape & Reel
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided)
with one die operating, 10 sec. max.

November, 2000 – Rev. 6 MMDF2P02E/D
MMDF2P02E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 25 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
(VGS = 10 Vdc, ID = 2.0 Adc) – 0.19 0.25
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.3 0.4
Vdc, VGS = 0 Vd
Vdc,
Coss – 220 300
f = 1.0 MHz)
VGS = 5
5.00 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
(VDS = 16 Vdc, ID = 2.0 Adc, Q1 – 1.0 –

VGS = 10 Vdc) Q2 – 3.5 –
Q3 – 3.0 –
S Fi
See Figure 11
(IS = 2.0 Adc, VGS = 0 Vdc, ta – 19 –
dIS/dt = 100 A/µs) tb – 12 –
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input pad size. These can vary from the minimum pad size can calculate the power dissipation of the device which in
for soldering to the pad size given for maximum power this case is 2.0 Watts.
PD = 150°C – 25°C = 2.0 Watts
TJ(max) – TA
RθJA
ratings table on the data sheet. Substituting these values into
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CASE 751 D2P02
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) 8 LYWW
STYLE 11
1
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 20 Vdc L = Location Code
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc Y = Year
WW = Work Week
PIN ASSIGNMENT
(Note 2.) Source–1 Drain–1
1 8
Operating and Storage Temperature Range TJ, Tstg – 55 to °C Gate–1 2 7 Drain–1
150
(VDD = 20 Vdc, VGS = 5.0 Vdc, Top View
IL = 6.0 Apk, L = 18 mH, RG = 25 Ω)
(Note 2.)
Maximum Lead Temperature for Soldering TL 260 °C Device Package Shipping
MMDF2P02HDR2 SO–8 2500 Tape & Reel

MMDF2P02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 2.0 Adc) – 0.118 0.160
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.152 0.180
Vdc, VGS = 0 Vd
Vdc,
Coss – 290 406
f = 1.0 MHz)
Rise Time (VDS = 10 Vdc, ID = 2.0 Adc, tr – 66 132
VGS = 4
4.55 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
(VDS = 16 Vdc, ID = 2.0 Adc, Q1 – 1.2 –

VGS = 10 Vdc) Q2 – 5.0 –
Q3 – 4.0 –

– 1.5 2.1
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
– 1.24 –
(VDD = 15 V, IS = 2.0 A, ta – 17 –
dIS/dt = 100 A/µs)
tb – 21 –
QRR – 0.034 – µC
4. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.max.
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D2P03
8 CASE 751
LYWW
STYLE 11
1
Drain–to–Source Voltage VDSS 30 Vdc L = Location Code
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc Y = Year
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc WW = Work Week

PIN ASSIGNMENT
Total Power Dissipation @ TC = 25°C (Note 2.) PD 2.0 Watts Source–1 Drain–1
1 8
Operating and Storage Temperature Range TJ, Tstg – 55 °C
to 150
Energy – Starting TJ = 25°C Gate–2 4 5 Drain–2
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak Top View
IL = 6.0 Apk, L = 18 mH, RG = 25 Ω)
(Note 2.) ORDERING INFORMATION
1. Negative sign for P–Channel device omitted for clarity. MMDF2P03HDR2 SO–8 2500 Tape & Reel

MMDF2P03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 2.0 Adc) – 0.170 0.200
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.225 0.300
Vdc, VGS = 0 Vd
Vdc,
Coss – 189 250
f = 1.0 MHz)
Rise Time (VDD = 15 Vdc, ID = 2.0 Adc, tr – 17.5 35
VGS = 4
4.55 Vdc
Vdc,
Turn–Off Delay Time RG = 6.0 Ω) td(off) – 62.5 125
Turn–On Delay Time td(on) – 9.0 18
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 24 Vdc, ID = 2.0 Adc, Q1 – 1.1 –
VGS = 10 Vdc) Q2 – 4.5 –
Q3 – 3.5 –

(IS = 2.0 Adc, VGS = 0 Vdc, – 1.36 –
TJ = 125°C)
S Fi
See Figure 15
(IS = 2.0 Adc, VGS = 0 Vdc, ta – 15.6 –
dIS/dt = 100 A/µs) tb – 26.7 –
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CASE 751 D3N02
8 LYWW
STYLE 11
1
WW = Work Week
Drain Current – Continuous @ TA = 100°C ID 2.6 PIN ASSIGNMENT
Total Power Dissipation @ TA = 25°C PD 2.0 Watts Source–1 1 8 Drain–1
(Note 1.)
150
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak
IL = 9.0 Apk, L = 10 mH, RG = 25 Ω)
(Note 1.)
Purposes, 1/8″ from case for 10 seconds MMDF3N02HDR2 SO–8 2500 Tape & Reel

November, 2000 – Rev. 6 MMDF3N02HD/D
MMDF3N02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 3.0 Adc) – 0.058 0.090
(VGS = 4.5 Vdc, ID = 1.5 Adc) – 0.074 0.100
Vdc, VGS = 0 Vd
Vdc,
Coss – 184 250
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
Turn–On Delay Time td(on) – 7.0 21
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 16 Vdc, ID = 3.0 Adc, Q1 – 1.3 –
VGS = 10 Vdc) Q2 – 2.8 –
Q3 – 2.4 –

(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.72 –
S Fi
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dIS/dt = 100 A/µs) tb – 5.0 –
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150°C
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D3N03
8 CASE 751
LYWW
STYLE 11

Drain Current – Single Pulse (tp ≤ 10 µs) IDM 40 Apk PIN ASSIGNMENT
(Note 1.)
150 Source–2 3 6 Drain–2
Single Pulse Drain–to–Source Avalanche EAS 324 mJ Gate–2 4 5 Drain–2
IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω)
(Note 1.)
Purposes, 1/8″ from case for 10 seconds MMDF3N03HDR2 SO–8 2500 Tape & Reel
1. When mounted on 2″ square FR–4 board (1″ square 2 oz. Cu 0.06″ thick
single sided) with one die operating, 10s max.

MMDF3N03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.7 3.0
Threshold Temperature Coefficient (Negative) mV/°C
(VGS = 10 Vdc, ID = 3.0 Adc) – 0.06 0.07
(VGS = 4.5 Vdc, ID = 1.5 Adc) – 0.065 0.075
(VDS = 3.0 Vdc, ID = 1.5 Adc) 2.0 3.6 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 160 225
f = 1.0 MHz)

VGS = 4
4.55 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
(VDS = 10 Vdc, ID = 3.0 Adc, Q1 – 1.5 –

VGS = 10 Vdc) Q2 – 3.5 –
Q3 – 2.8 –
Forward On–Voltage (Note 2.) (IS = 3.0 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 3.0 Adc, VGS = 0 Vdc, – 0.82 1.2
TJ = 125°C) – 0.7 –
S Fi
See Figure 12 (IS = 3.0
3 0 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 17 –
dIS/dt = 100 A/µs)
tb – 7 –
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These miniature surface mount MOSFETs feature ultra low RDS(on) and
true logic level performance. They are capable of withstanding high energy
in the avalanche and commutation modes and the drain–to–source diode http://onsemi.com
has a very low reverse recovery time. MiniMOSt devices are designed
for use in low voltage, high speed switching applications where power 3 AMPERES
efficiency is important. Typical applications are dc–dc converters, and 40 VOLTS
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used for
RDS(on) = 80 m
low voltage motor controls in mass storage products such as disk drives
and tape drives. The avalanche energy is specified to eliminate the N–Channel
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
Life


• IDSS Specified at Elevated Temperature MARKING
DIAGRAM
SO–8, Dual
D3N04H
8 CASE 751
LYWW
STYLE 14
1
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
N–Gate 2 7 N–Drain
P–Source 3 6 P–Drain
P–Gate 4 5 P–Drain
Top View
MMDF3N04HDR2 SO–8 2500 Tape & Reel


MMDF3N04HD

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 40 Vdc
Drain Current – Continuous @ TA = 25°C (Note 1.) ID 3.4 Adc
Drain Current– Continuous @ TA = 70°C (Note 1.) ID 3.0
Drain Current– Pulsed Drain Current (Note 3.) IDM 40 Apk
Total Power Dissipation @ TA = 25°C (Note 1.) PD 2.0 Watts
Linear Derating Factor (1) 16 mW/°C
Linear Derating Factor (2) 11.11 mW/°C
Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C EAS mJ
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 4.0 mH, VDS = 40 Vdc) 162
THERMAL RESISTANCE
Rating Symbol Typ. Max. Unit
Thermal Resistance – Junction to Ambient, PCB Mount (Note 1.) RθJA – 62.5 °C/W
– Junction to Ambient, PCB Mount (Note 2.) RθJA – 90
1. When mounted on 1″ square FR–4 or G–10 board (VGS = 10 V, @ 10 Seconds)
2. When mounted on minimum recommended FR–4 or G–10 board (VGS = 10 V, @ Steady State)
http://onsemi.com
522
MMDF3N04HD

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 4. & 6.) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 40 – –
(VDS = 40 Vdc, VGS = 0 Vdc) – 0.015 2.5
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – 0.013 500 nAdc
Gate Threshold Voltage (Cpk ≥ 2.0) (Notes 4. & 6.) VGS(th) Vdc
(VDS = VGS, ID = 0.25 mAdc) 1.0 2.0 3.0
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Notes 4. & 6.) RDS(on) mΩ
(VGS = 10 Vdc, ID = 3.4 Adc) – 55 80
(VGS = 4.5 Vdc, ID = 1.7 Adc) – 79 100
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc) (Note 4.) gFS 2.0 4.5 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 130 230
f = 1.0 MHz)
Turn–Off Delay Time VGS = 10 Vdc, RG = 6 Ω) (Note 4.) td(off) – 28 56
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6 Ω) (Note 4.) td(off) – 17 34
(VDS = 40 Vdc, ID = 3.4 Adc, Q1 – 2.1 –

VGS = 10 Vdc) (Note 4.) Q2 – 3.7 –
Q3 – 5.4 –

Forward On–Voltage (IS = 3.4 Adc, VGS = 0 Vdc) (Note 4.) VSD Vdc
(IS = 3.4 Adc, VGS = 0 Vdc, – 0.87 1.5
TJ = 125°C) – 0.8 –
(IS = 3.4
3 4 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 20 –
tb – 7.0 –
Cpk =
3 x SIGMA
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150°C
150°C
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MASS ASSEMBLIES
5°C

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These miniature surface mount MOSFETs feature low RDS(on) and http://onsemi.com
true logic level performance. Dual MOSFET devices are designed for
use in low voltage, high speed switching applications where power 3 AMPERES
efficiency is important. Typical applications are dc–dc converters, and
power management in portable and battery powered products such as 60 VOLTS
computers, printers, cellular and cordless phones. They can also be RDS(on) = 100 mW
disk drives and tape drives. N–Channel


DIAGRAM
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc SO–8, Dual
D3N06
Drain Current – Continuous @ TA = 25°C ID 3.3 Adc 8 CASE 751
LYWW
IDM 16.5 Apk STYLE 11
Source Current – Continuous @ TA = 25°C IS 1.7 Adc 1
(Note 1.) L = Location Code
Y = Year
WW = Work Week
150
Energy – Starting TJ = 25°C PIN ASSIGNMENT
(VDD = 60 Vdc, VGS = 5.0 Vdc,
VDS = 32 Vdc, IL = 15 Apk, L = 10 mH, Source–1 Drain–1
1 8
RG = 25 Ω)
Purposes, 1/8″ from case for 10 seconds Gate–2 4 5 Drain–2
1. Mounted on G10/FR4 glass epoxy board using minimum recommended Top View
footprint.

This document contains information on a new product. Specifications and information and best overall value.

MMDF3N06HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 – –

(VDS = 48 Vdc, VGS = 0 Vdc) – 0.001 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS – 12 100 nAdc
(VDS = VGS, ID = 0.25 mAdc) 1.0 – –

(VGS = 10 Vdc, ID = 3.3 Adc) – 67.5 100
(VGS = 4.5 Vdc, ID = 2.5 Adc) – 82.5 200
(VDS = 15 Vdc, ID = 1.5 Adc) – 7.5 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 97.6 137
f = 1.0 MHz)
Transfer Capacitance Crss – 24.4 34.2

VGS = 4
4.55 Vdc
Vdc,
Turn–Off Delay Time RG = 30 Ω) td(off) – 23.8 47.6
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) – 32.4 64.8
(S Figure
(See Fi 8)
(VDS = 30 Vdc, ID = 3.3 Adc, Q1 – 1.8 –
VGS = 10 Vdc) Q2 – 3.5 –
Q3 – 3.75 –
(IS = 1.7 Adc, VGS = 0 Vdc) – 0.78 1.2
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.65 –
(IS = 1.7
1 7 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 23 –
dIS/dt = 100 A/µs)
tb – 4.9 –
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150°C
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power supplies, converters and power motor controls, these devices
are particularly well suited for bridge circuits where diode speed and 3 AMPERES
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
60 VOLTS
• On–resistance Area Product about One–half that of Standard RDS(on) = 130 mΩ
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FETt Predecessors N–Channel
• IDSS and VDS(on) Specified at Elevated Temperature

• Static Parameters are the Same for both TMOS V and TMOS E–FET

MARKING
DIAGRAM
Drain–to–Gate Voltage, (RGS = 1 MΩ) VDGR 60 Vdc
Drain Current – Continuous @ TA = 25°C ID 3.3 Adc SO–8, Dual
3N06V
Drain Current – Continuous @ TA = 100°C ID 0.7 8 CASE 751
LYWW
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 10 Apk STYLE 11
(Note 1.)
Operating and Storage Temperature Range TJ, Tstg –55 to °C L = Location Code
150 Y = Year
WW = Work Week
IL = 3.3 Apk, L = 10 mH, RG = 25 Ω)
PIN ASSIGNMENT
(Note 1.)
Purposes, 0.0625″ from case for 10 Source–2 3 6 Drain–2
seconds Gate–2 4 5 Drain–2
1. Mounted on G10/FR4 glass epoxy board using minimum recommended Top View
footprint.
MMDF3N06VLR2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 1 MMDF3N06VL/D
MMDF3N06VL

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 – –
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 5.0 Vdc, ID = 3.3 Adc) – 0.12 0.13
Drain–to–Source On–Voltage VDS(on) Vdc

(VGS = 5.0 Vdc, ID = 3.3 Adc) – – 0.5
(VGS = 5.0 Vdc, ID = 1.65 Adc, TJ = 150°C) – – 0.4
Forward Transconductance (VDS = 15 Vdc, ID = 1.65 Adc) gFS 1.0 3.0 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 110 150
f = 1.0 MHz)
VGS = 5
5.00 Vdc
Vdc,
(VDS = 48 Vdc, ID = 3.3 Adc, Q1 – 1.5 –

VGS = 5.0 Vdc) Q2 – 4.3 –
Q3 – 3.5 –
(IS = 3.3 Adc, VGS = 0 Vdc, TJ = 150°C) – 0.67 –
ta – 38 –
(IS = 3.3
3 3 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 20 –
Reverse Recovery Storage QRR – 0.11 – µC
Charge
http://onsemi.com
541
(.
Preferred Device
#$%& '(

MiniMOSt devices are designed for use in low voltage, high speed
4 AMPERES
applications are dc–dc converters, and power management in portable RDS(on) = 45 m
N–Channel
in mass storage products such as disk drives and tape drives.

Life

• Mounting Information for SO–8 Package Provided MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) SO–8, Dual

CASE 751 D4N01
Rating Symbol Value Unit 8 LYWW
STYLE 11
L = Location Code
Drain Current – Continuous @ TA = 25°C ID 5.2 Adc WW = Work Week
PIN ASSIGNMENT
(Note 1.) Source–1 Drain–1
1 8
Operating and Storage Temperature Range TJ, Tstg – 55 to °C Gate–1 2 7 Drain–1
150
Thermal Resistance – Junction to Ambient RθJA 62.5 °C/W Gate–2 4 5 Drain–2
(Note 1.)
Top View


MMDF4N01HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
(VDS = 12 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS – – 100 nAdc
(VDS = VGS, ID = 0.25 mAdc) 0.6 0.8 1.1
(VGS = 4.5 Vdc, ID = 4.0 Adc) – 0.035 0.045
(VGS = 2.7 Vdc, ID = 2.0 Adc) – 0.043 0.055
Vdc, VGS = 0 Vd
Vdc,
Coss – 270 378
f = 1.0 MHz)
VGS = 22.7
7 Vdc
Vdc,
VGS = 44.5
5 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 10 Vdc, ID = 4.0 Adc, Q1 – 1.3 –
VGS = 4.5 Vdc) Q2 – 3.5 –
Q3 – 3.0 –

(IS = 4.0 Adc, VGS = 0 Vdc, – 0.95 1.1
TJ = 125°C) – 0.78 –
(IS = 4.0 Adc, VGS = 0 Vdc, ta – 17 –

dIS/dt = 100 A/µs) tb – 22 –
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http://onsemi.com
549
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PEAK AT
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150°C
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MASS ASSEMBLIES
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http://onsemi.com
550
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EZFETst are an advanced series of Power MOSFETs which
http://onsemi.com
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low RDS(on) and true logic 5 AMPERES
level performance. They are capable of withstanding high energy in 20 VOLTS
the avalanche and commutation modes and the drain–to–source diode RDS(on) = 40 mΩ
has a very low reverse recovery time. EZFET devices are designed for
use in low voltage, high speed switching applications where power N–Channel
efficiency is important. D
• Zener Protected Gates Provide Electrostatic Discharge Protection
G
• IDSS Specified at Elevated Temperature S
MARKING
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) DIAGRAM
Drain–to–Source Voltage VDSS 20 Vdc SO–8, Dual
CASE 751 5N02Z
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 20 Vdc 8
STYLE 11 LYWW
Drain Current – Continuous @ TA = 25°C ID 5.0 Adc 1
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 40 Apk 5N02Z = Device Code
L = Location Code
Y = Year
Operating and Storage Temperature Range TJ, Tstg – 55 °C WW = Work Week
to 150
Thermal Resistance – Junction to RθJA 62.5 °C/W
Ambient PIN ASSIGNMENT
Maximum Temperature for Soldering TL 260 °C
1. When mounted on 1 inch square FR–4 or G–10 board
(VGS = 4.5 V, @ 10 Seconds). Gate–1 2 7 Drain–1
Top View

January, 2001 – Rev. 2 MMDF5N02Z/D
MMDF5N02Z

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
(VDS = 12 Vdc, VGS = 0 Vdc) – – 0.5
(VDS = 20 Vdc, VGS = 0 Vdc) – – 15
Gate–Body Leakage Current (VGS = ± 12 Vdc, VDS = 0 Vdc) IGSS – – 1.5 µAdc
(VDS = VGS, ID = 0.25 mAdc) 0.5 0.78 1.1
(VGS = 4.5 Vdc, ID = 5.0 Adc) – 34 40
(VGS = 2.7 Vdc, ID = 2.5 Adc) – 44 50
Vdc, VGS = 0 Vd
Vdc,
Coss – 330 460
f = 1.0 MHz)

Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6 Ω) td(off) – 190 238
(VDS = 10 Vdc, ID = 5.0 Adc, Q1 – 1.1 –

VGS = 4.5 Vdc) Q2 – 5.4 –
Q3 – 3.5 –
Forward On–Voltage (IS = 5.0 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 5.0 Adc, VGS = 0 Vdc, – 0.78 1.0
TJ = 125°C) – 0.65 –
(IS = 5.0
5 0 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 72 –
dIS/dt = 100 A/µs)
tb – 123 –
Cpk =
3 x SIGMA
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SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves the total power averaged over a complete switching cycle
define the maximum simultaneous drain–to–source must not exceed (T J(MAX) – T C )/(RθJC ).
voltage and drain current that a transistor can handle A power MOSFET designated E–FET can be safely
safely when it is forward biased. Curves are based upon used in switching circuits with unclamped inductive
maximum peak junction temperature and a case loads. For reliable operation, the stored energy from
temperature (T C ) of 25°C. Peak repetitive pulsed power circuit inductance dissipated in the transistor while in
limits are determined by using the thermal response data avalanche must be less than the rated limit and must be
in conjunction with the procedures discussed in AN569, adjusted for operating conditions differing from those
“Transient Thermal Resistance – General Data and Its specified. Although industry practice is to rate in terms
Use.” of energy, avalanche energy capability is not a constant.
Switching between the off–state and the on–state may The energy rating decreases non–linearly with an
traverse any load line provided neither rated peak current increase of peak current in avalanche and peak junction
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the temperature.
transition time (t r, tf ) does not exceed 10 µs. In addition
http://onsemi.com
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0.6 1.270
inches
mm

PD = 150°C – 25°C = 2.0 Watts
TJ(max) – TA
RθJA
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558
MMDF5N02Z


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

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559
(!.
Preferred Device
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These miniature surface mount MOSFETs feature low RDS(on) and
true logic level performance. Dual MOSFET devices are designed for
use in low voltage, high speed switching applications where power http://onsemi.com
power management in portable and battery powered products such as 6 AMPERES
computers, printers, cellular and cordless phones. They can also be 30 VOLTS
disk drives and tape drives. RDS(on) = 35 mW
• Logic Level Gate Drive – Can Be Driven by Logic ICs N–Channel


Rating Symbol Value Unit MARKING
Drain–to–Source Voltage VDSS 30 Vdc DIAGRAM
SO–8, Dual
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 30 Apk D6N03
8 CASE 751
Source Current – Continuous @ TA = 25°C IS 1.7 Adc LYWW
STYLE 11
1
(Note 1.)
Operating and Storage Temperature Range TJ, Tstg – 55 to °C D6N03 = Device Code
150 L = Location Code
Single Pulse Drain–to–Source Avalanche EAS 325 mJ Y = Year
Energy – Starting TJ = 25°C WW = Work Week
(VDD = 30 Vdc, VGS = 5.0 Vdc,
VDS = 20 Vdc, IL = 9.0 Apk,
PIN ASSIGNMENT
L = 10 mH, RG = 25 W)
Thermal Resistance – Junction–to–Ambient RθJA 62.5 °C/W Source–1 Drain–1
1 8
Maximum Lead Temperature for Soldering TL 260 °C Gate–1 2 7 Drain–1
Purposes, 1/8″ from Case for 10 sec.
1. Mounted on G10/FR4 glass epoxy board using minimum recommended
footprint. Gate–2 4 5 Drain–2
Top View


MMDF6N03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 24 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc
(VDS = VGS, ID = 0.25 mAdc) 1.0 – –
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance RDS(on) mΩ
(VGS = 10 Vdc, ID = 5.0 Adc) – 28 35
(VGS = 4.5 Vdc, ID = 3.9 Adc) – 42 50
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) gFS – 9.0 – Mhos
(VDS = 24 Vdc,
Output Capacitance VGS = 0 Vdc, Coss – 217 300
f=1
1.0
0 MH
MHz))
Transfer Capacitance Crss – 67.5 135

(VDD = 15 Vdc
Vdc,
Rise Time VGS = 10 Vdc, tr – 8.48 16.9
Turn–Off Delay Time ID = 1.0 Adc, td(off) – 89.6 179
RG = 6 0 Ω)
6.0
(VDD = 15 Vdc
Vdc,
Rise Time VGS = 4.5 Vdc, tr – 51.3 102
Turn–Off Delay Time ID = 1.0 Adc, td(off) – 47.2 94.5
RG = 6 0 Ω)
6.0
(S Figure
(See Fi 8) (VDS = 15 Vdc, Q1 – 2.0 –
ID = 5
5.0
0 Adc
Adc,
VGS = 10 Vdc) Q2 – 4.6 –
Q3 – 3.86 –
Forward On–Voltage (IS = 1.7 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 1.7 Adc, VGS = 0 Vdc, – 0.77 1.2
TJ = 125°C) – 0.65 –
(IS = 5.0 Adc, VGS = 0 Vdc, ta – 14.8 –

dIS/dt = 100 A/µs) tb – 39.7 –
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MMDF6N03HD
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567
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160°C
150°C
150°C
40 TO 80 SECONDS
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100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
568
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contain monolithic back–to–back zener diodes. These zener diodes http://onsemi.com
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low RDS(on) and true 7 AMPERES
logic level performance. They are capable of withstanding high energy
20 VOLTS
in the avalanche and commutation modes and the drain–to–source
diode has a very low reverse recovery time. EZFET devices are RDS(on) = 27 mΩ
designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc–dc N–Channel
converters, and power management in portable and battery powered D
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives.
G
• Designed to Withstand 200 V Machine Model and 2000 V Human
Body Model S
Life MARKING
DIAGRAM
• Logic Level Gate Drive – Can be Driven by Logic ICs
• Diode is Characterized for use in Bridge Circuits SO–8, Dual
7N02Z
• Diode Exhibits High Speed, with Soft Recovery 8 CASE 751
STYLE 11
LYWW
• IDSS Specified at Elevated Temperature 1
7N02Z = Device Code
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
Top View

January, 2001 – Rev. 1 MMDF7N02Z/D
MMDF7N02Z

Rating Symbol Max Unit
Drain Current Adc
Continuous @ TA = 25°C (Note 1.) ID 7.0
Continuous @ TA = 70°C (Note 1.) ID 4.6
Pulsed Drain Current (Note 3.) IDM 35
Linear Derating Factor @ TA = 25°C (Note 1.) 16 mW/°C
Linear Derating Factor @ TA = 25°C (Note 2.) 11.11 mW/°C
THERMAL RESISTANCE
Parameter Symbol Typ Max Unit
Junction–to–Ambient (Note 1.) RqJA – 62.5 °C/W
Junction–to–Ambient (Note 2.) – 90

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ±12 Vdc, VDS = 0 Vdc) IGSS – – 3.0 µAdc
(VDS = VGS, ID = 0.25 mAdc) 0.5 0.7 1.0
(VGS = 4.5 Vdc, ID = 7.0 Adc) – 23 27
(VGS = 2.5 Vdc, ID = 3.5 Adc) – 30 35
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) (Note 4.) gFS 5.0 11 – Mhos
1. When mounted on 1″ square FR4 or G–10 board (VGS = 10 V, @ 10 seconds).
2. When mounted on minimum recommended FR4 or G–10 board (VGS = 10 V, @ Steady State).
Cpk =
3 x SIGMA
http://onsemi.com
570
MMDF7N02Z

Vdc, VGS = 0 Vd
Vdc,
Coss – 350 490
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 12 Vdc, ID = 5.0 Adc, Q1 – 1.4 –
VGS = 4.5 Vdc) (Note 6.) Q2 – 6.7 –
Q3 – 6.5 –
Forward On–Voltage (IS = 7.0 Adc, VGS = 0 Vdc) (Note 6.) VSD – 0.90 1.1 Vdc
(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.84 –
(IS = 7.0 Adc, VGS = 0 Vdc, ta – 190 –

dIS/dt = 100 A/µs) (Note 6.) tb – 590 –
http://onsemi.com
571
MMDF7N02Z

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determined by TJ(max), the maximum rated junction 62.5°CńW
The 62.5°C/W for the SO–8 package assumes the
the device junction to ambient; and the operating
recommended footprint on a glass epoxy printed circuit
temperature, TA. Using the values provided on the data
board to achieve a power dissipation of 2.0 Watts using the
sheet for the SO–8 package, PD can be calculated as
footprint shown. Another alternative would be to use a
follows:
T (max) * TA
PD + J Thermal Cladt. Using board material such as Thermal
RqJA Clad, the power dissipation can be doubled using the same
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P–Channel SO–8, FETKYt
The FETKY product family incorporates low RDS(on), true logic
level MOSFETs packaged with industry leading, low forward drop, http://onsemi.com
low leakage Schottky Barrier rectifiers to offer high efficiency
components in a space saving configuration. Independent pinouts for 2 AMPERES
MOSFET and Schottky die allow the flexibility to use a single
component for switching and rectification functions in a wide variety
20 VOLTS
of applications such as Buck Converter, Buck–Boost, Synchronous RDS(on) = 160 mW
Rectification, Low Voltage Motor Control, and Load Management in VF = 0.39 Volts
Battery Packs, Chargers, Cell Phones and other Portable Products.
• Power MOSFET with Low VF, Low IR Schottky Rectifier P–Channel
• Lower Component Placement and Inventory Costs along with
D
Board Space Savings
• Logic Level Gate Drive – Can be Driven by Logic ICs
• IDSS Specified at Elevated Temperature G
• Applications Information Provided
S
(Note 1.)
MARKING
Rating Symbol Value Unit DIAGRAM
Drain–to–Gate Voltage (RGS = 1.0 MW) VDGR 20 Vdc SO–8
2P102
Gate–to–Source Voltage – Continuous VGS "20 Vdc 8 CASE 751
LYWW
STYLE 18
Drain Current (Note 3.)
– Continuous @ TA = 25°C ID 3.3 Adc 1
– Single Pulse (tp v 10 ms) IDM 20 Apk L = Location Code
Y = Year
Total Power Dissipation @ TA = 25°C PD 2.0 Watts WW = Work Week
(Note 2.)
Single Pulse Drain–to–Source Avalanche EAS 324 mJ PIN ASSIGNMENT

Energy – STARTING TJ = 25°C
VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20
Anode 1 8 Cathode
Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W
Anode 2 7 Cathode
1. Negative sign for P–channel device omitted for clarity.
2. Pulse Test: Pulse Width ≤ 250 µs, Duty Cycle ≤ 2.0%. Source 3 6 Drain
3. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Gate 4 5 Drain
10 sec. max.
Top View
MMDFS2P102R2 SO–8 2500 Tape & Reel

November, 2000 – Rev. 1 MMDFS2P102/D
MMDFS2P102
SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Peak Repetitive Reverse Voltage VRRM 20 Volts
Average Forward Current (Note 4.) (Rated VR) TA = 100°C IO 1.0 Amps
Peak Repetitive Forward Current (Note 3.) (Rated VR, Square Wave, 20 kHz) TA = 105°C Ifrm 2.0 Amps
Non–Repetitive Peak Surge Current Ifsm 20 Amps
(Surge applied at rated load conditions, halfwave, single phase, 60 Hz)
THERMAL CHARACTERISTICS – SCHOTTKY AND MOSFET

Thermal Resistance – Junction–to–Ambient (Note 5.) – MOSFET RqJA 167 °C/W
Thermal Resistance – Junction–to–Ambient (Note 6.) – MOSFET RqJA 100
Thermal Resistance – Junction–to–Ambient (Note 3.) – MOSFET RqJA 62.5
Thermal Resistance – Junction–to–Ambient (Note 5.) – Schottky RqJA 204
Operating and Storage Temperature Range Tj, Tstg –55 to 150
4. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), 10 sec. max.
5. Mounted with minimum recommended pad size, PC Board FR4.
6. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Steady State.
http://onsemi.com
580
MMDFS2P102
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 7.)
OFF CHARACTERISTICS
Drain–Source Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mA) 20 – – Vdc
Zero Gate Drain Current IDSS µAdc
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
Gate Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc
(VDS = VGS, ID = 0.25 mA) 1.0 1.5 2.0
Static Drain–Source Resistance RDS(on) Ohms
(VGS = 10 Vdc, ID = 2.0 Adc) – 0.118 0.160
(VGS = 4.5 Vdc, ID = 2.5 Adc) – 0.152 0.180
Vdc, VGS = 0 Vd
Vdc,
Coss – 290 406
f = 1.0 MHz)

VGS = 4
4.55 Vdc
Vdc,
(VDS = 16 Vdc, ID = 2.0 Adc, Q1 – 1.2 –

VGS = 10 Vdc) Q2 – 5.0 –
Q3 – 4.0 –
DRAIN SOURCE DIODE CHARACTERISTICS

Forward On–Voltage (Note 8.) (IS = 2.0 Adc, VSD V
VGS = 0 Vdc) – 1.5 2.1
ta – 17 –
(IS = 2.0
2 0 Adc,
Adc VDD = 15 VV,
dIS/dt = 100 A/µs) tb – 21 –
Charge
SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

g (Note
Maximum Instantaneous Forward Voltage ( 8.)) VF TJ = 25°C TJ = 125°C Volts
IF = 1.0
10A
0.47 0.39
IF = 2.0 A
0.58 0.53
Maximum Instantaneous Reverse Current (Note

( 8.)) IR TJ = 25°C TJ = 125°C mA
VR = 20 V
0.05 10
Maximum Voltage Rate of Change VR = 20 V dV/dt 10,000 V/ms
7. Negative sign for P–channel device omitted for clarity.
8. Pulse Test: Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2.0%.
9. Switching characteristics are independent of operating temperature.
http://onsemi.com
581
MMDFS2P102
TYPICAL FET ELECTRICAL CHARACTERISTICS
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TYPICAL APPLICATIONS
STEP DOWN SWITCHING REGULATORS

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STEP UP SWITCHING REGULATORS

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MULTIPLE BATTERY CHARGERS
Buck Regulator/Charger
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Li–lon BATTERY PACK APPLICATIONS
Battery Pack
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• During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge.
• During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation.
• Under normal operation, both transistors are on.
http://onsemi.com
588
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N–Channel SO–8, FETKYt
http://onsemi.com
The FETKY product family incorporates low RDS(on), true logic
level MOSFETs packaged with industry leading, low forward drop,
6 AMPERES
low leakage Schottky Barrier rectifiers to offer high efficiency
components in a space saving configuration. Independent pinouts for 30 VOLTS
MOSFET and Schottky die allow the flexibility to use a single RDS(on) = 35 mW
component for switching and rectification functions in a wide variety VF = 0.42 Volts
of applications such as Buck Converter, Buck–Boost, Synchronous
Rectification, Low Voltage Motor Control, and Load Management in
N–Channel
Battery Packs, Chargers, Cell Phones and other Portable Products.
• Power MOSFET with Low VF D
• Lower Component Placement and Inventory Costs along with
Board Space Savings
• Logic Level Gate Drive — Can be Driven by Logic ICs G
• Applications Information Provided S
• R2 Suffix for Tape and Reel (2500 units/13″ reel)
• Marking: 6N303 MARKING
DIAGRAM
(Note 1.)
SO–8
Rating Symbol Value Unit 6N303
8 CASE 751
Drain–to–Source Voltage VDSS 30 Vdc LYWW
STYLE 18
Drain–to–Gate Voltage (RGS = 1.0 MW) VDGR 30 Vdc 1
Gate–to–Source Voltage — Continuous VGS "20 Vdc
6N303 = Device Code
Drain Current (Note 2.) L = Location Code
– Continuous @ TA = 25°C ID 6.0 Adc Y = Year
– Single Pulse (tp v 10 ms) IDM 30 Apk WW = Work Week
Energy — Startin TJ = 25°C Anode 1 8 Cathode
VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Anode 2 7 Cathode
Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W
Source 3 6 Drain
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Gate 4 5 Drain
10 sec. max. Top View
MMDFS6N303R2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 1 MMDFS6N303/D
MMDFS6N303
SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Peak Repetitive Reverse Voltage VRRM 30 Volts
Average Forward Current (Note 3.) IO Amps

(Rated VR) TA = 104°C 2.0
Peak Repetitive Forward Current (Note 3.) Ifrm Amps

(Rated VR, Square Wave, 20 kHz) TA = 108°C 4.0
Non–Repetitive Peak Surge Current Ifsm 30 Amps

(Surge applied at rated load conditions, halfwave, single phase, 60 Hz)
THERMAL CHARACTERISTICS — SCHOTTKY AND MOSFET

Thermal Resistance — Junction–to–Ambient (Note 4.) — MOSFET RqJA 167 °C/W
Thermal Resistance — Junction–to–Ambient (Note 5.) — MOSFET RqJA 97
Thermal Resistance — Junction–to–Ambient (Note 2.) — MOSFET RqJA 62.5
Thermal Resistance — Junction–to–Ambient (Note 4.) — Schottky RqJA 197
Thermal Resistance — Junction–to–Ambient (Note 5.) — Schottky RqJA 97
Thermal Resistance — Junction–to–Ambient (Note 3.) — Schottky RqJA 62.5
Operating and Storage Temperature Range Tj, Tstg –55 to 150
MOSFET ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 6.)
OFF CHARACTERISTICS
Drain–Source Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mA) 30 — — Vdc
Temperature Coefficient (Positive) — — — mV/°C
Zero Gate Drain Current IDSS µAdc
(VDS = 24 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 20
Gate Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — 100 nAdc
(VDS = VGS, ID = 0.25 mA) 1.0 — —
Temperature Coefficient (Negative) — — —
Static Drain–Source Resistance RDS(on) mW
(VGS = 10 Vdc, ID = 5.0 Adc) — 28 35
(VGS = 4.5 Vdc, ID = 3.9 Adc) — 42 50
Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) gFS — 9.0 — mhos
Input Capacitance Ciss — 430 600 pF
Vdc, VGS = 0 Vd
Vdc,
Coss — 217 300
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 67.5 135
3. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), 10 sec. max.
4. Mounted with minimum recommended pad size, PC Board FR4.
5. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided), Steady State.
http://onsemi.com
590
MMDFS6N303
MOSFET ELECTRICAL CHARACTERISTICS – continued (TC = 25°C unless otherwise noted) (Note 7.)
Turn–On Delay Time td(on) — 8.2 16.5 ns
Rise Time (VDD = 15 Vdc, ID = 1.0 Adc, tr — 8.5 17
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 6.0 Ω) td(off) — 89.6 179
Fall Time tf — 61.1 122
Gate Charge QT — 15.7 31.4 nC
(VDS = 15 Vdc, ID = 5.0 Adc, Q1 — 2.0 —

VGS = 10 Vdc) Q2 — 4.6 —
Q3 — 3.9 —
DRAIN SOURCE DIODE CHARACTERISTICS

Forward On–Voltage (Note 7.) (IS = 1.7 Adc, VSD Vdc
VGS = 0 Vdc) — 0.77 1.2
Reverse Recovery Time trr — 54.5 — ns
ta — 14.8 —
(VGS = 0 VV, IS = 5.0
50A A,
dIS/dt = 100 A/µs) tb — 39.7 —
Reverse Recovery Stored QRR — 0.048 — µC
Charge
SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

g (Note
Maximum Instantaneous Forward Voltage ( 7.)) VF TJ = 25°C TJ = 125°C Volts
IF = 100 mAdc
Ad
0.28 0.13
IF = 3.0 Adc
0.42 0.33
IF = 6.0 Adc
0.50 0.45
Maximum Instantaneous Reverse Current (Note

( 7.)) IR TJ = 25°C TJ = 125°C mA
VR = 30 V
250 —
— 25 mA
Maximum Voltage Rate of Change VR = 30 V dV/dt 10,000 V/ms
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5 5
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Buck Regulator

5 5
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http://onsemi.com
596
MMDFS6N303
STEP UP SWITCHING REGULATORS

5 5
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MULTIPLE BATTERY CHARGERS
Buck Regulator/Charger
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Li–lon BATTERY PACK APPLICATIONS
Battery Pack
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• Applicable in battery packs which require a high current level.

• During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge.
• During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation.
• Under normal operation, both transistors are on.
http://onsemi.com
598
("
Preferred Device
#$%& '(

This Power MOSFET is designed for high speed, low loss power
switching applications such as switching regulators, dc–dc converters,
solenoid and relay drivers. The device is housed in the SOT–223 http://onsemi.com
package which is designed for medium power surface mount
applications.
250 mA
• Silicon Gate for Fast Switching Speeds 200 VOLTS
• Low Drive Requirement RDS(on) = 14
• The SOT–223 Package can be soldered using wave or reflow.
N–Channel
The formed leads absorb thermal stress during soldering
eliminating the possibility of damage to the die.

Drain–to–Source Voltage VDSS 200 Volts
Gate–to–Source Voltage – Non–Repetitive VGS ±20 Volts
Drain Current ID 250 mAdc

Total Power Dissipation @ TA = 25°C PD 0.8 Watts MARKING
(Note 1.) DIAGRAM
Operating and Storage Temperature TJ, Tstg –65 to °C 4
TO–261AA FT107
Range 150
CASE 318E LWW
THERMAL CHARACTERISTICS 1 STYLE 3
2
3
Thermal Resistance – RθJA 156 °C/W
Junction–to–Ambient
L = Location Code
Maximum Temperature for Soldering TL WW = Work Week
Purposes 260 °C
Time in Solder Bath 10 Sec
1. Device mounted on FR–4 glass epoxy printed circuit using minimum PIN ASSIGNMENT
recommended footprint.
4 ()%
1 2 3
)'1 ()% ;(1
MMFT107T1 SOT–223 1000 Tape & Reel


November, 2000 – Rev. 4 MMFT107T1/D
MMFT107T1

OFF CHARACTERISTICS
(VGS = 0, ID = 10 µA)
Zero Gate Voltage Drain Current IDSS – – 30 nAdc

(VDS = 130 V, VGS = 0)
Gate–Body Leakage Current – Reverse IGSS – – 10 nAdc

(VGS = 15 Vdc, VDS = 0)

Static Drain–to–Source On–Resistance RDS(on) – – 14 Ohms

(VGS = 10 Vdc, ID = 200 mA)
Drain–to–Source On–Voltage VDS(on) – – 2.8 Vdc

(VGS = 10 V, ID = 200 mA)

(VDS = 25 V, ID = 250 mA)
(VDS = 25 VV, VGS = 0
0,
f = 1.0 MHz)
Transfer Capacitance Crss – 6.0 –
SOURCE DRAIN DIODE CHARACTERISTICS

Diode Forward Voltage VF – 0.8 – V
Continuous Source Current, Body IS – – 250 mA
(VGS = 0,
Diode
IS = 250 mA)
Pulsed Source Current, Body ISM – – 500
Diode
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http://onsemi.com
601
MMFT107T1
INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE

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SOT-223 POWER DISSIPATION

The power dissipation of the SOT-223 is a function of the PD = 150°C – 25°C = 0.8 watts
pad size. This can vary from the minimum pad size for 156°C/W
soldering to a pad size given for maximum power
The 156°C/W for the SOT-223 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 0.8 watts.
There are other alternatives to achieving higher power
the device junction to ambient, and the operating
dissipation from the SOT-223 package. One is to increase
the area of the collector pad. By increasing the area of the
sheet for the SOT-223 package, PD can be calculated as
collector pad, the power dissipation can be increased.
follows:
Although the power dissipation can almost be doubled with
TJ(max) – TA
PD = this method, area is taken up on the printed circuit board
RθJA which can defeat the purpose of using surface mount
The values for the equation are found in the maximum technology. A graph of RθJA versus collector pad area is
ratings table on the data sheet. Substituting these values shown in Figure 9.
one can calculate the power dissipation of the device which
in this case is 0.8 watts.
http://onsemi.com
602
MMFT107T1
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Pad Area for the SOT-223 Package (Typical)
Another alternative would be to use a ceramic substrate board, the power dissipation can be doubled using the same
or an aluminum core board such as Thermal Cladt. Using footprint.
a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed or stainless steel with a typical thickness of 0.008 inches.
circuit board, solder paste must be applied to the pads. A The stencil opening size for the SOT-223 package should
solder stencil is required to screen the optimum amount of be the same as the pad size on the printed circuit board, i.e.,
solder paste onto the footprint. The stencil is made of brass a 1:1 registration.
http://onsemi.com
603
MMFT107T1

For any given circuit board, there will be a group of The line on the graph shows the actual temperature that
control settings that will give the desired heat pattern. The might be experienced on the surface of a test board at or
operator must set temperatures for several heating zones, near a central solder joint. The two profiles are based on a
and a figure for belt speed. Taken together, these control high density and a low density board. The Vitronics
settings make up a heating “profile” for that particular SMD310 convection/infrared reflow soldering system was
circuit board. On machines controlled by a computer, the used to generate this profile. The type of solder used was
computer remembers these profiles from one operating 62/36/2 Tin Lead Silver with a melting point between
session to the next. Figure 10 shows a typical heating 177–189°C. When this type of furnace is used for solder
profile for use when soldering a surface mount device to a reflow work, the circuit boards and solder joints tend to
printed circuit board. This profile will vary among heat first. The components on the board are then heated by
soldering systems but it is a good starting point. Factors that conduction. The circuit board, because it has a large surface
can affect the profile include the type of soldering system in area, absorbs the thermal energy more efficiently, then
use, density and types of components on the board, type of distributes this energy to the components. Because of this
solder used, and the type of board or substrate material effect, the main body of a component may be up to 30
being used. This profile shows temperature versus time. degrees cooler than the adjacent solder joints.

PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
604
(
Preferred Device
#$%& '(
"
switching applications such as switching regulators, converters,
applications.
700 mA
• High Voltage – 240 Vdc RDS(on) = 6.0
• Low Drive Requirement
N–Channel

The formed leads absorb thermal stress during soldering,


Drain Current ID 700 mAdc MARKING
DIAGRAM
(Note 1.)
Derate above 25°C 12 mW/°C 4
TO–261AA T2406
Operating and Storage Temperature TJ, Tstg –65 to °C CASE 318E LWW
Range 150 1 STYLE 3
2
THERMAL CHARACTERISTICS 3
Thermal Resistance – RθJA 83.3 °C/W

L = Location Code
Junction–to–Ambient (surface mounted)
WW = Work Week
(Note 1.)
Lead Temperature for Soldering Purposes, TL 260 °C
1/16″ from case PIN ASSIGNMENT
4 ()%
1. Device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in.
x 0.059 in.; mounting pad for the collector lead min. 0.93 sq. in.
1 2 3
)'1 ()% ;(1


MMFT2406T1

Characteristics Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS 240 – Vdc
(VGS = 0, ID = 100 µA)
Zero Gate Voltage Drain Current IDSS – 10 µAdc

(VDS = 120 V, VGS = 0)
Gate–Body Leakage Current IGSS – 100 nAdc

(VGS = 15 Vdc, VDS = 0)

Gate Threshold Voltage VGS(th) 0.8 2.0 Vdc

(VGS = 2.5 Vdc, ID = 0.1 Adc) – 10
(VGS = 10 Vdc, ID = 0.5 Adc) – 6.0
Drain–to–Source On–Voltage VDS(on) – 3.0 Vdc
(VGS = 10 V, ID = 0.5 A)
Forward Transconductance gFS 300 – mmhos

(VDS = 6.0 V, ID = 0.5 A)
(VDS = 25 VV, VGS = 0,
0
Output Capacitance Coss – 50
f = 1.0 MHz)
Transfer Capacitance Crss – 20
http://onsemi.com
606
MMFT2406T1

$
48
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pad size. This can vary from the minimum pad size for 83.3°C/W
The 83.3°C/W for the SOT-223 package assumes the use
follows:
TJ(max) – TA
http://onsemi.com
607
MMFT2406T1
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session to the next. Figure 2 shows a typical heating profile 177–189°C. When this type of furnace is used for solder
for use when soldering a surface mount device to a printed reflow work, the circuit boards and solder joints tend to
circuit board. This profile will vary among soldering heat first. The components on the board are then heated by
systems but it is a good starting point. Factors that can conduction. The circuit board, because it has a large surface
affect the profile include the type of soldering system in area, absorbs the thermal energy more efficiently, then

PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
609
( )
Preferred Device
#$%& '(

This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. This new energy efficient device
also offers a drain–to–source diode with a fast recovery time. http://onsemi.com
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
1 AMPERE
particularly well suited for bridge circuits where diode speed and 60 VOLTS
commutating safe operating areas are critical and offer additional RDS(on) = 300 m
safety margin against unexpected voltage transients. The device is
housed in the SOT–223 package which is designed for medium power P–Channel
surface mount applications.
• Silicon Gate for Fast Switching Speeds
• The SOT–223 Package can be Soldered Using Wave or Reflow. The
Formed Leads Absorb Thermal Stress During Soldering, Eliminating
the Possibility of Damage to the Die

Drain–to–Source Voltage VDS 60 MARKING
Vdc DIAGRAM
Gate–to–Source Voltage – Continuous VGS ±15
Drain Current – Pulsed IDM 4.8 4
TO–261AA 2955E
CASE 318E LWW
Total Power Dissipation @ TA = 25°C PD 0.8 Watts 1 STYLE 3
Derate above 25°C (Note 1.) 6.4 mW/°C 2
3
Range 150
2955E = Device Code
Single Pulse Drain–to–Source Avalanche EAS 108 mJ L = Location Code
Energy – Starting TJ = 25°C WW = Work Week
(VDD = 25 V, VGS = 10 V, Peak
IL= 1.2 A, L = 0.2 mH, RG = 25 Ω)
PIN ASSIGNMENT
THERMAL CHARACTERISTICS 4 ()%
Maximum Temperature for Soldering 260 °C
Purposes, TL
1. Power rating when mounted on FR–4 glass epoxy printed circuit board using 1 2 3
recommended footprint. )'1 ()% ;(1
MMFT2955ET1 SOT–223 1000 Tape & Reel
MMFT2955ET3 SOT–223 1000 Tape & Reel


November, 2000 – Rev. 5 MMFT2955E/D
MMFT2955E

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA) V(BR)DSS 60 – – Vdc
Zero Gate Voltage Drain Current, IDSS µAdc
(VDS = 60 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current, IGSS nAdc
(VGS = 15 V, VDS = 0) – – 100
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 2.0 – 4.5 Vdc
Static Drain–to–Source On–Resistance, (VGS = 10 V, ID = 0.6 A) RDS(on) – – 0.3 Ohms
Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1.2 A) VDS(on) – – 0.48 Vdc
Forward Transconductance, (VDS = 15 V, ID = 0.6 A) gFS – 7.5 – mhos
Input Capacitance Ciss – 460 –
(VDS = 20 V,
Output Capacitance VGS = 0, Coss – 210 – pF
f = 1 MH
MHz))

Rise Time (VDD = 25 V, ID = 1.6 A tr – 29 –
VGS = 10 V
V, RG = 50 ohms,
ohms ns
Turn–Off Delay Time RGS = 25 ohms) td(off) – 44 –
Total Gate Charge Qg – 18 –
(VDS = 48 V, ID = 1.2 A,
Gate–Source Charge VGS = 10 Vdc) Qgs – 2.8 – nC
S Figures
See Fi 15 andd 16
SOURCE DRAIN DIODE CHARACTERISTICS (Note 3.)
Forward On–Voltage IS = 1.2 A, VGS = 0 VSD – 1.0 – Vdc
Forward Turn–On Time IS = 1.2 A, VGS = 0, ton Limited by stray inductance
dlS/dt = 400 A/µs,
A/µs
Reverse Recovery Time VR = 30 V trr – 90 – ns
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FORWARD BIASED SAFE OPERATING AREA


voltage and drain current that a device can safely handle " #
when it is forward biased, or when it is on, or being turned
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AN569, “Transient Thermal Resistance–General Data and
Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to Figure 7. Maximum Rated Forward Biased
the MOSFET. The fundamental limits are the peak current, Safe Operating Area
IDM and the breakdown voltage, BVDSS. The switching
SOA is applicable for both turn–on and turn–off of the
devices for switching times less than one microsecond.

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The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows
the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to
those of Figure 9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device,
package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse
blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in ON Semiconductor’s test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns
was attained with dI S /dt of 400 A/µs.
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The power dissipation of the SOT–223 is a function of 150°C – 25°C = 800 milliwatts
PD =
the drain pad size. This can vary from the minimum pad 156°C/W
size for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is The 156°C/W for the SOT–223 package assumes the use
determined by TJ(max), the maximum rated junction of the recommended footprint on a glass epoxy printed
temperature of the die, RθJA, the thermal resistance from circuit board to achieve a power dissipation of 800
the device junction to ambient, and the operating milliwatts. There are other alternatives to achieving higher
temperature, TA. Using the values provided on the data power dissipation from the SOT–223 package. One is to
sheet for the SOT–223 package, PD can be calculated as increase the area of the drain pad. By increasing the area of
follows: the drain pad, the power dissipation can be increased.
Although one can almost double the power dissipation with
TJ(max) – TA
PD = this method, one will be giving up area on the printed
RθJA circuit board which can defeat the purpose of using surface
The values for the equation are found in the maximum mount technology. A graph of RθJA versus drain pad area is
in this case is 800 milliwatts.
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Area for the SOT–223 Package (Typical)

circuit board, solder paste must be applied to the pads. A The stencil opening size for the SOT–223 package should
http://onsemi.com
617
MMFT2955E


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
618
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avalanche and commutation modes. This device is also designed with
a low threshold voltage so it is fully enhanced with 5 Volts. This new http://onsemi.com
energy efficient device also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
2 AMPERES
applications in power supplies, dc–dc converters and PWM motor 20 VOLTS
controls, these devices are particularly well suited for bridge circuits RDS(on) = 150 m
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage N–Channel
transients. The device is housed in the SOT–223 package which is
designed for medium power surface mount applications.
• Silicon Gate for Fast Switching Speeds
• Low Drive Requirement to Interface Power Loads to Logic Level
ICs, VGS(th) = 2 Volts Max
• The SOT–223 Package can be Soldered Using Wave or Reflow. The
Formed Leads Absorb Thermal Stress During Soldering, Eliminating
the Possibility of Damage to the Die
MARKING
MAXIMUM RATINGS (TA = 25°C unless otherwise noted) DIAGRAM
Drain–to–Source Voltage VDS 20 4
TO–261AA
Vdc 2N02L
Gate–to–Source Voltage – Continuous VGS ±15 CASE 318E LWW
1 STYLE 3
Drain Current – Continuous ID 1.6 Adc 2
3
Drain Current – Pulsed IDM 6.4
Total Power Dissipation @ TA = 25°C PD 0.8 Watts L = Location Code
Derate above 25°C (Note 1.) 6.4 mW/°C WW = Work Week
Range 150
PIN ASSIGNMENT
4 ()%
(VDD = 10 V, VGS = 5 V, Peak
IL= 2 A, L = 0.2 mH, RG = 25 Ω)
1 2 3
Maximum Temperature for Soldering 260 °C )'1 ()% ;(1
Purposes, TL
Time in Solder Bath 10 Sec ORDERING INFORMATION
1. Power rating when mounted on FR–4 glass epoxy printed circuit board using
recommended footprint. Device Package Shipping
MMFT2N02ELT1 SOT–223 1000 Tape & Reel


November, 2000 – Rev. 4 MMFT2N02EL/D
MMFT2N02EL

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA) V(BR)DSS 20 – – Vdc
Zero Gate Voltage Drain Current, (VDS = 20 V, VGS = 0) IDSS – – 10 µAdc
Gate–Body Leakage Current, (VGS = 15 V, VDS = 0) IGSS – – 100 nAdc
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 1 – 2 Vdc
Static Drain–to–Source On–Resistance, (VGS = 5 V, ID = 0.8 A) RDS(on) – – 0.15 Ohms
Drain–to–Source On–Voltage, (VGS = 5 V, ID = 1.6 A) VDS(on) – – 0.32 Vdc
Forward Transconductance, (VDS = 10 V, ID = 0.8 A) gFS – 2.6 – mhos
Input Capacitance Ciss – 580 –
(VDS = 15 V,
Output Capacitance VGS = 0, Coss – 430 – pF
f = 1 MH
MHz))
Rise Time (VDD = 15 V, ID = 1.6 A tr – 73 –
VGS = 5 V
V, RG = 50 ohms,
ohms ns
Turn–Off Delay Time RGS = 25 ohms) td(off) – 77 –
Total Gate Charge Qg – 20 –
(VDS = 16 V, ID = 1.6 A,
Gate–Source Charge VGS = 5 Vdc) Qgs – 1.7 – nC
S Figures
See Fi 15 andd 16
Gate–Drain Charge Qgd – 6 –
SOURCE DRAIN DIODE CHARACTERISTICS (Note 2.)
Forward On–Voltage IS = 1.6 A, VGS = 0 VSD – 0.9 – Vdc
Forward Turn–On Time IS = 1.6 A, VGS = 0, ton Limited by stray inductance
dlS/dt = 400 A/µs,
A/µs
Reverse Recovery Time VR = 16 V trr – 55 – ns
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%
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620
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621
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FORWARD BIASED SAFE OPERATING AREA

voltage and drain current that a device can safely handle
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AN569, “Transient Thermal Resistance–General Data and

Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) is the boundary

that the load line may traverse without incurring damage to Figure 7. Maximum Rated Forward Biased
the MOSFET. The fundamental limits are the peak current, Safe Operating Area
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turn–on and turn–off of the devices for
switching times less than one microsecond.

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The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows
the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to
those of Figure 9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device,
package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse
blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in ON Semiconductor’s test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns
was attained with dI S /dt of 400 A/µs.
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623
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The power dissipation of the SOT–223 is a function of 150°C – 25°C
The 156°C/W for the SOT–223 package assumes the use
circuit board to achieve a power dissipation of 800
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT–223 package. One is to
increase the area of the drain pad. By increasing the area of
sheet for the SOT–223 package, PD can be calculated as
the drain pad, the power dissipation can be increased.
follows:
TJ(max) – TA this method, one will be giving up area on the printed
PD =
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PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
627
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These Power MOSFETs are designed for low voltage, high speed
switching applications in power supplies, converters and power motor
controls, these devices are particularly well suited for bridge circuits http://onsemi.com
1 AMPERE
transients. 60 VOLTS
• Avalanche Energy Specified RDS(on) = 130 m
N–Channel

– Continuous VGS ± 20 Vdc

– Non–repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk
Drain Current – Continuous @ 100°C ID 1.4 MARKING
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 6.0 Apk DIAGRAM
Total PD @ TA = 25°C mounted on 1″ sq. PD 2.1 Watts
Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 1.7 4
TO–261AA TBD
0.70″ sq. Drain pad on FR–4 bd material CASE 318E LWW
Total PD @ TA = 25°C mounted on min. 0.94 1 STYLE 3
Drain pad on FR–4 bd material 2
3
L = Location Code
Range 175
WW = Work Week
(VDD = 25 Vdc, VGS = 10 Vdc, Peak 58 PIN ASSIGNMENT
IL = 3.4 Apk, L = 10 mH, RG = 25 Ω )
4 ()%
– Junction to Ambient on 1″ sq. Drain RθJA 70
pad on FR–4 bd material
– Junction to Ambient on 0.70″ sq. Drain RθJA 88
– Junction to Ambient on min. Drain pad RθJA 159
on FR–4 bd material 1 2 3
Maximum Lead Temperature for Soldering TL 260 °C )'1 ()% ;(1
seconds ORDERING INFORMATION
MMFT3055VT1 SOT–223 1000 Tape & Reel
MMFT3055VT3 SOT–223 4000 Tape & Reel

November, 2000 – Rev. 2 MMFT3055V/D
MMFT3055V

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3.) V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 – – Vdc
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Gate Threshold Voltage (Cpk ≥ 2.0) (Note 3.) VGS(th)
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Note 3.) RDS(on) Ohm
(VGS = 10 Vdc, ID = 0.85 Adc) – 0.115 0.13

(VGS = 10 Vdc, ID = 1.7 Adc) – – 0.27
(VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150°C) – – 0.25
Vdc, VGS = 0 Vd
Vdc,
Coss – 110 150
f = 1.0 MHz)
Rise Time (VDD = 30 Vdc, ID = 1.7 Adc, tr – 9.0 20
VGS = 10 Vdc
Vdc,
(VDS = 48 Vdc, ID = 1.7 Adc, Q1 – 2.0 –

VGS = 10 Vdc) Q2 – 5.0 –
Q3 – 4.0 –
(IS = 1.7 Adc, VGS = 0 Vdc, – 0.85 1.6
TJ = 150°C) – 0.7 –
ta – 34 –
(IS = 1.7
1 7 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 6.0 –
Charge
(Measured from the drain lead 0.25″ from package to center of die) – 4.5 –

(Measured from the source lead 0.25″ from package to source bond pad) – 7.5 –
Cpk =
3 x SIGMA
http://onsemi.com
629
MMFT3055V
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SAFE OPERATING AREA
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases non–linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal temperature.
Resistance–General Data and Its Use.” Although many E–FETs can withstand the stress of
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 µs. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 13). Maximum
exceed (TJ(MAX) – TC)/(RθJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated E–FET can be safely used assumed to equal the values indicated.
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PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

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636
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These Power MOSFETs are designed for low voltage, high speed
switching applications in power supplies, converters and power motor
controls, these devices are particularly well suited for bridge circuits http://onsemi.com
1 AMPERE
transients. 60 VOLTS
• Avalanche Energy Specified RDS(on) = 140 m
N–Channel


Drain Current – Continuous @ 100°C ID 1.2 MARKING
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 5.0 Apk DIAGRAM
Total PD @ TA = 25°C mounted on 1″ sq. PD 2.1 Watts
Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 1.7 4
TO–261AA TBD
0.70″ sq. Drain pad on FR–4 bd material CASE 318E LWW
Total PD @ TA = 25°C mounted on min. 0.94 1 STYLE 3
Drain pad on FR–4 bd material 2
3
L = Location Code
Range 175
WW = Work Week
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak 58 PIN ASSIGNMENT
IL = 3.4 Apk, L = 10 mH, RG = 25 Ω )
4 ()%
– Junction to Ambient on 1″ sq. Drain RθJA 70
– Junction to Ambient on 0.70″ sq. Drain RθJA 88
– Junction to Ambient on min. Drain pad RθJA 159
on FR–4 bd material 1 2 3
Maximum Lead Temperature for Soldering TL 260 °C )'1 ()% ;(1
MMFT3055VLT1 SOT–223 1000 Tape & Reel
MMFT3055VLT3 SOT–223 4000 Tape & Reel

November, 2000 – Rev. 2 MMFT3055VL/D
MMFT3055VL

OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3.) V(BR)DSS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Gate Threshold Voltage (Cpk ≥ 2.0) (Note 3.) VGS(th)
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Note 3.) RDS(on) – 0.125 0.14 Ohm
(VGS = 5.0 Vdc, ID = 0.75 Adc)

(VGS = 5.0 Vdc, ID = 1.5 Adc) – – 0.25
(VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150°C) – – 0.24
Vdc, VGS = 0 Vd
Vdc,
Coss – 110 150
f = 1.0 MHz)
VGS = 5
5.00 Vdc
Vdc,
(VDS = 48 Vdc, ID = 1.5 Adc, Q1 – 1.0 –

VGS = 5.0 Vdc) Q2 – 4.0 –
Q3 – 3.5 –
(IS = 1.5 Adc, VGS = 0 Vdc, – 0.82 1.2
TJ = 150°C) – 0.68 –
ta – 29 –
(IS = 1.5
1 5 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 12 –
Charge

Cpk =
3 x SIGMA
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This miniature surface mount MOSFET features ultra low RDS(on)
and true logic level performance. It is capable of withstanding high
energy in the avalanche and commutation modes and the http://onsemi.com
MMFT5P03HD devices are designed for use in low voltage, high
5 AMPERES
speed switching applications where power efficiency is important. 30 VOLTS
Typical applications are dc–dc converters, and power management in RDS(on) = 100 mΩ
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage P–Channel
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
Life
• Miniature SOT–223 Surface Mount Package – Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits MARKING
• Diode Exhibits High Speed, With Soft Recovery DIAGRAM
• Avalanche Energy Specified 4
TO–261AA 5P03H
CASE 318E LWW
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WW = Work Week
PIN ASSIGNMENT
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November, 2000 – Rev. 3 MMFT5P03HD/D
MMFT5P03HD

Negative sign for P–Channel devices omitted for clarity
Rating Symbol Max Unit
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 V
Gate–to–Source Voltage – Continuous VGS ± 20 V
1″ SQ. Thermal Resistance – Junction to Ambient RTHJA 40 °C/W
FR–4 or G–10 PCB Total Power Dissipation @ TA = 25°C PD 3.13 Watts
Linear Derating Factor 25 mW/°C
Drain Current – Continuous @ TA = 25°C ID 5.2 A
10 seconds Continuous @ TA = 70°C ID 4.1 A
Minimum Thermal Resistance – Junction to Ambient RTHJA 80 °C/W
FR–4 or G–10 PCB Total Power Dissipation @ TA = 25°C PD 1.56 Watts
Linear Derating Factor 12.5 mW/°C
Drain Current – Continuous @ TA = 25°C ID 3.7 A
10 seconds Continuous @ TA = 70°C ID 2.9 A
150
(VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.5 mH, RG = 25 W) 250
http://onsemi.com
647
MMFT5P03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 24 Vdc, VGS = 0 Vdc) – – 1.0
ON CHARACTERISTICS(1)
(VDS = VGS, ID = 0.25 mAdc) 1.0 1.75 3.0
(VGS = 10 Vdc, ID = 5.2 Adc) – 79 100
(VGS = 4.5 Vdc, ID = 2.6 Adc) – 119 150
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) (Note 2.) gFS 2.0 4.0 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 220 440
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
VGS = 4
4.55 Vdc
Vdc,
(VDS = 24 Vdc, ID = 4.0 Adc, Q1 – 1.7 –

VGS = 10 Vdc) (Note 2.) Q2 – 6.3 –
Q3 – 4.6 –

Forward On–Voltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (Note 2.) VSD Vdc
(IS = 4.0 Adc, VGS = 0 Vdc, – 1.1 1.5
TJ = 125°C) – 0.89 –
(IS = 4.0 Adc, VGS = 0 Vdc, ta – 20 –

dIS/dt = 100 A/µs) (Note 2.) tb – 19 –
Cpk =
3 x SIGMA
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The power dissipation of the SOT–223 is a function of 150°C – 25°C = 3.13 watts
PD =
temperature of the die, RθJA, the thermal resistance from circuit board to achieve a power dissipation of 3.13 watts.
the device junction to ambient, and the operating There are other alternatives to achieving higher power
temperature, TA. Using the values provided on the data dissipation from the SOT–223 package. One is to increase
sheet for the SOT–223 package, PD can be calculated as the area of the drain pad. By increasing the area of the drain
follows: pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
TJ(max) – TA
PD = one will be giving up area on the printed circuit board
The values for the equation are found in the maximum technology.
ratings table on the data sheet. Substituting these values Another alternative would be to use a ceramic substrate
into the equation for an ambient temperature TA of 25°C, or an aluminum core board such as Thermal Cladt. Using
one can calculate the power dissipation of the device which a board material such as Thermal Clad, an aluminum core
in this case is 3.13 watts. board, the power dissipation can be doubled using the same
footprint.
http://onsemi.com
654
MMFT5P03HD


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
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switching applications such as switching regulators, dc–dc converters,
applications.
300 mA
• Low Drive Requirement RDS(on) = 1.7
N–Channel
The formed leads absorb thermal stress during soldering

Drain–to–Source Voltage VDS 60 Volts
Gate–to–Source Voltage – Non–Repetitive VGS ±30 Volts
Drain Current ID 300 mAdc

Total Power Dissipation @ TA = 25°C PD 0.8 Watts MARKING
(Note 1.) DIAGRAM
Operating and Storage Temperature TJ, Tstg –65 to °C 4
TO–261AA FT960
Range 150
CASE 318E LWW
THERMAL CHARACTERISTICS 1 STYLE 3
2
3
Junction–to–Ambient
FT960 = Device Code
Maximum Temperature for Soldering TL 260 °C L = Location Code
Purposes WW = Work Week
1. Device mounted on a FR–4 glass epoxy printed circuit board using minimum
recommended footprint. PIN ASSIGNMENT
4 ()%
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MMFT960T1

OFF CHARACTERISTICS
(VGS = 0, ID = 10 µA)
Zero Gate Voltage Drain Current IDSS – – 10 µAdc

(VDS = 60 V, VGS = 0)

(VGS = 15 Vdc, VDS = 0)

Static Drain–to–Source On–Resistance RDS(on) – – 1.7 Ohms

(VGS = 10 Vdc, ID = 1.0 A)

(VGS = 10 V, ID = 0.5 A) – – 0.8
(VGS = 10 V, ID = 1.0 A) – – 1.7
(VDS = 25 V, ID = 0.5 A)
(VDS = 25 VV, VGS = 0
0,
f = 1.0 MHz)
Transfer Capacitance Crss – 7.0 –
Total Gate Charge Qg – 3.2 – nC
(VGS = 10 V
V, ID = 1.0
1 0 A,
A
VDS = 48 V)
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The 156°C/W for the SOT-223 package assumes the use
follows:
TJ(max) – TA
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150°C
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100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
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N–Channel SO–8
provide protection against ESD and unexpected transients. These http://onsemi.com
miniature surface mount MOSFETs feature low RDS(on) and true logic
level performance. They are capable of withstanding high energy in 10 AMPERES
the avalanche and commutation modes and the drain–to–source diode 20 VOLTS
has a very low reverse recovery time. EZFET devices are designed for
use in low voltage, high speed switching applications where power RDS(on) = 15 m
efficiency is important.
• Zener Protected Gates Provide Electrostatic Discharge Protection N–Channel


Rating Symbol Value Unit DIAGRAM
Gate–to–Source Voltage – Continuous VGS ± 12 Vdc SO–8
10N02Z
8 CASE 751
Drain Current – Continuous @ TA = 25°C ID 10 Adc LYWW
STYLE 12
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 80 Apk 1
L = Location Code
(Note 1.)
Y = Year
Operating and Storage Temperature Range TJ, Tstg – 55 to °C WW = Work Week
150
Thermal Resistance – Junction to Ambient RθJA 50 °C/W
Maximum Temperature for Soldering TL 260 °C PIN ASSIGNMENT
1. When mounted on 1″ square FR–4 or G–10 board (VGS = 4.5 V, @
10 Seconds) Source 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
Gate 4 5 Drain
Top View
MMSF10N02ZR2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 3 MMSF10N02Z/D
MMSF10N02Z

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 10
Gate–Body Leakage Current (VGS = ± 12 Vdc, VDS = 0 Vdc) IGSS – 0.6 1.5 µAdc
(VDS = VGS, ID = 0.25 mAdc) 0.5 0.72 1.1
(VGS = 4.5 Vdc, ID = 10 Adc) – 13 15
(VGS = 2.7 Vdc, ID = 5.0 Adc) – 16 19
Forward Transconductance (VDS = 9.0 Vdc, ID = 5.0 Adc) gFS 11 14 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 775 810
f = 1.0 MHz)
Turn–Off Delay Time VGS = 4.0 Vdc, RG = 10 Ω) td(off) – 325 640
(VDS = 16 Vdc, ID = 10 Adc, Q1 – 2.5 –

VGS = 4.0 Vdc) Q2 – 13 –
Q3 – 9.0 –

(IS = 10 Adc, VGS = 0 Vdc)
– 0.83 1.2
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
– 0.68 –
(IS = 10 Ad
Adc, VGS = 0 VdVdc,
ta – 240 –
dIS/dt = 100 A/µs)
tb – 530 –
Cpk =
3 x SIGMA
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The Forward Biased Safe Operating Area curves the total power averaged over a complete switching cycle
define the maximum simultaneous drain–to–source must not exceed (T J(MAX) – T C )/(RθJC ).
voltage and drain current that a transistor can handle A power MOSFET designated E–FET can be safely
safely when it is forward biased. Curves are based upon used in switching circuits with unclamped inductive
maximum peak junction temperature and a case loads. For reliable operation, the stored energy from
temperature (T C ) of 25°C. Peak repetitive pulsed power circuit inductance dissipated in the transistor while in
limits are determined by using the thermal response data avalanche must be less than the rated limit and must be
in conjunction with the procedures discussed in AN569, adjusted for operating conditions differing from those
“Transient Thermal Resistance – General Data and Its specified. Although industry practice is to rate in terms
Use.” of energy, avalanche energy capability is not a constant.
Switching between the off–state and the on–state may The energy rating decreases non–linearly with an
traverse any load line provided neither rated peak current increase of peak current in avalanche and peak junction
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the temperature.
transition time (t r, tf ) does not exceed 10 µs. In addition

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PD = 150°C – 25°C = 2.5 Watts
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the device junction to ambient; and the operating The 50°C/W for the SO–8 package assumes the
TJ(max) – TA
RθJA
http://onsemi.com
669
MMSF10N02Z


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
670
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Preferred Device

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N–Channel SO–8
EZFETst are an advanced series of Power MOSFETs contain http://onsemi.com
monolithic back–to–back zener diodes. These zener diodes provide
protection against ESD and unexpected transients. These miniature 10 AMPERES
surface mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the 30 VOLTS
avalanche and commutation modes and the drain–to–source diode has RDS(on) = 13 mW
a very low reverse recovery time. EZFET devices are designed for use
in low voltage, high speed switching applications where power N–Channel

power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
disk drives and tape drives.
• Designed to Withstand 200 V Machine Model and 2000 V Human
Body Model
Life MARKING
• Logic Level Gate Drive – Can Be Driven by Logic ICs DIAGRAM
• Diode Is Characterized for Use In Bridge Circuits SO–8
• Diode Exhibits High Speed, With Soft Recovery 8 CASE 751
10N03Z
LYWW
• IDSS Specified at Elevated Temperature STYLE 12
• Mounting Information for SO–8 Package Provided 1
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
Source 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
Gate 4 5 Drain
Top View
This document contains information on a new product. Specifications and information Preferred devices are recommended choices for future use
herein are subject to change without notice. and best overall value.

November, 2000 – Rev. 1 MMSF10N03Z/D
MMSF10N03Z

Parameter Symbol Max Unit
Drain Current – Continuous @ TA = 25°C (Note 1.) ID 10 Adc
Drain Current – Continuous @ TA = 70°C (Note 1.) ID 7.7
Drain Current – Pulsed Drain Current (Note 3.) IDM 50
150
(VDD = 30 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 20 mH, RG = 25 W) 1000
THERMAL RESISTANCE
Parameter Symbol Typ Max Unit
Junction–to–Ambient (Note 1.) RqJA – 50 °C/W
Junction–to–Ambient (Note 2.) – 80
1. When mounted on 1″ square FR4 or G–10 board (VGS = 10 V, @ 10 seconds).
2. When mounted on minimum recommended FR4 or G–10 board (VGS = 10 V, @ Steady State).
http://onsemi.com
672
MMSF10N03Z

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS – – 3.0 µAdc
ON CHARACTERISTICS(1)
(VDS = VGS, ID = 0.25 mAdc) 1.0 1.2 1.7
(VGS = 10 Vdc, ID = 10 Adc) – 10 13
(VGS = 4.5 Vdc, ID = 5.0 Adc) – 13 18
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Vdc, VGS = 0 Vd
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Coss – 570 800
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Q3 – 8.1 –

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(IS = 10 Adc, VGS = 0 Vdc,
– 0.70 –
TJ = 125°C)
(IS = 2.3 Adc, VGS = 0 Vdc, ta – 180 –

dIS/dt = 100 A/µs) (Note 4.) tb – 280 –
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designed for use in low voltage, high speed switching applications where
7 AMPERES
power efficiency is important. Typical applications are dc–dc converters, 30 VOLTS
and power management in portable and battery powered products such as RDS(on) = 30 mW
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the N–Channel
• High Speed Switching Provides High Efficiency for DC/DC
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MARKING
DIAGRAM
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc SO–8
S1308
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc 8 CASE 751
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(Note 1.) Y = Year
WW = Work Week
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PIN ASSIGNMENT
THERMAL RESISTANCE
Source 1 8 Drain
Source 2 7 Drain
1. When mounted on 1″ square FR–4 or G–10 board
(VGS = 10 V, @ 10 Seconds) Source 3 6 Drain
2. Repetitive rating; pulse width limited by maximum junction temperature. Gate 4 5 Drain
Top View
MMSF1308R2 SO–8 2500 Tape & Reel


November, 2000 – Rev. 1 MMSF1308/D
MMSF1308

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 0.25 mAdc) 1.0 1.6 2.5
(VGS = 10 Vdc, ID = 7.0 Adc) – 22 30
(VGS = 4.5 Vdc, ID = 3.5 Adc) – 30 39
Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) gFS – 4.5 – Mhos
Vdc, VGS = 0 V
V,
Coss – 290 410
f = 1.0 MHz)
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Vdc,
(VDS = 15 Vdc, ID = 7.0 Adc, Q1 – 2.5 –

VGS = 10 Vdc) (Note 3.) Q2 – 6.0 –
Q3 – 8.0 –

Forward On–Voltage (IS = 7.0 Adc, VGS = 0 Vdc) (Note 3.) VSD Vdc
(IS = 7.0 Adc, VGS = 0 Vdc, – 0.85 1.0
TJ = 125°C) – 0.71 –
(IS = 7.0 Adc, VGS = 0 Vdc, ta – 20 –

dIS/dt = 100 A/µs) (Note 3.) tb – 15 –
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diode has a very low reverse recovery time. MiniMOSt devices are
designed for use in low voltage, high speed switching applications where
10 AMPERES
power efficiency is important. Typical applications are dc–dc converters, 30 VOLTS
and power management in portable and battery powered products such as RDS(on) = 15 mW
drives and tape drives. The avalanche energy is specified to eliminate the N–Channel
• High Speed Switching Provides High Efficiency for DC/DC
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MARKING
DIAGRAM
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc SO–8
S1310
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc 8 CASE 751
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Total Power Dissipation @ TA = 25°C PD 2.5 W L = Location Code
(Note 1.) Y = Year
WW = Work Week
150
PIN ASSIGNMENT
THERMAL RESISTANCE
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1. When mounted on 1″ square FR–4 or G–10 board Source 2 7 Drain
(VGS = 10 V, @ 10 Seconds) Source 3 6 Drain
2. Repetitive rating; pulse width limited by maximum junction temperature. Gate 4 5 Drain
Top View


MMSF1310

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 0.25 mAdc) 1.0 1.3 2.5
(VGS = 10 Vdc, ID = 10 Adc) – 9.5 15
(VGS = 4.5 Vdc, ID = 5.0 Adc) – 12.5 19
Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) gFS – 5.0 – Mhos
Vdc, VGS = 0 V
V,
Coss – 680 960
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(VDS = 15 Vdc, ID = 10 Adc, Q1 – 3.0 –

VGS = 10 Vdc) (Note 3.) Q2 – 4.0 –
Q3 – 7.0 –

Forward On–Voltage (IS = 10 Adc, VGS = 0 Vdc) (Note 3.) VSD Vdc
(IS = 10 Adc, VGS = 0 Vdc, – 0.82 1.0
TJ = 125°C) – 0.67 –
(IS = 10 Adc, VGS = 0 Vdc, ta – 23 –

dIS/dt = 100 A/µs) (Note 3.) tb – 30 –
Cpk =
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times may be approximated by the following: The resistive switching time variation versus gate resistance
tr = Q2 x RG/(VGG – VGSP) (Figure 8) shows how typical switching performance is
tf = Q2 x RG/VGSP affected by the parasitic circuit elements. If the parasitics
where were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is power electronic loads are inductive; the data in the figure
not constant. The simplest calculation uses appropriate is taken with a resistive load, which approximates an
values from the capacitance curves in a standard equation for optimally snubbed inductive load. Power MOSFETs may be
voltage change in an RC network. The equations are: safely operated into an inductive load; however, snubbing
td(on) = RG Ciss In [VGG/(VGG – VGSP)] reduces switching losses.
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storage products such as disk drives and tape drives. The avalanche P–Channel
Life


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• IDSS Specified at Elevated Temperature SO–8
S4P01
8 CASE 751
LYWW
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) STYLE 13
L = Location Code
Drain Current WW = Work Week
– Continuous @ TA = 25°C (Note 2.) ID 2.5 Adc
– Single Pulse (tp ≤ 10 µs) IDM 13 Apk PIN ASSIGNMENT
(Note 2.) N–C 1 8 Drain
Operating and Storage Temperature Range TJ, Tstg – 55 to °C Source 2 7 Drain
150 Source 3 6 Drain
Single Pulse Drain–to–Source Avalanche EAS 216 mJ Gate 4 5 Drain
(VDD = 20 Vdc, VGS = 5.0 Vdc, Top View
IL = 6.0 Apk, L = 12 mH, RG = 25 Ω)
Thermal Resistance – Junction to Ambient RθJA 50 °C/W ORDERING INFORMATION
(Note 2.)
MMSF2P02ER2 SO–8 2500 Tape & Reel
10 sec. max. Preferred devices are recommended choices for future use

November, 2000 – Rev. 5 MMSF2P02E/D
MMSF2P02E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
Threshold Temperature Coefficient (Negative) 4.7 – mV/°C
(VGS = 10 Vdc, ID = 2.0 Adc) – 0.19 0.25
(VGS = 4.5 Vdc, ID = 1.0 Adc) – 0.3 0.4
Vdc, VGS = 0 Vd
Vdc,
Coss – 220 300
f = 1.0 MHz)
VGS = 5
5.00 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
(VDS = 16 Vdc, ID = 2.0 Adc, Q1 – 1.1 –

VGS = 10 Vdc) Q2 – 3.3 –
Q3 – 2.5 –

(IS = 2.0 Adc, VGS = 0 Vdc, ta – 18 –

dIS/dt = 100 A/µs) tb – 16 –
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Although many E–FETs can withstand the stress of custom. The energy rating must be derated for temperature
drain–to–source avalanche at currents up to rated pulsed as shown in the accompanying graph (Figure 13). Maximum
current (IDM), the energy rating is specified at rated energy at currents below rated continuous ID can safely be
continuous current (ID), in accordance with industry assumed to equal the values indicated.

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avalanche and commutation modes and the drain–to–source diode has a
very low reverse recovery time. WaveFETt devices are designed for use 11.5 AMPERES
in low voltage, high speed switching applications where power efficiency
is important. Typical applications are dc–dc converters, and power 30 VOLTS
management in portable and battery powered products such as computers, RDS(on) = 12.5 mW
printers, cellular and cordless phones. They can also be used for low
voltage motor controls in mass storage products such as disk drives and N–Channel
tape drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional safety
margin against unexpected voltage transients.
• Characterized Over a Wide Range of Power Ratings
• Ultralow RDS(on) Provides Higher Efficiency and Extends Battery
Life in Portable Applications


• Miniature SO–8 Surface Mount Package – Saves Board Space SO–8
S3300
8 CASE 751
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MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) STYLE 12
Parameter Symbol Value Unit 1

L = Location Code
Drain–to–Gate Voltage VDGR 30 Vdc Y = Year
Gate–to–Source Voltage VGS ±20 Vdc WW = Work Week
Gate–to–Source Operating Voltage VGS ±16 Vdc
PIN ASSIGNMENT
150
Single Pulse Drain–to–Source Avalanche EAS 500 mJ Source Drain
1 8
(VDD = 25 Vdc, VGS = 10 Vdc, Source 2 7 Drain
L = 18.8 mH, IL(pk) = 7.3 A, VDS = 30 Vdc) Source 3 6 Drain
Gate 4 5 Drain
Top View


MMSF3300
POWER RATINGS (TJ = 25°C unless otherwise specified)

Parameter Symbol Value Unit
Drain Current – Continuous @ TA = 100°C Mounted on 1 inch square ID 8.2 Adc
Drain Current – Single Pulse (tp ≤ 10 ms) FR–4 or G10 board IDM 50 Adc
Linear Derating Factor VGS = 10 Vdc 20 mW/°C
Thermal Resistance – Junction–to–Ambient t ≤ 10 seconds RθJA 50 °C/W
Continuous Source Current (Diode Conduction) IS 3.0 Adc

Drain Current – Continuous @ TA = 100°C Mounted on 1 inch square ID 6.5 Adc
Linear Derating Factor VGS = 10 Vdc 12.5 mW/°C
Thermal Resistance – Junction–to–Ambient Steady State RθJA 80 °C/W

Drain Current – Continuous @ TA = 100°C Mounted on minimum recommended ID 6.5 Adc
Thermal Resistance – Junction–to–Ambient t ≤ 10 seconds RθJA 80 °C/W

Drain Current – Continuous @ TA = 100°C Mounted on minimum recommended ID 4.7 Adc
Thermal Resistance – Junction–to–Ambient Steady State RθJA 150 °C/W
http://onsemi.com
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MMSF3300
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 mAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – 0.004 1.0

(VDS = VGS, ID = 250 mAdc) 1.0 1.9 –
(VGS = 10 Vdc, ID = 10 Adc) – 10 12.5
(VGS = 4.5 Vdc, ID = 5.0 Adc) – 16 20
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) gFS 3.0 18 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 600 –
f = 1.0 MHz)

VGS = 4
4.55 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
(VDS = 15 Vdc, ID = 2.0 Adc, Q1 – 5.1 –

VGS = 10 Vdc) Q2 – 14 –
Q3 – 13 –

(IS = 2.3 Adc, VGS = 0 Vdc) – 0.78 1.1
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.60 –
(IS = 3.5 Adc, VGS = 0 Vdc, ta – 21 –

dIS/dt = 100 A/µs) tb – 19 –
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The switching characteristics of a MOSFET body diode are di/dts. The diode’s negative di/dt during ta is directly
very important in systems using it as a freewheeling or controlled by the device clearing the stored charge. However,
commutating diode. Of particular interest are the reverse the positive di/dt during tb is an uncontrollable diode
recovery characteristics which play a major role in characteristic and is usually the culprit that induces current
determining switching losses, radiated noise, EMI and RFI. ringing. Therefore, when comparing diodes, the ratio of tb/ta
System switching losses are largely due to the nature of the serves as a good indicator of recovery abruptness and thus
body diode itself. The body diode is a minority carrier device, gives a comparative estimate of probable noise generated. A
therefore it has a finite reverse recovery time, trr, due to the ratio of 1 is considered ideal and values less than 0.5 are
storage of minority carrier charge, QRR, as shown in the considered snappy.
typical reverse recovery wave form of Figure 16. It is this Compared to ON Semiconductor standard cell density low
stored charge that, when cleared from the diode, passes voltage MOSFETs, high cell density MOSFET diodes are
through a potential and defines an energy loss. Obviously, faster (shorter trr), have less stored charge and a softer reverse
repeatedly forcing the diode through reverse recovery further recovery characteristic. The softness advantage of the high
increases switching losses. Therefore, one would like a diode cell density diode means they can be forced through reverse
with short trr and low QRR specifications to minimize these recovery at a higher di/dt than a standard cell MOSFET diode
losses. without increasing the current ringing or the noise generated.
The abruptness of diode reverse recovery effects the In addition, power dissipation incurred from switching the
amount of radiated noise, voltage spikes, and current ringing. diode will be less due to the shorter recovery time and lower
The mechanisms at work are finite irremovable circuit switching losses.
parasitic inductances and capacitances acted upon by high
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http://onsemi.com
712
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RθJA
temperature ratings as shown on the data sheet. When *Soldering a device without preheating can cause excessive
using infrared heating with the reflow soldering thermal shock and stress which can result in damage to the
method, the difference shall be a maximum of 10°C. device.
http://onsemi.com
713
MMSF3300


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
714
(!# .
Preferred Device
#$%& '(
!
P–Channel SO–8
Life



• Mounting Information for SO–8 Package Provided SO–8
S3P02
CASE 751
8 LYWW
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.) STYLE 13
L = Location Code
Y = Year
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 30 Apk PIN ASSIGNMENT
(Note 2.) N–C 1 8 Drain
Operating and Storage Temperature Range TJ, Tstg – 55 to °C Source 2 7 Drain
150 Source 3 6 Drain
Single Pulse Drain–to–Source Avalanche EAS 567 mJ Gate 4 5 Drain
Top View
IL = 9.0 Apk, L = 14 mH, RG = 25 Ω)
Thermal Resistance – Junction to Ambient RθJA 50 °C/W ORDERING INFORMATION
(Note 2.)
MMSF3P02HDR2 SO–8 2500 Tape & Reel
10 sec. max. Preferred devices are recommended choices for future use

November, 2000 – Rev. 6 MMSF3P02HD/D
MMSF3P02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance RDS(on) Ohm
(VGS = 10 Vdc, ID = 3.0 Adc) – 0.06 0.075
(VGS = 4.5 Vdc, ID = 1.5 Adc) – 0.08 0.095
Vdc, VGS = 0 Vd
Vdc,
Coss – 740 920
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 16 Vdc, ID = 3.0 Adc, Q1 – 3.0 –
VGS = 10 Vdc) Q2 – 11 –
Q3 – 10 –

(IS = 3.0 Adc, VGS = 0 Vdc, – 1.35 1.75
TJ = 125°C) – 0.96 –
S Fi
See Figure 15
(IS = 3.0 Adc, VGS = 0 Vdc, ta – 32 –
dIS/dt = 100 A/µs) tb – 44 –
http://onsemi.com
716
MMSF3P02HD
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721
MMSF3P02HD

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TJ(max) – TA
RθJA
http://onsemi.com
722
MMSF3P02HD


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
723
( .
Preferred Device
#$%& '(

N–Channel SO–8
Life



S5N02
8 CASE 751
LYWW
STYLE 13
1
WW = Work Week
PIN ASSIGNMENT
Total Power Dissipation @ TA = 25°C PD 2.5 Watts N–C 1 8 Drain
(Note 1.)
Source 2 7 Drain
Source 3 6 Drain
150
Gate 4 5 Drain
IL = 15 Apk, L = 6.0 mH, RG = 25 Ω)
(Note 1.) Device Package Shipping
Purposes, 1/8″ from case for 10 seconds MMSF5N02HDR2 SO–8 2500 Tape & Reel
10 sec. max.

November, 2000 – Rev. 6 MMSF5N02HD/D
MMSF5N02HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 – –
(VDS = 20 Vdc, VGS = 0 Vdc) – 0.02 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 5.0 Adc) – 0.0185 0.025
(VGS = 4.5 Vdc, ID = 2.5 Adc) – 0.0219 0.040
Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) gFS 3.0 12 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 464 650
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
Turn–On Delay Time td(on) – 9.0 –
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 16 Vdc, ID = 5.0 Adc, Q1 – 3.0 –
VGS = 10 Vdc) Q2 – 7.5 –
Q3 – 6.0 –

(IS = 5.0 Adc, VGS = 0 Vdc, – 0.82 1.0
TJ = 125°C) – 0.69 –
S Fi
See Figure 15
(IS = 5.0 Adc, VGS = 0 Vdc, ta – 24 –
dIS/dt = 100 A/µs) tb – 8.0 –
http://onsemi.com
725
MMSF5N02HD

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730
MMSF5N02HD

9
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TJ(max) – TA
RθJA
http://onsemi.com
731
MMSF5N02HD


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
732
(!.
Preferred Device
#$%& '(
!
N–Channel SO–8
RDS(on) = 40 m
Life



S5N03
8 CASE 751
LYWW
STYLE 13
1
WW = Work Week
(Note 1.)
Source 2 7 Drain
Source 3 6 Drain
150
Gate 4 5 Drain
IL = 15 Apk, L = 4.0 mH, RG = 25 Ω)
(Note 1.)
10 sec. max.

MMSF5N03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
Static Drain–Source On–Resistance RDS(on) Ohms
(VGS = 10 Vdc, ID = 5.0 Adc) – 0.033 0.040
(VGS = 4.5 Vdc, ID = 2.5 Adc) – 0.04 0.050
Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) gFS 3.0 8.0 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 354 490
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
(VDS = 24 Vdc, ID = 5.0 Adc, Q1 – 3.4 –
VGS = 10 Vdc) Q2 – 6.6 –
Q3 – 5.6 –

– 0.88 1.3
(IS = 5 Adc, VGS = 0 Vdc, TJ = 125°C)
– 0.77 –
S Fi
See Figure 15
(IS = 5.0 Adc, VGS = 0 Vdc, ta – 21 –
dIS/dt = 100 A/µs) tb – 12 –
http://onsemi.com
734
MMSF5N03HD

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737
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738
MMSF5N03HD

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739
MMSF5N03HD

9
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50°C/W
TJ(max) – TA
RθJA
http://onsemi.com
740
MMSF5N03HD


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
741
("!.
Preferred Device
#$%& '(
" !
N–Channel SO–8
RDS(on) = 28 m
Life



S7N03
8 CASE 751
LYWW
STYLE 13
1
WW = Work Week
(Note 1.)
Source 2 7 Drain
Source 3 6 Drain
150
Gate 4 5 Drain
IL = 15 Apk, L = 4.0 mH, RG = 25 Ω)
(Note 1.)
10 sec. max.

MMSF7N03HD

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – 0.02 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance RDS(on) Ohms
(VGS = 10 Vdc, ID = 7.0 Adc) – 0.023 0.028
(VGS = 4.5 Vdc, ID = 3.5 Adc) – 0.029 0.040
Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) gFS 3.0 12 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 371 490
f = 1.0 MHz)
VGS = 4
4.55 Vdc
Vdc,
Turn–On Delay Time td(on) – 9.0 –
VGS = 10 Vdc
Vdc,
Fall Time tf – 39
S Fi
See Figure 8
(VDS = 16 Vdc, ID = 5.0 Adc, Q1 – 3.0 –
VGS = 10 Vdc) Q2 – 7.5 –
Q3 – 6.0 –

(IS = 7.0 Adc, VGS = 0 Vdc, – 0.82 1.0
TJ = 125°C) – 0.69 –
S Fi
See Figure 15
(IS = 7.0 Adc, VGS = 0 Vdc, ta – 24 –
dIS/dt = 100 A/µs) tb – 8.0 –
http://onsemi.com
743
MMSF7N03HD
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746
MMSF7N03HD
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747
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http://onsemi.com
748
MMSF7N03HD

9
$#
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mm

50°C/W
TJ(max) – TA
RθJA
to a high temperature, failure to complete soldering within a • When shifting from preheating to soldering, the
short time could result in device failure. Therefore, the maximum temperature gradient shall be 5°C or less.
following items should always be observed in order to
• After soldering has been completed, the device should
minimize the thermal stress to which the devices are
subjected.
be allowed to cool naturally for at least three minutes.
• Always preheat the device. Gradual cooling should be used as the use of forced
• The delta temperature between the preheat and cooling will increase the temperature gradient and
soldering should be 100°C or less.* result in latent failure due to mechanical stress.
• When preheating and soldering, the temperature of the • Mechanical stress or shock should not be applied
leads and the case must not exceed the maximum during cooling.
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering * Soldering a device without preheating can cause
method, the difference shall be a maximum of 10°C. excessive thermal shock and stress which can result in
damage to the device.
http://onsemi.com
749
MMSF7N03HD


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
750
("!8
#$%& '(
" !
N–Channel SO–8
EZFETst are an advanced series of Power MOSFETs which contain
monolithic back–to–back zener diodes. These zener diodes provide http://onsemi.com
protection against ESD and unexpected transients. These miniature
surface mount MOSFETs feature ultra low RDS(on) and true logic level 7 AMPERES
performance. They are capable of withstanding high energy in the
30 VOLTS
avalanche and commutation modes and the drain–to–source diode has a
very low reverse recovery time. EZFET devices are designed for use in RDS(on) = 30 mW
low voltage, high speed switching applications where power efficiency is
important. Typical applications are dc–dc converters, and power N–Channel
management in portable and battery powered products such as
drives and tape drives.
Life
• Designed to withstand 200V Machine Model and 2000V Human
Body Model MARKING
• Logic Level Gate Drive – Can Be Driven by Logic ICs DIAGRAM
• Diode Is Characterized for Use In Bridge Circuits SO–8
• Diode Exhibits High Speed, With Soft Recovery 8 CASE 751 7N03Z
LYWW
STYLE 12
• Mounting Information for SO–8 Package Provided 1
7N03Z = Device Code

L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
Source 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
Gate 4 5 Drain
Top View

January, 2001 – Rev. 1 MMSF7N03Z/D
MMSF7N03Z

Drain Current
– Continuous @ TA = 25°C (Note 1.) ID 7.5 Adc
– Continuous @ TA = 70°C (Note 1.) ID 5.6
– Pulsed Drain Current (Note 3.) IDM 60 Apk
Linear Derating Factor (Note 1.) 20 mW/°C
Linear Derating Factor (Note 2.) 12 mW/°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 Ω) 450
Thermal Resistance RθJA 50 °C/W
– Junction to Ambient (Note 1.) 80
– Junction to Ambient (Note 2.)
1. When mounted on 1″ square FR–4 or G–10 board (VGS = 10 V, @ 10 Seconds)
2. When mounted on 1″ square FR–4 or G–10 board (VGS = 10 V, @ Steady State)
http://onsemi.com
752
MMSF7N03Z

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – 0.03 2.0
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS – 1.3 5.0 µAdc
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
(VGS = 10 Vdc, ID = 7.5 Adc) – 22 30
(VGS = 4.5 Vdc, ID = 3.8 Adc) – 30 40
Forward Transconductance (VDS = 3.0 Vdc, ID = 3.8 Adc) (Note 4.) gFS 4.0 9.5 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 340 680
f = 1.0 MHz)
Turn–Off Delay Time VGS = 10 Vdc, RG = 6 Ω) (Note 4.) td(off) – 470 940
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6 Ω) (Note 4.) td(off) – 430 860
(VDS = 24 Vdc, ID = 5.0 Adc, Q1 – 3.5 –

VGS = 10 Vdc) (Note 4.) Q2 – 9.5 –
Q3 – 6.5 –

Forward On–Voltage (Note 4.) (IS = 7.5 Adc, VGS = 0 Vdc) (Note 4.) VSD Vdc
(IS = 7.5 Adc, VGS = 0 Vdc, – 0.83 1.6
TJ = 125°C) – 0.67 –
(IS = 7.5
7 5 Adc,
Ad VGS = 0 Vdc,
Vd
ta – 22 –
tb – 90 –
Cpk =
3 x SIGMA
http://onsemi.com
753
MMSF7N03Z

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RθJA
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759
MMSF7N03Z


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
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100°C

MASS ASSEMBLIES
5°C

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N–Channel TO–92

Rating Symbol MPF930 MPF960 MPF990 Unit
2 AMPERES
Drain–Source VDS 35 60 90 Vdc
Voltage 35, 60, 90 VOLTS
Drain–Gate Voltage VDG 35 60 90 Vdc RDS(on) = 0.7 Ω (MPF930)
Gate–Source RDS(on) = 0.8 Ω (MPF960)
±20
Voltage
– Continuous
VGS
VGSM ±40
Vdc
Vpk
RDS(on) = 1.2 Ω (MPF990)
– Non–repetitive
(tp ≤ 50 µs) N–Channel

Drain Current Adc
Continuous ID 2.0
(Note 1.)
Pulsed (Note 2.) IDM 3.0
Total Device PD
Dissipation 1.0 Watts
@ TA = 25°C 8.0 mW/°C

Derate above
25°C
Operating and TJ, Tstg –55 to 150 °C
Storage Junction
Temperature TO–92
Range CASE 29
Style 22
Thermal Resistance θJA 125 °C/W
12
3
current.
MARKING DIAGRAM
& PIN ASSIGNMENT
MPF930
YWW
1 3
Source Drain
2
Gate
Y = Year
WW = Work Week


November, 2000 – Rev. 3 MPF930/D
MPF930, MPF960, MPF990

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSX Vdc
(VGS = 0, ID = 10 µAdc) MPF930 35 – –
MPF960 60 – –
MPF990 90 – –
Gate Reverse Current (VGS = 15 Vdc, VDS = 0) IGSS – – 50 nAdc

Zero–Gate–Voltage Drain Current IDSS – – 10 µAdc
(VDS = Maximum Rating, VGS = 0)
Gate Threshold Voltage VGS(Th) 1.0 – 3.5 Vdc
(ID = 1.0 mAdc, VDS = VGS)
Drain–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 0.5 Adc) MPF930 – 0.4 0.7
MPF960 – 0.6 0.8
MPF990 – 0.6 1.2
(ID = 1.0 Adc) MPF930 – 0.9 1.4
MPF960 – 1.2 1.7
MPF990 – 1.2 2.4
(ID = 2.0 Adc) MPF930 – 2.2 3.0
MPF960 – 2.8 3.5
MPF990 – 2.8 4.8
Static Drain–Source On Resistance rDS(on) Ω
(VGS = 10 Vdc, ID = 1.0 Adc) MPF930 – 0.9 1.4
MPF960 – 1.2 1.7
MPF990 – 1.2 2.0
On–State Drain Current ID(on) 1.0 2.0 – Amps
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)
Forward Transconductance gfs 200 380 – mmhos
(VDS = 25 Vdc, ID = 0.5 Adc)
Turn–Off Time toff – 7.0 15 ns
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MPF930RLRE TO–92 2000 Tape & Reel
MPF930A TO–92 1000 Unit/Box
MPF930ARLRE TO–92 2000 Tape & Reel
MPF960RLRA TO–92 2000 Tape & Reel
MPF990RLRA TO–92 2000 Tape & Reel
MPF990RLRP TO–92 2000 Ammo Pack
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764
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N–Channel D2PAK
avalanche and commutation modes. The energy efficient design also
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offers a drain–to–source diode with fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly 75 AMPERES
well suited for bridge circuits where diode speed and commutating 30 VOLTS
safe operating areas are critical and offer additional safety margin
RDS(on) = 6.5 mΩ
• Source–to–Drain Diode Recovery Time Comparable to a Discrete N–Channel
Fast Recovery Diode D
• Short Heatsink Tab Manufactured – Not Sheared G
• Specially Designed Leadframe for Maximum Power Dissipation
S
D2PAK
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc CASE 418B
1 2
STYLE 2
– Non–Repetitive (tp ≤ 10 ms) VGSM ±20 Vpk MARKING DIAGRAM
Drain Current & PIN ASSIGNMENT
– Continuous ID 75 Adc 4
– Continuous @ 100°C ID 59 Drain
MTB1306
Total Power Dissipation @ TA = 25°C 2.5 Watts
YWW
(Note 1.)
Range 150
1 2 3
Single Pulse Drain–to–Source Avalanche EAS mJ Gate Drain Source
Energy – Starting TJ = 25°C 280
(VDD = 25 Vdc, VGS = 10 Vdc, Peak MTB1306 = Device Code
IL = 75 Apk, L = 0.1 mH, RG = 25 Ω) Y = Year
WW = Work Week
Purposes, 1/8″ from Case for 5.0 MTB1306 D2PAK 50 Units/Rail
seconds
MTB1306T4 D2PAK 800/Tape & Reel
pad size.

November, 2000 – Rev.1 MTB1306/D
MTB1306

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 30 – –
(VDS = 30 Vdc, VGS = 0 Vdc) – – 10
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 38 Adc) – 5.8 6.5
(VGS = 5.0 Vdc, ID = 38 Adc) – 7.4 8.5
(VGS = 10 Vdc, ID = 75 Adc) – 0.44 0.5
(VGS = 10 Vdc, ID = 38 Adc, TJ = 150°C) – – 0.38
Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) gFS 15 55 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 1305 1827
f = 1.0 MHz)

VGS = 55.0
0 Vdc
Vdc,
(VDS = 24 Vdc, ID = 75 Adc, Q1 – 8.3 –

VGS = 5.0 Vdc) Q2 – 25.3 –
Q3 – 17.2 –
(IS = 20 Adc, VGS = 0 Vdc) – 0.75 1.1
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.64 –
ta – 35 –
Adc VGS = 0 Vdc,
(IS = 20 Adc, Vdc
dIS/dt = 100 A/µs) tb – 53 –
Charge
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766
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N–Channel D2PAK
offers a drain–to–source diode with a fast recovery time. Designed for http://onsemi.com
RDS(on) = 160 mΩ
• Source–to–Drain Diode Recovery Time Comparable to a N–Channel
Discrete Fast Recovery Diode D
• Short Heatsink Tab Manufactured – Not Sheared G
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Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 200 Vdc D2PAK
CASE 418B
Gate–Source Voltage 1 2
STYLE 2
– Continuous VGS ± 20 Vdc 3
– Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
Drain Current – Continuous ID 20 Adc MARKING DIAGRAM
Drain Current – Continuous @ 100°C ID 12 & PIN ASSIGNMENT
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 60 Apk 4
Total Power Dissipation PD 125 Watts Drain
Total Power Dissipation @ TA = 25°C, 2.5 Watts
when mounted with the minimum
T20N20E
recommended pad size
YWW
Range 150
1 2 3
Gate Drain Source
T20N20E = Device Code
IL = 20 Apk, L = 3.0 mH, RG = 25 Ω)
Y = Year
Thermal Resistance °C/W WW = Work Week
– Junction to Case RθJC 1.0
– Junction to Ambient RθJA 62.5
– Junction to Ambient, when mounted RθJA 50
with the minimum recommended pad size Device Package Shipping
Purposes, 1/8″ from case for 10 MTB20N20E D2PAK 50 Units/Rail
seconds
MTB20N20ET4 D2PAK 800/Tape & Reel


November, 2000 – Rev. 3 MTB20N20E/D
MTB20N20E

OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS
(VDS = 200 Vdc, VGS = 0 Vdc) – – 10
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 – 4.0 Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) – 0.12 0.16 Ohm
(ID = 20 Adc) – – 3.84
(ID = 10 Adc, TJ = 125°C) – – 3.36
Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) gFS 8.0 11 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 378 535
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Figure 8)
(VDS = 160 Vdc, ID = 20 Adc, Q1 – 12 –
VGS = 10 Vdc)
Q2 – 24 –
Q3 – 22 –

Forward On–Voltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 20 Adc, VGS = 0 Vdc, – 1.0 1.35
TJ = 125°C) – 0.82 –
(S Figure
(See Fi 14)
(IS = 20 Adc, VGS = 0 Vdc, ta – 136 –
dIS/dt = 100 A/µs) tb – 103 –

Internal Drain Inductance LD – 4.5 – nH
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance LS – 7.5 – nH

(Measured from the source lead 0.25″ from package to source bond pad)
http://onsemi.com
773
MTB20N20E
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times may be approximated by the following: The resistive switching time variation versus gate resistance
tr = Q2 x RG/(VGG – VGSP) (Figure 9) shows how typical switching performance is
tf = Q2 x RG/VGSP affected by the parasitic circuit elements. If the parasitics
where were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is power electronic loads are inductive; the data in the figure
not constant. The simplest calculation uses appropriate is taken with a resistive load, which approximates an
values from the capacitance curves in a standard equation for optimally snubbed inductive load. Power MOSFETs may be
voltage change in an RC network. The equations are: safely operated into an inductive load; however, snubbing
td(on) = RG Ciss In [VGG/(VGG – VGSP)] reduces switching losses.
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INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE

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POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a PD = 150°C – 25°C = 2.5 Watts
function of the drain pad size. These can vary from the 50°C/W
minimum pad size for soldering to a pad size given for
The 50°C/W for the D2PAK package assumes the use of
maximum power dissipation. Power dissipation for a
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts. There are
maximum rated junction temperature of the die, RθJA, the
other alternatives to achieving higher power dissipation
thermal resistance from the device junction to ambient, and
from the surface mount packages. One is to increase the
the operating temperature, TA. Using the values provided
area of the drain pad. By increasing the area of the drain
on the data sheet, PD can be calculated as follows:
pad, the power dissipation can be increased. Although one
TJ(max) – TA can almost double the power dissipation with this method,
PD =
RθJA one will be giving up area on the printed circuit board
The values for the equation are found in the maximum which can defeat the purpose of using surface mount
ratings table on the data sheet. Substituting these values technology. For example, a graph of RθJA versus drain pad
into the equation for an ambient temperature TA of 25°C, area is shown in Figure 16.
one can calculate the power dissipation of the device. For a
D2PAK device, PD is calculated as follows.
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should be approximately 50% of the tab area. The opening Figure 17. Typical Stencil for DPAK and
for the leads is still a 1:1 registration. Figure 17 shows a D2PAK Packages
http://onsemi.com
779
MTB20N20E

being used. This profile shows temperature versus time. degrees cooler than the adjacent solder joint.

PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
780
!#
Preferred Device
#$%& '(
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P–Channel D2PAK
avalanche and commutation modes. Designed for low voltage, high
http://onsemi.com
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are 23 AMPERES
critical and offer additional safety margin against unexpected voltage 60 VOLTS
transients.
RDS(on) = 120 mΩ
P–Channel


Drain Current – Continuous @ 25°C ID 23 Adc
Drain Current – Continuous @ 100°C ID 15 4
D2PAK
Total Power Dissipation @ 25°C PD 90 Watts CASE 418B
1 2
Derate above 25°C 0.60 W/°C STYLE 2
Total Power Dissipation @ TA = 25°C 3.0 3
(Note 1.)
MARKING DIAGRAM
Range 175 & PIN ASSIGNMENT
4
Drain
IL = 23 Apk, L = 3.0 mH, RG = 25 Ω)
Thermal Resistance °C/W MTB23P06V
– Junction to Case RθJC 1.67 YWW
– Junction to Ambient (Note 1.) RθJA 50
Maximum Lead Temperature for Soldering TL 260 °C 1 2 3
Purposes, 1/8″ from Case for 10 Gate Drain Source
seconds
1. When surface mounted to an FR4 board using the minimum recommended MTB23P06V = Device Code
pad size. Y = Year
WW = Work Week
MTB23P06V D2PAK 50 Units/Rail
MTB23P06VT4 D2PAK 800/Tape & Reel


November, 2000 – Rev.2 MTB23P06V/D
MTB23P06V

OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 11.5 Adc) RDS(on) – 0.093 0.12 Ohm
(VGS = 10 Vdc, ID = 23 Adc) – 2.1 3.3
(VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150°C) – – 3.2
(VDS = 10.9 Vdc, ID = 11.5 Adc) 5.0 11.5 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 380 530
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 23 Adc, Q1 – 7.0 –
VGS = 10 Vdc) Q2 – 18 –
Q3 – 14 –

– 2.2 3.5
(IS = 23 Adc, VGS = 0 Vdc, TJ = 150°C)
– 1.8 –
ta – 100 –
(IS = 23 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 41 –
Charge

(Measured from contact screw on tab to center of die) – 3.5 –
(Measured from the drain lead 0.25″ from package to center of die) 4.5
http://onsemi.com
782
MTB23P06V
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786
MTB23P06V

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787
MTB23P06V

SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode ÇÇ
ÇÇ ÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇ ÇÇ

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http://onsemi.com
788
MTB23P06V


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
789
)
Preferred Device
#$%& '(
)
N–Channel D2PAK
converters and PWM motor controls. These devices are particularly 29 AMPERES
RDS(on) = 70 mΩ
G
S
D2PAK
CASE 418B
1 2
Drain Current – Continuous ID 29 Adc STYLE 2
MARKING DIAGRAM
Derate above 25°C 1.0 W/°C & PIN ASSIGNMENT
Total Power Dissipation @ TA = 25°C 2.5 Watts 4
(Note 1.) Drain

Range 150
T29N15E
YWW
IL = 29 Apk, L = 1.0 mH, RG = 25 Ω)
1 2 3
– Junction to Ambient RθJA 62.5 T29N15E = Device Code
– Junction to Ambient (Note 1.) RθJA 50 Y = Year
pad size. Device Package Shipping
MTB29N15E D2PAK 50 Units/Rail


MTB29N15E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 150 – –
(VDS = 150 Vdc, VGS = 0 Vdc) – – 10
(VDS = VGS, ID = 250 µAdc) 2.0 2.7 4.0
(VGS = 10 Vdc, ID = 14.5 Adc) – 0.054 0.07
Drain–to–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc

(ID = 29 Adc) – – 2.4
(ID = 14.5 Adc, TJ = 125°C) – – 2.1
Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) gFS 10 20 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 450 630
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(VDS = 120 Vdc, ID = 29 Adc, Q1 – 12 –

VGS = 10 Vdc) Q2 – 37 –
Q3 – 23 –

(IS = 29 Adc, VGS = 0 Vdc) – 0.92 1.3
(IS = 29 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.84 –
ta – 126 –
(IS = 29 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 48 –
Charge

(Measured from the contact screw on tab to center of die) – 3.5 –
Internal Source Inductance LS
http://onsemi.com
791
MTB29N15E
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792
MTB29N15E
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794
MTB29N15E
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795
MTB29N15E

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796
MTB29N15E


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
797
!
Preferred Device
#$%& '(
!
* %+%
N–Channel D2PAK
speed switching applications in power supplies, converters and power http://onsemi.com
transients.
RDS(on) = 50 mΩ
N–Channel
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) D

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc G
S
– Non–Repetitive (tp ≤ 10 ms) VGSM ±20 Vpk
Drain Current – Continuous ID 30 Adc
Drain Current – Continuous @ 100°C ID 20
4
Total Power Dissipation PD 90 Watts D2PAK
Derate above 25°C 0.6 W/°C CASE 418B
1 2
Total Power Dissipation @ TA = 25°C 3.0 Watts STYLE 2
(Note 1.) 3
Operating and Storage Temperature TJ, Tstg – 55 to °C MARKING DIAGRAM

Range 175
& PIN ASSIGNMENT
IL = 30 Apk, L = 0.342 mH, RG = 25 Ω)
Thermal Resistance °C/W T30N06VL
seconds
1. When surface mounted to an FR4 board using the minimum recommended T30N06VL = Device Code
pad size. Y = Year
WW = Work Week
MTB30N06VL D2PAK 50 Units/Rail
MTB30N06VLT4 D2PAK 800/Tape & Reel


November, 2000 – Rev. 5 MTB30N06VL/D
MTB30N06VL

OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Static Drain–to–Source On–Resistance (VGS = 5 Vdc, ID = 15 Adc) RDS(on) – 0.033 0.05 Ohms
(VGS = 5 Vdc, ID = 30 Adc) – 1.1 1.8
(VGS = 5 Vdc, ID = 15 Adc, TJ = 150°C) – – 1.73
Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) gFS 13 21 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 360 500
f = 1.0 MHz)

VGS = 5 Vdc,
Vdc
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 30 Adc, Q1 – 5 –
VGS = 5 Vdc) Q2 – 17 –
Q3 – 15 –
– 0.98 1.6
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
– 0.89 –
ta – 49 –
Adc VGS = 0 Vdc,
(IS = 30 Adc, Vdc
dIS/dt = 100 A/µs) tb – 37 –
Charge


http://onsemi.com
799
MTB30N06VL
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800
MTB30N06VL
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MTB30N06VL
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MTB30N06VL
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803
MTB30N06VL

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MTB30N06VL

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http://onsemi.com
805
MTB30N06VL


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
806
!#
Preferred Device
#$%& '(
!
P–Channel D2PAK
http://onsemi.com
speed switching applications in power supplies, converters and power
transients.
RDS(on) = 80 mΩ
P–Channel


D2PAK
1 2
Total Power Dissipation @ TA = 25°C 3.0 3
(Note 1.)
MARKING DIAGRAM
4
Drain
IL = 30 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance °C/W MTB30P06V
seconds
1. When surface mounted to an FR4 board using the minimum recommended MTB30P06V = Device Code
pad size. Y = Year
WW = Work Week
MTB30P06V D2PAK 50 Units/Rail
MTB30P06VT4 D2PAK 800/Tape & Reel


November, 2000 – Rev.2 MTB30P06V/D
MTB30P06V

OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
(VGS = 10 Vdc, ID = 30 Adc) – 2.0 2.9
(VGS = 10 Vdc, ID = 15 Adc, TJ = 150°C) – – 2.8
(VDS = 8.3 Vdc, ID = 15 Adc) 5.0 7.9 –
Vdc, VGS = 0 Vd
Vdc,
Coss – 524 730
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 30 Adc, Q1 – 9.0 –
VGS = 10 Vdc) Q2 – 26 –
Q3 – 20 –

– 2.3 3.0
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
– 1.9 –
ta – 107 –
(IS = 30 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 68 –
Charge

(Measured from the drain lead 0.25″ from package to center of die) 4.5
http://onsemi.com
808
MTB30P06V
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809
MTB30P06V
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810
MTB30P06V
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http://onsemi.com
811
MTB30P06V
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812
MTB30P06V

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813
MTB30P06V

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ÇÇ ÇÇÇ ÇÇ
ÇÇ
ÇÇ ÇÇÇ
ÇÇÇÇÇÇ
http://onsemi.com
814
MTB30P06V


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
815
!
Preferred Device
#$%& '(
!
N–Channel D2PAK
transients.
RDS(on) = 40 mΩ
N–Channel

S
– Non–Repetitive (tp ≤ 50 µs) VGSM ±25 Vpk
Drain Current – Continuous @ 100°C ID 22.6 4
D2PAK
1 2
(Note 1.)
4
Drain
IL = 32 Apk, L = 0.1 mH, RG = 25 Ω)
Thermal Resistance °C/W MTB36N06V
seconds
1. When surface mounted to an FR4 board using the minimum recommended MTB36N06V = Device Code
pad size. Y = Year
WW = Work Week
MTB36N06V D2PAK 50 Units/Rail
MTB36N06VT4 D2PAK 800/Tape & Reel


November, 2000 – Rev. 3 MTB36N06V/D
MTB36N06V

OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) – 0.034 0.04 Ohm
(VGS = 10 Vdc, ID = 32 Adc) – 1.25 1.54
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150°C) – – 1.47
Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) gFS 5.0 7.83 – mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 337 470
f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 74.8 150

VGS = 10 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 32 Adc, Q1 – 7 –
VGS = 10 Vdc) Q2 – 17 –
Q3 – 13 –
– 1.03 2.0
(IS = 32 Adc, VGS = 0 Vdc, TJ = 150°C)
– 0.94 –
ta – 64 –
Adc VGS = 0 Vdc,
(IS = 32 Adc, Vdc
dIS/dt = 100 A/µs) tb – 28 –
Charge


http://onsemi.com
817
MTB36N06V
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818
MTB36N06V
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http://onsemi.com
819
MTB36N06V
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820
MTB36N06V
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http://onsemi.com
821
MTB36N06V

44
848
8
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822
MTB36N06V

ÇÇÇÇÇÇ ÇÇ

ÇÇ ÇÇÇ ÇÇ
ÇÇ
ÇÇ ÇÇÇ
ÇÇÇÇÇÇ
http://onsemi.com
823
MTB36N06V


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
824

Preferred Device
#$%& '(

N–Channel D2PAK
RDS(on) = 40 mΩ
G
S
D2PAK
CASE 418B
1 2
Drain Current – Continuous ID 40 Adc STYLE 2
MARKING DIAGRAM
Derate above 25°C 1.35 W/°C & PIN ASSIGNMENT
(Note 1.) Drain

Range 150
T40N10E
YWW
IL = 40 Apk, L = 1.0 mH, RG = 25 Ω)
1 2 3
– Junction to Ambient RθJA 62.5 T40N10E = Device Code
– Junction to Ambient (Note 1.) RθJA 50 Y = Year
pad size. Device Package Shipping
MTB40N10E D2PAK 50 Units/Rail


MTB40N10E

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 100 – –
Temperature Coefficient (Positive) (Cpk ≥ 2.0) (Note 4.) – 112 – mV/°C
(VDS = 100 Vdc, VGS = 0 Vdc) – – 10
(VDS = VGS, ID = 250 µAdc) 2.0 2.9 4.0
(VGS = 10 Vdc, ID = 20 Adc) (Cpk ≥ 2.0) (Note 4.) – 0.033 0.04
Drain–to–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc

(ID = 40 Adc) – – 1.9
(ID = 20 Adc, TJ = 125°C) – – 1.7
Vdc, VGS = 0 Vd
Vdc,
Coss – 620 1240
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 80 Vdc, ID = 40 Adc, Q1 – 15 –
VGS = 10 Vdc) Q2 – 40 –
Q3 – 29 –
(IS = 40 Adc, VGS = 0 Vdc) – 0.96 1.0
(IS = 40 Adc, VGS = 0 Vdc, TJ = 125°C) – 0.88 –
(S Figure
(See Fi 14)
ta – 117 –
(IS = 40 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) tb – 35 –
Charge
(Measured from the contact screw on tab to center of die) – 3.5 –
Internal Source Inductance LS
Ť
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3 sigma
Ť
http://onsemi.com
826
MTB40N10E
8 8
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827
MTB40N10E
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828
MTB40N10E
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N–Channel D2PAK
transients.
RDS(on) = 28 mΩ
N–Channel

Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc G
S
D2PAK
1 2
(Note 1.)
4
Drain
IL = 42 Apk, L = 0.454 µH, RG = 25 Ω)
Thermal Resistance °C/W MTB50N06V
Purposes, 1/8″ from case for 10 Gate Drain Source
seconds
1. When surface mounted to an FR4 board using the minimum recommended MTB50N06V = Device Code
pad size. Y = Year
WW = Work Week
MTB50N06V D2PAK 50 Units/Rail
MTB50N06VT4 D2PAK 800/Tape & Reel


November, 2000 – Rev. 4 MTB50N06V/D
MTB50N06V

OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS – – 100 nAdc
(ID = 42 Adc) – 1.4 1.7
(ID = 21 Adc, TJ = 150°C) – – 1.6
Vdc, VGS = 0 Vd
Vdc,
Coss – 465 660
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 42 Adc, Q1 – 9 –
VGS = 10 Vdc) Q2 – 21 –
Q3 – 16 –
– 1.06 2.5
(IS = 42 Adc, VGS = 0 Vdc, TJ = 150°C)
– 0.99 –
(S Figure
(See Fi 14)
ta – 73 –
Adc VGS = 0 Vdc,
(IS = 42 Adc, Vdc
dIS/dt = 100 A/µs) tb – 11 –
Charge

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150°C
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100°C

MASS ASSEMBLIES
5°C

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* %+%
N–Channel D2PAK
transients.
RDS(on) = 32 mΩ
N–Channel

S
Drain Current – Continuous @ 100°C ID 30
4
Total Power Dissipation @ 25°C PD 125 Watts D2PAK
Derate above 25°C 0.83 W/°C CASE 418B
1 2
Total Power Dissipation @ TA = 25°C 3.0 Watts STYLE 2
(Note 1.) 3

Range 175
& PIN ASSIGNMENT
IL = 42 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance °C/W T50N06VL
seconds
1. When surface mounted to an FR4 board using the minimum recommended T50N06VL = Device Code
pad size. Y = Year
WW = Work Week
MTB50N06VL D2PAK 50 Units/Rail
MTB50N06VLT4 D2PAK 800/Tape & Reel


November, 2000 – Rev. 3 MTB50N06VL/D
MTB50N06VL

OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = .25 mAdc) 60 – – Vdc
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
Static Drain–to–Source On–Resistance (VGS = 5 Vdc, ID = 21 Adc) RDS(on) – 0.025 0.032 Ohms
(VGS = 5 Vdc, ID = 42 Adc) – 1.2 1.6
(VGS = 5 Vdc, ID = 21 Adc, TJ = 150°C) – – 1.5
Forward Transconductance (VDS = 6 Vdc, ID = 20 Adc) gFS 17 28 – Mhos
Vdc, VGS = 0 Vd
Vdc,
Coss – 508 710
f = 1.0 MHz)

VGS = 5 Vdc,
Vdc
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 42 Adc, Q1 – 11 –
VGS = 5 Vdc) Q2 – 20 –
Q3 – 16 –
– 1.03 2.5
(IS = 42 Adc, VGS = 0 Vdc, TJ = 150°C)
– 0.94 –
ta – 63.8 –
Adc VGS = 0 Vdc,
(IS = 42 Adc, Vdc
dIS/dt = 100 A/µs) tb – 27.3 –
Charge

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850
MTB50N06VL


PEAK AT
160°C
150°C
150°C
40 TO 80 SECONDS
MASS OF ASSEMBLY)
100°C

MASS ASSEMBLIES
5°C

http://onsemi.com
851
#!.
Preferred Device
#$%& '(
!
* %+%
P–Channel D2PAK
against unexpected voltage transients. RDS(on) = 25 mΩ
• Source–to–Drain Diode Recovery Time Comparable to a P–Channel
Discrete Fast Recovery Diode
• Short Heatsink Tab Manufactured – Not Sheared

Drain–Source Voltage VDSS 30 Vdc D2PAK
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc CASE 418B
1 2

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DL135/D

PUBLICATION ORDERING INFORMATION

Power MOSFET Numeric Data Sheet

Chapter 1: Power MOSFET Data Sheets

Device Function Page

Device Function Page

Device Function Page

Table 1. ChipFET – Case 1206A

Table 2. SO-8 (MiniMOS) – Case 751–06

Devices listed in bold, italic are ON Semiconductor preferred devices.

Table 2. SO-8 (MiniMOS) – Case 751–06 (continued)

Table 3. SO–8 FETKY –– Case 751–06

Table 5. Micro8 – Case 846A–02

Table 6. SOT-223 – Case 318E–04

Table 7. TSOP–6 – Case 318G–02

Table 8. TSSOP–8 – Case 318G–02

Table 9. SOT–23 – Case 318–08

Table 10. SC–70 / SOT–323 – Case 419–02

Table 11. SC–88 / SOT–363 – Case 419B–01

Table 12. DPAK – Case 369A–13 (TO–252)

Table 13. D2PAK – Case 418B–03 (TO–264)

Table 14. TO-220AB – Case 221A–09

Table 15. TO-247 (Isolated Mounting Hole) – Case 340K–01

Table 16. TO-264 – Case 340G–02

Table 17. SMARTDISCRETES

Table 18. TO-92

Table 19. Ignition IGBTs – Insulated Gate Bipolar Transistors

MAXIMUM RATINGS (–55°C ≤ TJ ≤ 175°C unless otherwise noted)

NGD15N41CLT4 DPAK 2500/Tape & Reel

This document contains information on a product under development. ON Semiconductor

 Semiconductor Components Industries, LLC, 2001 21 Publication Order Number:

UNCLAMPED COLLECTOR–TO–EMITTER AVALANCHE CHARACTERISTICS (–55°C ≤ TJ ≤ 175°C)

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

Zero Gate Voltage Collector Current ICES VCE = 300 V, – – 40 µADC

SMARTDISCRETES devices are an advanced series of Power 52 AMPERES

 Semiconductor Components Industries, LLC, 2001 23 Publication Order Number:

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Zero Gate Voltage Drain Current IDSS µAdc

(VDS = 32 Vdc, ID = 25 Adc, Q1 – 6.0 –

SOURCE–DRAIN DIODE CHARACTERISTICS

(IS = 25 Adc, VGS = 0 Vdc, ta – 29 –

TEMPERATURE SENSE DIODE CHARACTERISTICS

TYPICAL ELECTRICAL CHARACTERISTICS

I D, DRAIN CURRENT (AMPS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN–TO–SOURCE RESISTANCE (mW)

Figure 5. On–Resistance Variation with Figure 6. Capacitance Variation

TYPICAL ELECTRICAL CHARACTERISTICS

IS, SOURCE CURRENT (A)

Figure 7. Capacitance Variation Figure 8. Diode Forward Voltage

VFTC, TEMPERATURE COEFFICIENT (mV/°C)

 Semiconductor Components Industries, LLC, 2001 27 Publication Order Number:

MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Static Drain–to–Source On–Resistance (Note 2.) RDS(on) mΩ

DYNAMIC CHARACTERISTICS (Note 3.)

SWITCHING CHARACTERISTICS (Note 3.)

(VDS = 6.0 Vdc, ID = 3.0 Adc, Q1 – 2.8 –

MIRROR MOSFET CHARACTERISTICS (TJ = 25°C unless otherwise noted)

MAXIMUM RATINGS (TC = 25°C unless otherwise noted) MARKING

 Semiconductor Components Industries, LLC, 2001 29 Publication Order Number:

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

SWITCHING CHARACTERISTICS (Note 3.)

ID, DRAIN CURRENT (AMPS)