08 Antonio Cerdeira

Training Courses on Compact Modeling
Tarragona, June 30-July 1, 2010
DC PARAMETER EXTRACTION
METHODS FOR MOSFETS
Antonio Cerdeira Altuzarra

Section of Solid State Electronics, CINVESTAV, México, D.F.
cerdeira@cinvestav.mx
OUTLINE
Circuit simulation
 MOSFET models in SPICE simulator
 Model Parameters
Individual extraction methods (DC)

Threshold voltage extraction methods:
 Constant current (CC)
 Extrapolation in linear region (ELR)
 Second derivative (SD)
 Extrapolation in saturation region (ESR)
Subthreshold slope
Effective channel length and series resistance:
 Hu method
Mathematical extraction methods (optimization).
Examples.
Training Courses on
Compact Modeling DC Parameter Extraction Methods 2
SIMULATION IN SEMICONDUCTOR DEVICE
DEVELOPMENT
In the process of development of new semiconductor devices,

different types of simulations are required:
• Semiconductor Process Simulation
Virtual fabrication of semiconductor devices.
• Semiconductor Device simulation.

Electrical behavior of semiconductor devices.
• Circuit simulation (SPICE type).

Behavior of an electrical circuit with different devices
interconnected.
All these simulations require models, and all models require
parameters
Training Courses on
CIRCUIT SIMULATION
The Spice-type circuit simulators calculates the current-voltage

characteristics of the devices to conform a circuit net, where
currents in each branch, and voltages at each node, are
determined.
The behavior of each semiconductor device is described by
equations that we know as device model.
Each model has a set of parameters that must be defined. Some
of them are technological, others are electrical and others are just
adjusting parameters.
Models used in circuit simulators must provide: accuracy in the
reproduction of I-V characteristics and low CPU time
consumption.
Training Courses on
MOSFET MODELS IN SPICE SIMULATOR
At the beginning, the main goal was to develop analytical models

to provide a simple description of the MOSFET, looking to
understand its behavior, rather than to provide a precise model
for circuit simulation.
As device dimensions reduced, MOSFET modeling shifted from
the physically based analytical description to a more complicated,
but precise representation that could provide efficient circuit
simulation.
The Spice-type MOSFET models can be grouped in:
 Threshold voltage models
 Compact models
 Analytical models.
Training Courses on
Threshold voltage models
The I-V characteristics are divided into several parts or regions,
with different sets of equations for each region: e.g. subthreshold;
above threshold; linear and saturation regions.
Examples of these first models are SPICE LEVEL 1, LEVEL 2,
LEVEL 3 and the first BSIM models. They have a problem of
discontinuity of functions or their derivatives at the point of transition
from one region to the other.
Compact models
Currents are obtained from only one equation that works in different
operation regions. They are based either the calculation of mobile
charge or surface potential. Examples are the BSIM4, PSP, HiSim,
EKV and SDDGM. Numerical calculation can be used.
Training Courses on
Analytical models
All magnitudes are described by analytical equations, so numerical
calculation is not needed.
Each transistor model has a set of parameters which must be
determined in order to use it.
There are three types of model parameters:
1. “Technological parameters” as transistor dimensions, thickness
of different layers, impurity concentrations;
2. “Electrical parameters” as threshold voltage and mobility;
3. “Adjusting parameters” used for fitting the model to the
experimental data.
Training Courses on
PARAMETERS OF THE MODELS
The process of determination of the value of model

parameters is known as “parameter extraction”.
There are two ways for obtaining these parameters:
“the individual method” – where parameters are
extracted one by one, both DC or RF methods can be
used;
“the optimization method” - where all the parameters
are determined at the same time.
Training Courses on
INDIVIDUAL PARAMETER EXTRACTION METHODS
Individual extraction method.

Useful when it is necessary to study one physical
parameter as function of technology or operating
conditions to characterize the device, as e.g. VT, or
mobility reduction, or effective channel length, Leff.
Drawbacks: sometimes complexity and time consuming.
In the following sections we will review several DC
methods of extractions of the following parameters for
MOS transistors: VT, S, Leff and series resistance, Rs.
Training Courses on
THRESHOLD VOLTAGE (VT) EXTRACTION
The threshold voltage extraction:

VT is a fundamental parameter for MOSFET modeling and
characterization, which represents the onset of significant
drain current flow. It has been given several definitions, but it
may be essentially understood as the gate voltage value at
which the transition between weak and strong inversion
takes place in the channel of the inversion-type MOSFET.
A review of MOSFET threshold voltage extraction methods
can be found in [*], some of which will be mentioned below.
* A. Ortiz-Conde, F.J.García-Sánchez, J.J. Liou, A. Cerdeira, M. Estrada, Y. Yue, “A

review of recent MOSFET threshold voltage extraction method” Microelectronics
Reliability, 42, pag. 583-596, 2002.
Training Courses on
VT extraction methods in MOSFETs biased in the linear region:

1) Constant Current (CC) method.
Defines VT as the gate voltage, VG, corresponding to a certain
predefined practical constant drain current ID;
2) Extrapolation of the Linear Region (ELR) method:
Determines the gate voltage axis intercept of the linear extrapolation
of the ID-VG characteristic at the maximum slope;
3) Transconductance Linear Extrapolation (GMLE) method:
Determines the gate voltage axis intercept of the linear extrapolation
of the gm-VG characteristic at the maximum slope.
Training Courses on
VT extraction methods in MOSFETs biased in the linear region

(cont):
4) Second Derivative (SD) method:
Determines VT as the gate voltage corresponding to the maximum
of the second derivative of the ID - VG characteristic;
5) Ratio method (RM):
Determines the gate voltage axis intercept of the ratio of the drain
current to the square root of the transconductance vs. VG;
6) Second Derivative Logarithmic (SDL) method:
Determines VT as the gate voltage corresponding to the minimum
of the second derivative of log(ID) – VG .
Training Courses on
VT extraction methods in MOSFETs biased in the saturation

region:
Extrapolation in the Saturation Region (ESR) method:
Determines the gate voltage axis intercept of the linear
extrapolation of the ID0.5-VG characteristics at maximum slope.
Training Courses on
VT - LINEAR REGION
Experimental data
Fully Depleted 0.6
(FD) SOI MOSFET L (µm) FD SOI
0.1 VD= 50 mV
0.5 0.12
W= 20 µm; 0.15
0.4 0.2
tox = 30 nm; ID (mA) 0.3
tSi = 80 nm; 0.5
0.3 1
tbox= 400 nm;
Poligate; 0.2
Na= 5x1017 cm-3.
0.1
Measured at
VD = 50 mV 0.0
0.0 0.5 1.0 1.5
VG (V)
Training Courses on
VT – CONSTANT CURRENT METHOD (CC)
0.6 Arbitrary constant drain
FD SOI L=100 nm
Lef= 78 nm current
0.5
VD= 50 mV IDarb=(W m / L m )0.1 [µA]
0.4
VTconst= -0.03 V
Wm and Lm are the mask
channel width and length,
ID (mA)
0.3 VTlin = 0.017 V

respectively.
experimental
0.2
linear regresion This method is widely
constant current =(W/L)10-7A used in industry because
0.1 VTconst of its simplicity for go/no-
go probers.
0.0
VTlin-nVD
Advantage: simplicity
0.0 0.5 1.0 1.5
Drawback: It is totally
VG (V) dependent on the
IDarb -green line arbitrarily chosen IDarb
VT-> intercept with the exp data
Training Courses on
VT – EXTRAPOLATION OF LINEAR REGION (ELR)
Most popular: find the
0.6 gate-voltage axis intercept
FD SOI L=100 nm
Lef= 78 nm (ID = 0) of the linear
0.5 extrapolation of the ID-VG
VD= 50 mV curve at the point of
0.4
VTconst= -0.03 V
maximum gm,.
ID (mA)
0.3 VTlin = 0.017 V Add Vd/2 to the resulting

gate-voltage axis intercept.
0.2 experimental
linear regresion Main drawback: maximum
constant current =(W/L)10-7A
0.1 VTconst
slope point might be
uncertain, because the ID-
0.0 VG can deviate from ideal
VTlin-nVD
straight line behavior at
0.0 0.5 1.0 1.5 gate voltages even slightly
VG (V) above VT , due to mobility
Extrapolation line– blue line degradation effects and to
VT=Vintercept+VD/2 Maximum slope at VG0 the presence of significant
source and drain series
Training Courses on parasitic resistances.
VT – EXTRAPOLATION OF LINEAR REGION (ELR)
0.6
R=0 R=65 Ω Effect of Rs on the
slope and
0.4 intercept point
values.
ID (mA)
Rs at source and
0.2
experimental
drain decrease the
lineal regretion: R=65 Ω slope in the linear
-0.009 R= 0 Ω
0.055
region changing
0.0
0.0 0.7 1.4
the intercept point
VG (V) to lower values,
and so affecting
the value of
Rs effect on the extrapolation line:
extracted VT.
VT=Vintercept+VD/2
Training Courses on
VT – SECOND DERIVATIVE METHOD (SD)
VT extracted from the maximum of the second derivative of ID - VG
6 Developed to avoid the
FD SOI L (µm) VT2D(V) dependence of VT by the
SECOND DERIVATIVE 0.1 0.024
5 series resistances,
0.12 0.054
0.15 0.096
4 0.2 0.135
VT is the voltage at the
0.3 0.17 maximum of the
3 0.5 0.2 transconductance
1 0.2
2 (dgm/dVG = d2ID/dVG2) .
1 The shift of VT with the

channel length is clearly
0 seen.
-1 This method is
-0.2 0.0 0.2 0.4 0.6 recommended for actual
VG (V) nanometric devices
(d2φS/dVG2 )
Training Courses on
VT EXTRACTION METHODS: COMPARISON
VT extracted from CC; ELR and SD as function of the L.

The roll-off effect is shown.
0.25
0.20
0.15
VT (V)
0.10
0.05 FD SOI VT ROLL-OFF
0.00 SECOND DERIVATIVE

CONSTANT CURRENT
EXTRAPOLATION LR
-0.05
0.0 0.2 0.4 0.6 0.8 1.0
Channel length (µm)
Training Courses on
I-V LINEAR REGION
Currents in the linear region for the FD SOI MOSFET can be

described by the following equations (VT model):
W
(VG − VT )VD − 1 + δ VD2
Drain current ID = Cox µ eff 2
L W  1  
1 + R Cox µ eff  (VG − VT ) −  + δ VD 
L  2  
Cbox C Si
δ - Equivalent body factor δ=
Cox (C Si + Cbox )
µ0
µ eff =
Effective mobility 1 + θg (VG − VT )
Training Courses on
I-V LINEAR REGION
The current expression for very low VD is equal to:
K (VG − VT )VD W
Drain current I Dlin = K= Cox µ 0
1 + [θg + RK ](VG − VT ) L
And the maximum W Cox µ 0

Pslope =
slope is equal to: L 1 + θg (1 + (VG 0 − VT ))
Extracting the maximum slope, VT; R and ∆L, the mobility degradation
factor θg and maximum mobility µ0 can be calculated as:
Pslope


θg = K
VD 
− R  −
1 µ0 =
W
(1 + θg (VG 0 − VT ))
 I measured (VG 0 )  VG 0 − VT Cox VD
L
Training Courses on
I-V LINEAR REGION
Drain current can be written in the following form:
 
 
µ  (V − V )V
= Cox 
W 0
I Dlin
L   W   G T D
1 + θg + R Cox µ 0  (VG − VT ) 
  L  
Mobility degradation and series resistance have the same

effect in the current and it is difficult to separate one effect
from the other.
It is important to remark that series resistance does not

affect mobility, it only affects the amplitude of the applied
voltage.
Training Courses on
VT EXTRACTION IN SATURATION
To extract the saturation threshold voltage VTsat the drain

current must be measured as a function of gate voltage with
the drain connected to the gate, to guarantee that the device
is operating in the saturation regime.
Normally the VTsat obtained in saturation is less that the VT
obtained in the linear region.
(VG − VT )2
W 2(1 + δ )
I D sat =
L
Cox µ eff
W   (V − VT )  I Dsat ∝ (VG − VT )
1 + R Cox µ eff   G 
L   2(1 + δ ) 
Training Courses on
EXAMPLE OF VT EXTRACTION IN SATURATION
0.12
FinFET
0.10 L= 50 nm 0.008 FinFET
VD= 1 V L= 10µm
VD= 1 V
0.08
0.006
0.5
0.06
( ID )0.5
( ID )
0.004
0.04
VT= -0.41 V
0.02 VTSD= -0.22 V 0.002 VT= -0.08 V VTSD= -0.05 V
0.00
0.000
-0.5 0.0 0.5 1.0 1.5
0.0 0.5 1.0 1.5
VG (V)
VG (V)
Intercept of the IDsat0.5-VG characteristics linearly extrapolated

at its maximum first derivative (slope) point.
Training Courses on
EXTRACTION OF SUBTHRESHOLD SLOPE S
Subthreshold slope
Ion
definition
0
10
10-2 V2 − V1 ∆V
S ∆V S= =
FD SOI
log( I 2 ) − log( I1 ) 1 decade
ID (mA)
VD= 50 mV
10-4
L (µm)
0.1
10-6 0.12
0.15
L (nm) S (mV/dec)
0.2 100 220
10-8 0.3
0.5 300 62
Ioff 1
10-10
-0.5 0.0 0.5 1.0
VG (V) The effect of leakage
gate current is important
in subthreshold
Training Courses on
EFFECTIVE CHANNEL LENGTH AND
SERIES RESISTANCE EXTRACTION METHODS
We define different channel length:

In the mask; in the gate; metallurgical and effective.
From the external node of voltages to the internal point at the

beginning of the channel there is a resistance that we define
as series resistance.
These both parameters can be voltage depended too.
Training Courses on
EFFECTIVE CHANNEL LENGTH (Leff)
There are different definitions
of channel length.
Lmask - Mask length
Lgate - Gate length. It is the

physical dimension of the
gate and is a process
monitoring parameter.
Lmet - Metallurgical channel

length. Distance between the
two P-N junctions of the
source and drain diffusions at
the silicon surface. Can be
extracted only with 2D TCAD
programs.
Training Courses on
Leff - Effective channel length.
It is defined through electrical

characteristics of the MOSFET
and is not strictly a physical
parameter. It is a key parameter
in CMOS technology used for
transistor models, short-channel
design and process monitoring. A
simple model is necessary.
The physical interpretation of Leff

is an open question.
Training Courses on
Simulated SOI FD MOSFET Lm= 1 um (NO-LDD and LDD)
Training Courses on
With the introduction of the HALO

diffusion in submicrometric
Gate
technology and retrograded
junctions, the definition of Leff is
Source Drain
less and less associated with
some real physical dimension.
Body/Halo Doping
Another important effect to take into consideration is the dispersion

of the gate channel length obtained in the technological process. In
this case Leff can change from one transistor to another in the
same chip.
Training Courses on
SERIES RESISTANCES (R) IN MOSFETS
Rs or Rd = contact resistance + n+ path + n- path. R=Rs+Rd
Rs is a real physical parameter. The introduction of the LDD process
increases RS and increases the gate dependence of this parameter.
Training Courses on
Leff and R EXTRACTION METHODS
The extraction of effective channel length Leff and the

series resistance R are normally made with the same
procedure.
From the 70th different method were proposed. Some

DC and another RF methods.
Nowadays the most used DC methods are the method

of Hu and Shift and Ratio Method.
Considering the complexity of the S&R method, we will

describe the Hu Method.
Training Courses on
HU METHOD
For SOI FD MOSFET in the linear region ID can be expressed as:
ID =
[
K 0 VGTVD − nVD2 ] VGT = VG − VT
1 + θGVGT + θ DVD
where:
K0 =
W
µ 0C01 Leff = Lm − ∆L δ=
C02 C S 1+ δ
Leff C01 (C S + C02 ) n=
2
Lm channel length in mask;

∆L channel length reduction;
θG, θD gate and drain bias mobility degradation factors, respectively;
C01,C02, Cs thin oxide, thick oxide and semiconductor capacitances
respectively.
Training Courses on
HU METHOD
In the linear region (triode region), the total resistance Rtot is equal to:
VD Lm − ∆L 1 + θ GVGT + θ DVD
Rtot = RS + Rchannel = =
ID Ko VGT − nVD
After some rearrangements:
1 + θ G VGT + θ D VD  2VGT − 3nVD

Rtot (VGT , Lm ) =  ⋅
 m ( L − ∆L (V ) ) + R (V )
 K o (VGT − nVD )  (VGT − nVD )
G S G
Rtot(Lm) is a linear function of Lm for constant VGS. and VDS.
Plotting Rtot vs. Lm will show an interception point that provides

information about Rs and Leff.
Training Courses on
HU METHOD
HU METHOD
Plotting Rtot vs. Lm at different VG will show an interception point

that provides information about Rs and Leff.
Rtot is calculated for two close VGT values (V1 and V2), for which
RS an Leff remain constant:
R(V1)=R(V2)=Ro and ∆L(V1)=∆L(V2)= ∆Lo ,
V1= VGT1+∆V/2 , V2= VGT2-∆V/2 and VGT=(V1+V2)/2
From previous equation:

nVD K o Ro (VGT )
Lmo (VGT ) = ∆Lo (VG ) + ≈ ∆Lo (VGT )
1 + (θ D + nθ G )VD
Ro (VGT ) = Rsource + Rdrain = R( Lmo , VGT )
Training Courses on
HU METHOD
Measured Data SOI FD LDD
14
12 Vgs=(V1+V2)/2 = 1.7 V
V1 = 1.8 V
10 V2 = 1.6 V
8
Rt (kΩ)
0 5 10 15 20
Lm (µm)
Training Courses on
HU METHOD
Measured Data SOI FD LDD near the intercept point

0.3
Vgs=(V1+V2)/2 = 1.7 V
V1 = 1.8 V
V2 = 1.6 V
0.2
Rt (kΩ)
0.1
Lmo= 0.19 µm
Rso= 153 Ω
0.0
0.0 0.1 0.2 0.3 0.4
Lm (µm)
Training Courses on
HU METHOD
Extracted Rs(VGS) V1-V2= 0.2 , 0.1 V Extracted ∆L(VGS)

1000
DATA FROM MARCELO 0.7
900
sin LDD 0.1 DATA FROM MARCELO
800 sin LDD 0.2 0.6
con LDD 0.1 sin LDD 0.1
700 con LDD 0.2 sin LDD 0.2
con LDD 0.1
600 0.5 con LDD 0.2
∆L [µm]
Rs [Ω]
500
0.4
400
300 0.3
200
100 0.2
0 0.5 1.0 1.5 2.0

0.5 1.0 1.5 2.0 Vgs [V]
Vgs [V]
Voltage dependence of R s and ∆L

Training Courses on
HU METHOD
Adjust to a fixed function:
0.55
500
0.50
∆L
Rs F1
400 F-1 0.45
F2
F-2
0.40
∆L [µm]
Rs [Ω]
300
0.35
200 0.30
0.25
100
0.20
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Vgs [V] Vgs [V]
F1 -> Shu,Hu,Ko,Hsu, 1984 F2 -> Reydezel, Murphy, 2002

1
Rs = 27.76 +
0.0116(VGS − 0.519)
Rs = 98.75 + 1414.45 e −4.39(VGS −0.413)
∆L = 0.122 +
1 ∆L = 0.215 + 0.58 e 2.43(VGS −0.413)
5.82(VGS − 0.253)
Training Courses on
PROBLEMS WITH THE TOTAL RESISTANCE
EXTRACTION METHODS
For some devices Rtotal can no longer be considered to vary linearly
with Lm. For FinFETs with channel length down to 40 nm non-linearity
can be significant .
8000 200
Vg= 1V Vg= 1V
Vg= 1.2 V Vg= 1.2 V
6000 Vg= 1.5 V Vg= 1.5 V
Total resistance (Ω)
Total resistance (Ω)

150
4000
100
2000
50
0
-1 0 1 2 3 4 5 6 7
0.00 0.05 0.10 0.15
Channel length (µm) Channel length (µm)
Training Courses on
EFFECT OF THE GATE CURRENT
In large channel transistors with very thin gate dielectric, including

stacks, gate tunneling current can be very large and the values of drain
and source currents are affected.
6.0
IG
FinFET with EOT= 2 nm 5.5
ID L= 10 um
5.0 IS Vds= 0.05 V
4.5 IG/2
In this case, it is ID+IG/2
4.0 IS-IG/2
important to measure IG
current [uA]
3.5
3.0
current in order to be 2.5
sure that the current 2.0
region used for 1.5
1.0
parameter extraction is 0.5
not affected by the gate 0.0
current. -0.5
-1.0 -0.5 0.0 0.5 1.0 1.5
Vgs
Training Courses on
INDIVIDUAL PARAMETER EXTRACTION METHODS
Individual extraction methods are not the best solution in the

following cases:
1. The model has too many parameters. (Some models have more
than hundred parameters).
2. The equations of the model do not have a direct dependence on
external voltages. They can depend on charges or electric fields, in
which cases it is not possible to obtain explicit equations.
3. The volume of data is too big, you need a very precise device
description or you are dealing with different types of transistors in
the circuit.
In these cases the parameter extraction must be done using a

mathematical algorithm, known as optimization.
Training Courses on
PARAMETER EXTRACTION : THE OPTIMIZATION METHOD
When you have a current-voltage data for one

transistor, you can use the well-known mathematical
method, optimization or minimization, in order to extract
the model parameter.
Levenberg-Marquardt algorithm is the best for this
purpose.
Training Courses on
OPTIMIZATION METHOD: DESCRIPTION
Levenberg-Marquard algorithm is implemented in the following way:
Current-voltage equation (model). I ( X ,V )
X = ( x1 , x2 ,..., x N )
Vector of N variables (parameters) X
M measured points, pairs of current i

I meas = f (Vi )
and voltage
2
M  I ( X , Vi ) − I meas
i

An objective function F(Vi,X) is F ( X ) = ∑  i


i =1  I meas 
defined. It must be normalized.
Training Courses on
OPTIMIZATION METHOD: DESCRIPTION
Like other numerical minimization algorithms, this is an

iterative procedure. An initial guess for the parameter vector
X is required .
In each step of iteration, the parameter vector Xk is replaced
by a new one Xk+1.
X k +1 k
[
= X − λk ⋅( J ⋅ J k ) ii +
T
J kT ⋅ Jk ]
−1
J kT ⋅ I ( X k , Vi )
The iterations stop when the difference is less than ε;

k +1
)<ε
k
F(X ) − F(X
Constrains are introduced to define the specified range for the

variation of parameters.
Training Courses on
EXAMPLE
A way to solve the parameter extraction is the solution of a

system of equations, using an algorithm of optimization
(minimization) in the following steps:
• Model definition
• Definition of N current-voltage equations at N measured
points.
• M –number of unknown parameters, N ≥ M.
Iterative solution steps stops when the measured
characteristics can be described using a parameter vector X
with a fixed error.
The solutions of this system of equations by the optimization
method can be done using any of the known mathematical
packages like Mathcad, Mathlab or Mathematica.
Training Courses on
EXAMPLE
In the SDDGM model (*) for double-gate transistors (FinFETs)
drain current is equal to:
  q s2 − q d2  q + qb  
2
 kT
+ 2(q s − q d ) − qb ln s
W
2 Cox µ 0    
L  q  2  qd + qb 
I D mod =
  E  P1  E  P 2   
1 +  m  +  m   + 2 Cox µ 0 R VG − VT −  + δ VD 
W 1
  E1  E  
  2  L  2  
qs (VG,VD) and qd (VG,VD) are the normalized mobile

charges at source and drain.
Em (VG,VD) is the medium electric field between S and D
Known parameters: VT , W, L, kT, µ0, δ, Cox

Unknown parameters: X(E1, E2, P1, P2, R)
* A. Cerdeira, B. Iñiguez and M. Estrada, “Compact model for short channel symmetric
doped double-gate MOSFETs”, Solid-State Electronics, 52 (2008) 1064-1070.
Training Courses on
EXAMPLE
For transfer characteristic in the linear region at fixed VD

currents are extracted at n gate voltage points:
IDexp (VGi) where i =1,2..n
A system of n equations is obtained:
I D exp (VGi , VD , X )
=1
I D mod (VGi , VD , X )
Training Courses on
EXAMPLE
The following FinFET transistor will be modeled:
EOT= 1.6 nm; 1.4

WFIN= 30 nm; 1.2 FinFET
L= 120 nm
Selected
HFIN = 60 nm; 1.0 W= 67.5 µm points:
W= 67.5 µm; VD= 20 mV 1. 0.4 V
ID (mA)
0.8
0.6
2. 0.6 V
VD= 20 mV; 3. 0.8 V
0.4
T= 25 ºC 4. 1.2 V
0.2
Metal gate with 5. 1.5 V
0.0
work function of 4.6 V 0.0 0.5 1.0 1.5
µ0= 1300 cm2/Vs VG (V)
VT=0.3 V
Training Courses on
EXAMPLE
Guess parameters Extracted parameters
E1= 104 V/cm 12 V/cm
E2= 2x106 V/cm 8.34x104 V/cm
P1= 0.33 0.2
P2= 1.5 1.13
R= 10 Ω 0 Ω
10
measured 1
1.2
modeled 0.1
VD= 20 mV 0.01
0.8 T= 25 ºC 1E-3
ID (mA)
ID (mA)
1E-4 measured
1E-5 modeled
0.4 1E-6 VD= 20 mV
1E-7 T= 25 ºC
1E-8
0.0
1E-9
-0.5 0.0 0.5 1.0 1.5 -0.5 0.0 0.5 1.0 1.5
VG (V) VG (V)
Training Courses on
OPTIMIZATION METHOD: ADVANTAGES
1. The extraction is made for all the parameters at the same

time.
2. When the program is well written, the method is fast and
easy to use.
3. The data and the resulting parameters can describe the I-
V in different regions, where different models work.
Training Courses on
OPTIMIZATION METHOD: ADVANTAGES
4. The input data can include measurements of one transistor,

or measurements of different transistors of the same type,
or accumulated measurements in a week, etc. That is, the
extracted parameters can be the result of considering
statistical data for one type of transistor.
5. These are the mean value parameters that the foundry
gives to the user in order to simulate the integrated circuits
with SPICE MODELS.
6. This method is the best for the extraction of those
parameters that are not depending directly on external
applied voltages. It gives the best fitting.
Training Courses on
OPTIMIZATION METHOD: DRAWBACKS
1. Extracted values of parameters are fitting values

which may not have physical meaning.
2. These parameters cannot be used in order to

analyze physical magnitudes as threshold voltage
or mobility.
Training Courses on
CONCLUSIONS
1. Parameter extraction is a necessary step in the

process of device modeling.
2. Extraction methods can be done using DC or RF
measurements.
3. Two types of DC method can be used: individual and
optimization.
4. Individual extraction of VT, S, R and ∆L were
presented.
5. For VT the best method for the actual nanometric
transistors is the Second Derivative Method.
Training Courses on
CONCLUSIONS
6. Extraction of R and ∆L is a complex process,

specially for short channel devices. In some cases
Hu method gives a good result. Another good
approach is by simulation.
7. The extraction by mathematical optimization
(minimization) is the best method for the new
MOSFETs when models have many parameters and
parameters have a complex dependence on fields
and voltages.
Training Courses on
Thanks for your attention
Training Courses on
I-V LINEAR REGION
Comparison with the experimental VD = 50 mV

0.6
Parameters extracted: FD SOI
VT= 0.024 V 0.5 W= 20 µm
R= 65 Ω L= 100 nm
∆L= 22 nm 0.4
ID (mA)
0.3
µo= 1400 cm2/Vs 0.2

θg= 0.09 1/V
0.1
experimental
modeled
0.0
0.0 0.5 1.0 1.5

VG (V)
Training Courses on

08 Antonio Cerdeira

Caricato da

Informazioni sul documento

Descrizione originale:

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

08 Antonio Cerdeira

Caricato da

Copyright:

Formati disponibili

Training Courses on Compact Modeling

Tarragona, June 30-July 1, 2010

Antonio Cerdeira Altuzarra

Individual extraction methods (DC)

Mathematical extraction methods (optimization).

In the process of development of new semiconductor devices,

• Semiconductor Device simulation.

• Circuit simulation (SPICE type).

The Spice-type circuit simulators calculates the current-voltage

At the beginning, the main goal was to develop analytical models

The process of determination of the value of model

Individual extraction method.

The threshold voltage extraction:

* A. Ortiz-Conde, F.J.García-Sánchez, J.J. Liou, A. Cerdeira, M. Estrada, Y. Yue, “A

VT extraction methods in MOSFETs biased in the linear region:

VT extraction methods in MOSFETs biased in the linear region

VT extraction methods in MOSFETs biased in the saturation

0.3 VTlin = 0.017 V

0.3 VTlin = 0.017 V Add Vd/2 to the resulting

1 The shift of VT with the

VT extracted from CC; ELR and SD as function of the L.

0.05 FD SOI VT ROLL-OFF

0.00 SECOND DERIVATIVE

Currents in the linear region for the FD SOI MOSFET can be

And the maximum W Cox µ 0

Drain current can be written in the following form:

Mobility degradation and series resistance have the same

It is important to remark that series resistance does not

To extract the saturation threshold voltage VTsat the drain

Intercept of the IDsat0.5-VG characteristics linearly extrapolated

We define different channel length:

From the external node of voltages to the internal point at the

These both parameters can be voltage depended too.

Lgate - Gate length. It is the

Lmet - Metallurgical channel

Leff - Effective channel length.

It is defined through electrical

The physical interpretation of Leff

With the introduction of the HALO

Another important effect to take into consideration is the dispersion

The extraction of effective channel length Leff and the

From the 70th different method were proposed. Some

Nowadays the most used DC methods are the method

Considering the complexity of the S&R method, we will

For SOI FD MOSFET in the linear region ID can be expressed as:

Lm channel length in mask;

After some rearrangements:

1 + θ G VGT + θ D VD  2VGT − 3nVD

Rtot(Lm) is a linear function of Lm for constant VGS. and VDS.

Plotting Rtot vs. Lm will show an interception point that provides

Plotting Rtot vs. Lm at different VG will show an interception point

From previous equation:

Measured Data SOI FD LDD near the intercept point

Extracted Rs(VGS) V1-V2= 0.2 , 0.1 V Extracted ∆L(VGS)

0 0.5 1.0 1.5 2.0

Voltage dependence of R s and ∆L

F1 -> Shu,Hu,Ko,Hsu, 1984 F2 -> Reydezel, Murphy, 2002

Total resistance (Ω)

In large channel transistors with very thin gate dielectric, including

Individual extraction methods are not the best solution in the

In these cases the parameter extraction must be done using a

When you have a current-voltage data for one

Levenberg-Marquard algorithm is implemented in the following way: