Chapter 1

Introduction
1.1 Integrated circuit:-

In electronics, an integrated circuit is a miniaturized electronic circuit (consisting

mainly of semiconductor devices, as well as passive components) that has been manufactured
in the surface of a thin substrate of semiconductor material. Integrated circuits are used in
almost all electronic equipment in use today and have revolutionized the world of electronics.
A hybrid integrated circuit is a miniaturized electronic circuit constructed of individual
semiconductor devices, as well as passive components, bonded to a substrate or circuit board.

Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes, and by mid-20th-
century technology advancements in semiconductor device fabrication. The integration of
large numbers of tiny transistors into a small chip was an enormous improvement over the
manual assembly of circuits using electronic components. The integrated circuit's mass
production capability, reliability, and building-block approach to circuit design ensured the
rapid adoption of standardized ICs in place of designs using discrete transistors.

There are two main advantages of ICs over discrete circuits: cost and performance.
Cost is low because the chips, with all their components, are printed as a unit by
photolithography and not constructed as one transistor at a time. Furthermore, much less
material is used to construct a circuit as a packaged IC die than as a discrete circuit.
Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and close
together.

1.2 HISTORY OF INTEGRATED CIRCUIT:-

The idea of integrated circuit was conceived by a radar scientist working for the Royal
Radar Establishment of the British Ministry of Defense, Geoffrey W.A. Dummer (1909-
2002), who published it at the Symposium on Progress in Quality Electronic Components in
Washington, D.C. on May 7, 1952. He gave many symposia publicly to propagate his ideas.

Early developments of the integrated circuit go back to 1949, when the German
engineer Werner Jacobi (Siemens AG) filed a patent for an integrated-circuit-like
semiconductor amplifying device showing five transistors on a common substrate arranged in
a 2-stage amplifier arrangement. The evolution of integrated circuit (IC) fabrication
techniques is a unique fact in the history of modern industry.
1.3 Generations of integrated circuit technologies:

We consider four main generations of integrated circuit technologies: micron, submicron,

deep submicron and ultra deep submicron technologies.

Figure 1.1: Evolution of lithography

The sub-micron era started in 1990 with the 0.8μm technology. The deep sub-micron
technology started in 1995 with the introduction of lithography better than 0.3μm. Ultra deep
submicron technology concerns lithography below 0.1μm.
In figure 1.1 it can be seen that the trend towards smaller dimensions has been
accelerated since 1996. In 2007, the lithography has decreased down to 0.07μm. The
lithography expressed in μm corresponds to the smallest patterns that can be implemented on
the surface of the integrated circuit.
The 1.2μm CMOS process features n-channel and p-channel MOS devices with a minimum
channel length of 0.8μm.
The two dimensional aspect of this technology is shown in figure no 1.2:-.

Figure1.2: Cross-section of the 1.2μm CMOS technology

The 0.35μm CMOS technology is a five-metal layer process with a minimal MOS device
length of 0.35μm. The MOS device includes lateral drain diffusions, with shallow trench
oxide isolations.

Figure1.3: Cross-section of the 0.35μm CMOS technology

The Microwind tools are configured by default in a CMOS 0.12μm six-metal layer
process with a minimal MOS device length of 0.12μm. The metal interconnects are very
narrow, around 0.2μm, separated by 0.2μm. The MOS device appears very small, below the
stacked layers of metal sandwiched between oxides.
 Figure1.4: 2D View of the 0.12μm process

The main consequence of improved lithography is the ability to implement an

identical function in an ever smaller silicon area. Consequently, more functions can be
integrated in the same space. Moreover, the number of metal layers used for interconnects has
been continuously increasing in the course of the past ten years. More layers for routing
means a more efficient use of the silicon surface, as for printed circuit boards. Active areas,
i.e MOS devices can be placed closer to each other if many routing layers are provided. The
increased density provides two significant improvements: the reduction of the silicon area
goes together with a decrease of parasitic capacitance of junctions and interconnects, thus
increasing the switching speed of cells. Secondly, the shorter dimensions of the device itself
speed up the switching, which leads to further operating clock improvements. The wafer
diameter for 0.12μm technology is 8 inches or 20cm. The introduction of high level
description languages such as VHDL and Verilog [Verilog] have made possible the design of
complete systems on a chip ,with complexities ranging from 1 million to 10 million
transistors.

1.4 Levels of Integration:-

1.4.1 SSI, MSI and LSI:-

The first integrated circuits contained only a few transistors called "Small-Scale
Integration" (SSI), digital circuits containing transistors numbering in the tens provided a
few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips
TAA320 had as few as two transistors. The term Large Scale Integration was first used by
IBM scientist Rolf Landauer when describing the theoretical concept, from there came the
terms for SSI, MSI, VLSI, and ULSI.SSI circuits were crucial to early aerospace projects,
and vice-versa. Both the Minuteman missile and Apollo program needed lightweight digital
computers for their inertial guidance systems; the Apollo guidance computer led and
motivated the integrated-circuit technology, while the Minuteman missile forced it into mass-
production.

The next step in the development of integrated circuits, taken in the late 1960s,
introduced devices which contained hundreds of transistors on each chip, called "Medium-
Scale Integration" (MSI).They were attractive economically because while they cost little
more to produce than SSI devices, they allowed more complex systems to be produced using
smaller circuit boards, less assembly work (because of fewer separate components), and a
number of other advantages.

Further development, driven by the same economic factors, led to "Large-Scale

Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip.
Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that
began to be manufactured in moderate quantities in the early 1970s, had under 4000
transistors. True LSI circuits, approaching 10000 transistors, began to be produced around
1974, for computer main memories and second-generation microprocessors.

1.4.2 VLSI:-

The final step in the development process, starting in the 1980s and continuing
through the present, was "very large-scale integration" (VLSI). The development started with
hundreds of thousands of transistors in the early 1980s, and continues beyond several billion
transistors as of 2009.

There was no single breakthrough that allowed this increase in complexity, though
many factors helped. Manufacturers moved to smaller rules and cleaner fabrications, so that
they could make chips with more transistors and maintain adequate yield. The path of process
improvements was summarized by the International Technology Roadmap for
Semiconductors (ITRS). Design tools improved enough to make it practical to finish these
designs in a reasonable time. The more energy efficient CMOS replaced NMOS and PMOS,
avoiding a prohibitive increase in power consumption.

In 1986 the first one megabit RAM chips were introduced, which contained more than
one million transistors. Microprocessor chips passed the million transistor mark in 1989 and
the billion transistor mark in 2005. The trend continues largely unabated, with chips
introduced in 2007 containing tens of billions of memory transistors.
1.4.3 ULSI, WSI, SOC and 3D-IC:-

To reflect further growth of the complexity, the term ULSI that stands for "ultra-
large-scale integration" was proposed for chips of complexity of more than 1 million
transistors.

Wafer-scale integration (WSI) is a system of building very-large integrated circuits

that uses an entire silicon wafer to produce a single "super-chip". Through a combination of
large size and reduced packaging, WSI could lead to dramatically reduced costs for some
systems, notably massively parallel supercomputers. The name is taken from the term Very-
Large-Scale Integration, the current state of the art when WSI was being developed.

A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components

needed for a computer or other systems are included on a single chip. The design of such a
device can be complex and costly, and building disparate components on a single piece of
silicon may compromise the efficiency of some elements. However, these drawbacks are
offset by lower manufacturing and assembly costs and by a greatly reduced power budget:
because signals among the components are kept on-die, much less power is required.

A three-dimensional integrated circuit (3D-IC) has two or more layers of active

electronic components that are integrated both vertically and horizontally into a single circuit.
Communication between layers uses on-die signaling, so power consumption is much lower
than in equivalent separate circuits. Judicious use of short vertical wires can substantially
reduce overall wire length for faster operation.

1.5 ADVANCES IN INTEGRATED CIRCUIT:-

The integrated circuit from an Intel 8742, an 8-bit microcontroller that includes a CPU
running at 12 MHz, 128 bytes of RAM, 2048 bytes of EPROM, and I/O in the same chip.

Among the most advanced integrated circuits are the microprocessors or "cores",
which control everything from computers to cellular phones to digital microwave ovens.
Digital memory chips and ASICs are examples of other families of integrated circuits that are
important to the modern information society. While the cost of designing and developing a
complex integrated circuit is quite high, when spread across typically millions of production
units the individual IC cost is minimized. The performance of ICs is high because the small
size allows short traces which in turn allows low power logic (such as CMOS) to be used at
fast switching speeds.

ICs have consistently migrated to smaller feature sizes over the years, allowing more
circuitry to be packed on each chip. This increased capacity per unit area can be used to
decrease cost and/or increase functionality—for instance Moore's law which, in its modern
interpretation, states that the number of transistors in an integrated circuit doubles every two
years. In general, as the feature size shrinks, almost everything improves—the cost per unit
and the switching power consumption go down, and the speed goes up. However, ICs with
nanometer-scale devices are not without their problems, principal among which is leakage
current although these problems are not insurmountable and will likely be solved or at least
ameliorated by the introduction of high-k dielectrics. Since these speed and power
consumption gains are apparent to the end user, there is fierce competition among the
manufacturers to use finer geometries.

1.6 POPULARITY OF INTEGRATED CIRCUIT:-

Only a half century after their development was initiated, integrated circuits have
become ubiquitous. Computers, cellular phones, and other digital appliances are now
inextricable parts of the structure of modern societies. That is, modern computing,
communications, manufacturing and transport systems, including the Internet, all depend on
the existence of integrated circuits.

1.7 CLASSIFICATION:-

Integrated circuits can be classified into analog, digital and mixed signal (both analog
and digital on the same chip).

Digital integrated circuits can contain anything from one to millions of logic gates,
flip-flops, multiplexers, and other circuits in a few square millimeters. The small size of these
circuits allows high speed, low power dissipation, and reduced manufacturing cost compared
with board-level integration. These digital ICs, typically microprocessors, DSPs, and micro
controllers work using binary mathematics to process "one" and "zero" signals.

Analog ICs, such as sensors, power management circuits, and operational amplifiers,
work by processing continuous signals. They perform functions like amplification, active
filtering, demodulation, mixing, etc. Analog ICs ease the burden on circuit designers by
having expertly designed analog circuits available instead of designing a difficult analog
circuit from scratch.

ICs can also combine analog and digital circuits on a single chip to create functions
such as A/D converters and D/A converters. Such circuits offer smaller size and lower cost,
but must carefully account for signal interference.
 Chapter 2
Logic gates

2.1 Adder:-

2.1.1 Half adder:-

A half adder is a logical circuit that performs an addition operation on two one-bit
binary numbers often written as A and B. The half adder output is a sum of the two inputs
usually represented with the signals Cout and S (where sum=2 x Cout+S). Following is the logic
table for a half adder:

INPUTS OUTPUTS
A B C S

0 0 0 0

0 1 0 0

1 0 0 1

1 1 1 0

Table2.1: logic table for a half adder

2.1.2 Full adder:-

Figure 2.1: full adder

A full adder is a logical circuit that performs an addition operation on three one-bit
binary numbers often written as A, B, and Cin. The full adder produces a two-bit output sum
typically represented with the signals Cout and S (where sum=2 x Cout+S).
The full adder's truth table is:-

INPUTS OUTPUTS
A B Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Table 2.2: logic table for a full adder

2.1.3 Parallel Adder:-

A full adder is capable of adding two 1–bit binary numbers and a carry–in. To add
two n-bit numbers together, n full-adders should be cascaded. Each full-adder represents a
column in the long addition. The carry signals ‘ripple’ through the adder from right to left.
The carry out of each full-adder is connected to the carry in of the next higher order adder. A
parallel adder is used to add two numbers in parallel form and to produce the sum bits as
parallel outputs.

Figure 2.2: 4 Bit parallel adder

2.2 Subtractor:-

2.2.1 Half- subtractor:

The half-subtractor is a combinational circuit which is used to perform subtraction of

two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference)
and B (borrow).

Figure 2.3: Logic diagram for a half subtractor

The truth table for the half subtractor is given below.

X Y D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Table 2.3: logic table for a half subtractor

2.2.2 Full subtractor:

The Full subtractor is a combinational circuit which is used to perform subtraction of
three bits. It has two inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two
outputs D (difference) and B (borrow).
The truth table for the full subtractor is given below:-

X Y Z D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Table 2.4: logic table for a full subtractor

Logic equations are:

2.3 XOR gate:-

The XOR gate is a digital logic gate that implements exclusive disjunction - it
behaves according to the truth table below. A HIGH output (1) results if one, and only one, of
the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW
output (0) results. XOR gate is short for exclusive OR.

The truth table of a XOR gate is as shown:-

 INPUT

A B OUTPUT

0 0 0

0 1 1

1 0 1

1 1 0

Table 2.5: Logic table for XOR gate

The XOR gate symbol is as shown:

Figure 2.4: Logic diagram for XOR gate

2.4 Multiplexer and Demultiplexer:-

A multiplexer is a device that performs multiplexing; it selects one of many input signals and
forwards the selected input into a single line. Multiplexer makes it possible for several signals to
share one device or resource, for example one A/D converter or one communication line,
instead of having one device per input signal. Multiplexers of common sizes are 4-to-1, 8-to-
1, and 16-to-1.

Figure 2.5: different multiplexers

A 4-to-1 multiplexer can be realized using a decoder, AND gates, and an OR gate as follow:-
 Figure 2.6: 4 to 1 multiplexer

A demultiplexer (or demux) is a device taking a single input signal and selecting one
of many data-output-lines, which is connected to the single input. A multiplexer is often used
with a complementary demultiplexer on the receiving end. It has only one input, n selectors
and 2n outputs. Depending on the combination of the select lines one of the outputs will be
selected to take the state of the input.

Figure 2.7: 1 to 4 demultiplexer

2.4 Flip-flop:-
 A flip-flop is a term referring to an electronic circuit that has two stable states and
thereby is capable of serving as one bit of memory. A flip-flop is usually controlled by one or
two control signals and/or a gate or clock signal. The output often includes the complement
as well as the normal output.

2.4.1 SR (Reset-Set) flip-flop:-

The fundamental latch is the simple RS flip-flop (also commonly known as SR flip-
flop), where R and S stand for reset and set, respectively. It can be constructed from a pair of
cross-coupled NAND or NOR logic gates. Normally, in storage mode, the R and S inputs are
both low, and feedback maintains the Q and complement Q outputs in a constant state. If S is
pulsed high while R is held low, then the Q output is forced high, and stays high even after S
returns low; similarly, if R is pulsed high while S is held low, then the Q output is forced low,
and stays low even after R returns low.

The next-state equation of the RS flip-flop is

Qnext = S + RQ

Where Q is the current state .Qnext becomes Q (the stored value) at clock edge.

An RS latch constructed from a pair of cross-coupled NOR gates is as shown :-

Figure 2.8: Gated SR Flip-Flop

The truth table is as shown below:-

 SR FLIP-FLOP(BUILT WITH NOR GATES)

CHARACTERISTIC TABLE EXCITATION TABLE

S R ACTION Q(t) Q(T+1) S R ACTION

0 0 KEEP 0 0 0 X NO
STATE CHANGE
0 1 Q=0 1 0 0 1 RESET

1 0 Q=1 0 1 1 0 SET

1 1 RACE 1 1 X 0 NO
CONDITION CHANGE

Table 2.6: Logic table for RS flip- flop

2.4.2 D (Delay) flip-flop:-

The D flip-flop is the most common flip-flop in use today. It is better known as delay
flip-flop. The Q output always takes on the state of the D input at the moment of a positive
edge (or negative edge if the clock input is active low). It is called the D flip-flop for this
reason, since the output takes the value of the D input or Data input, and Delays it by
maximum one clock count.

The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or

delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.

The symbol is:-

Figure 2.9: Logic symbol for D flip-flop

The truth table is as shown below:-

 CLOCK D Q QPREV

RISING 0 0 X
EDGE
RISING 1 1 X
EDGE
NON- X QPREV
RISING

Table 2.7: Logic table for D flip-flop

2.5 Ring counter:-

A ring counter is a type of counter composed of a circular shift register. The output of
the last shift register is fed to the input of the first register.There are two types of ring
counters:

a>A straight ring counter connects the output of the last shift register to the first shift register
input and circulates a single one (or zero) bit around the ring. For example, in a 4-register
one-hot counter, with initial register values of 1000, the repeating pattern is: 1000, 0100,
0010, 0001, 1000... .

b>A twisted ring counter or Johnson counter connects the complement of the output of the
last shift register to its input and circulates a stream of ones followed by zeros around the
ring. For example, in a 4-register counter, with initial register values of 0000, the repeating
pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000... . Four-bit ring counter
sequences of the different ring counters are as shown:-

STRAIGHT RING/OVERBECK COUNTER TWISTED RING/JOHNSON COUNTER

STATE Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
0 1 0 0 0 0 0 0 0 0
1 0 1 0 0 1 1 0 0 0
2 0 0 1 0 2 1 1 0 0
3 0 0 0 1 3 1 1 1 0
0 1 0 0 0 4 1 1 1 1
1 0 1 0 0 5 0 1 1 1
2 0 0 1 0 6 0 0 1 1
3 0 0 0 1 7 0 0 0 1
0 1 0 0 0 0 0 0 0 0

Table 2.8: Logic table for Four-bit ring counter sequences

2.6 Asynchronous Counter:-

 A digital counter is a set of flip-flops whose states change in response to pulses
applied at the input to the counter. Counters may be synchronous or asynchronous counters.

Asynchronous counters are also called ripple counters. The ripple counter is the
simplest type of counter, the easiest to design and requires the least amount of hardware. The
FFs within the counter are not made to change the states at the exactly same time. The clock
does not directly control the time at which every stage changes state. An asynchronous
counter uses T-FF to perform counting function. The actual hardware used is actually J-K
FFs connected in toggle mode. D-FFs are also used. But it is having a disadvantage, insofar
as the unwanted spikes are concerned. This is overcome in parallel counters.

The asynchronous counters are called ripple counters because when the counter, for
example, goes from 1111 to 0000, the first stage causes the second to flip, the second causes
the third to flip and so on. In other words, the transition of the first stage ripples through to
the last stage.

Figure 2.10: Asynchronous counter using D Flip-Flop

2.7 Ring oscillator:-

A ring oscillator is a device composed of an odd number of NOT gates whose output
oscillates between two voltage levels, representing true and false. The NOT gates, or
inverters, are attached in a chain; the output of the last inverter is fed back into the first.
Because a single inverter computes the logical NOT of its input, the last output of a chain of
an odd number of inverters is the logical NOT of the first input. This final output is asserted a
finite amount of time after the first input is asserted; the feedback of this last output to the
input causes oscillation. A circular chain composed of an even number of inverters cannot be
used as a ring oscillator; the last output in this case is the same as the input. A schematic of a
simple 3-inverter ring oscillator is as shown below:-

Figure 2.11: Logic symbol for Ring oscillator

Applications of Ring oscillator:-

• The voltage-controlled oscillator in most phase-locked loops is built from a ring

oscillator.
• A ring oscillator is often used to demonstrate a new hardware technology, analogous
to the way a hello world program is often used to demonstrate a new software
technology.
• Many wafers include a ring oscillator as part of the scribe line test structures. They are
used during wafer testing to measure the effects of manufacturing process variations.
• Ring oscillators can also be used to measure the effects of voltage and temperature on
a chip.

2.8 Frequency divider:-

A frequency divider is an electronic circuit that takes an input signal with a frequency,
fin, and generates an output signal with a frequency:

Where n is an integer.

For power-of-2 integer division, a simple binary counter can be used, clocked by the
input signal. The least-significant output bit alternates at the same rate as the input, the next
bit is the 1/2 the rate, the third bit is 1/4 the rate, etc. An arrangement of flip-flops is a classic
method for integer-n division. Such division is frequency and phase coherent to the source
over environmental variations including temperature. The easiest configuration is a series
where each flip-flop is a divide-by-2. For a series of three of these, such system would be a
divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios
can be obtained. Integrated circuit logic families can provide a single chip solution for some
common division ratios.

2.9 Binary to gray code converter:-

If an n-bit binary number is represented by,Bn Bn-1....B1

Bn=Gn

Bn-1 =Bn Gn-1

..

..

..

B1 =B2 G1
 And its gray code equivalent by , where and are the MSB’s then the gray code bits are
obtained from the binary codes as follows:

Where the symbols stand for the Exclusive –OR operation.

The conversion procedure is as follows:

1. Record the MSB’s of the binary as the MSB’s of the gray codes.

2. At the MSB’s of the binary to the next bit in the binary, recording the sum and
ignoring the carry if any, that is, the XOR the bits. This sum is the next sum
bit of the gray code.

3. At the second bit of the binary to the third bit of the binary, the third bit to the
fourth bit and so on.

4. Record the successive sums as a successive bits of the gray code until all the
bits of the binary number are exhausted.

If an n-bit gray number is represented by G n G n-1....G1 and its binary equivalent

by Bn Bn-1.....B1, then binary bits are obtained from gray bits as follows:

Chapter 3

CMOS
3.1 Introduction:-

Complementary metal–oxide–semiconductor (CMOS) is a technology for

constructing circuits. Historically, MOS technology has been the domain of the digital
designer. Analog designers might use MOS transistors for the input stage of a high input
impedance operational amplifier or use discrete MOS transistors in a linear circuit, but
bipolar technology ruled the linear integrated circuit world. CMOS technology has changed
this. The incredible growth of the CMOS market has caused rapid development of CMOS
technology which has led to advanced CMOS linear devices. There are a number of factors
that will cause the CMOS linear market to continue to grow rapidly and become a very
important part of linear technology. The proliferation of digital circuitry (digital displays,
digital computers, etc.) in analog applications, the large increase in chip density, demands for
smaller integrated circuits, and the rapid increase in demand for accurate, low power devices
will lead to a tremendous number of CMOS linear applications.

3.2 The Technology

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor

field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found
in computers, telecommunications equipment, and signal processing equipment. When a path
to output is created from the voltage source, the circuit is said to be pulled up. The other
circuit state occurs when a path to output is created from ground and the output pulled down
to the ground potential. CMOS circuits are constructed so that all PMOS transistors must
have either an input from the voltage source or from another PMOS transistor. Similarly, all
NMOS transistors must have either an input from ground or from another NMOS transistor.
The composition of a PMOS transistor creates low resistance between its source and
drain contacts when a low gate voltage is applied and high resistance when a high gate
voltage is applied. On the other hand, the composition of an NMOS transistor creates high
resistance between source and drain when a low gate voltage is applied and low resistance
when a high gate voltage is applied.
An important characteristic of a CMOS circuit is the duality that exists between its
PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always
to exist from the output to either the power source or ground.

Now let us consider physical layout of a NAND gate.

 Fig 3.1(a): NAND gate circuit

Fig 3.1(b): NAND gate in physical layout

The inputs to the NAND are in polysilicon. The CMOS transistors (devices) are formed by
the intersection of the polysilicon and diffusion: N diffusion for the N device; P
diffusion for the P device. The output is connected together in metal. Connections
between metal and polysilicon or diffusion are made through contacts.

3.3 Advantages of CMOS:-

The major advantages of silicon gate CMOS compared to metal gate linear ICs are
their higher speed and lower power consumption. These features impact abroad range of
device performance parameters. A faster chip widens the scope of possible applications and
increases signal quality and reliability. For a given frequency response, power can be
reduced. The CMOS ICs can respond to higher frequency inputs, the timers can oscillate at
higher frequencies, and the response times of operational amplifiers and comparators are
reduced while slew rate and operating frequency increase. All of these qualities give wider
signal frequency range and operating and design margin providing increased accuracy and
gain bandwidth at reduced voltages and power requirement over broad operating conditions.
Since most linear design is accomplished with bipolar junction transistors, an
examination of CMOS and Bipolar Junction Technology (BJT) and the merits of each will
best explain the advantages of each technology. CMOS technology is "simpler" than BJT
technology in that the BJT's three dimensional parameters like base depth, base thickness and
base and collector doping do not need to be considered. Since the three-dimensional bipolar
parameters are more difficult to control, CMOS technology leads to a better controlled
process with less variation in crucial device parameters. In addition, recent advances in
processing techniques and equipment are more applicable to CMOS ICs. This means it is
likely CMOS technology will advance more quickly than BJT technology. As the number of
chips required per function and the chip count per device goes down, the need for monolithic
analog and digital circuitry will increase. CMOS linear devices use the same fabrication
process as CMOS digital devices which make integration of analog and digital devices
simple. Bipolar junction transistor technology needs to combine with CMOS technology
which makes fabrication cumbersome, complex and expensive.
The low power consumptions of CMOS linear chips are advantageous in a number of
different ways. Many devices can operate at supply voltages as low as 1V and with ultra low
leakage current which facilitates battery operation. This not only means less power
consumption, but for operational amplifiers and comparators it results
In a lower offset voltage caused by thermal drift and for timers it results in higher
accuracy and stability. This lessens the dependence of timing accuracy on expensive
components, increasing the accuracy and reducing the cost of the timing function. In addition,
as the number of transistors per chip increases, the low power consumption of CMOS ICs
allow greater densities but will require little or no external cooling and very little self-heating
design considerations. An advantage of CMOS over NMOS is that both low-to-high and
high-to-low output transitions are fast since the pull-up transistors have low resistance when
switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings
the full voltage between the low and high rails. This strong, more nearly symmetric response
also makes CMOS more resistant to noise.
Another advantage of silicon gate CMOS linear technology is its compatibility with
CMOS digital technology. The availability and relative ease with which digital functions
such as logic gates, flip-flops, counters and memory cells can be added to the analog library
means that complete systems, including a large amount of digital logic, analog modules, and
passive components such as resistors and capacitors, can all be integrated into one ASIC chip.
This capability is referred to as mixed mode (analog and digital) integration where most
components of an electronic system are implemented in a single monolithic IC chip.
Generally, in a given system only a few other types of components such as transducers,
sensors, inductors, precision resistors, large capacitors, relays, etc. are left off the IC chip.
 The final advantage of CMOS linear technology is high circuit function density and
low cost. As CMOS linear technology is a VLSI (very large scale integration) technology,
many circuit function blocks can be integrated onto the same monolithic IC chip, not only
producing compactness, and system miniaturization, but also producing low per function cost
and high per function reliability. Further, due to integration of large number of elements,
board area cost, labour cost and inventory management costs are greatly reduced.

3.4 Disadvantages:

In spite of the many technological advantages, there are some disadvantages

associated with CMOS linear devices. Although not important for all applications, CMOS
devices often lack the current drive capability of BJT's. Noise can also be a drawback of
CMOS linear ICs. CMOS has an advantage in its low level of shot noise, but its 1/F noise is
larger. The final disadvantage is speed performance and ultra precision for certain
applications.
 Chapter 4
Simulation software

4.1 Introduction:-

Microwind is a computer-aided design program for layout editing, circuit extraction

and circuit simulation of microelectronic circuits on a physical layout level. The
MICROWIND program allows the student to design and simulate an integrated circuit. The
program has been used to a large extent worldwide for introductory courses in CMOS design
both for engineers in industry as well as university students in many countries.

Microwind is a truly integrated software encompassing IC designs from concept to

completion, enabling chip designers to design beyond their imagination.Microwind integrates
traditionally separated front-end and back-end chip design into an integrated flow,
accelerating the design cycle and reduce design complexities.

It tightly integrates mixed signal implementation with digital implementation, circuit

simulation, transistor level extraction and verification-providing an innovative education
initiative to help individuals to develop the skills needed for design positions in virtually
every domain of IC industry.

Microwind includes all the commands for a mask editor as well as new original tools
never gathered before in a single module. One can gain access to Circuit Simulation by
pressing one single key. The electric extraction of the circuit is automatically performed and
the analog simulator produces voltage and current curves immediately.

A specific command displays the characteristics of pMOS and nMOS, where the size
of the device and the process parameters can be very easily changed. Altering the MOS
model parameters one can see the effects on the V ds and Ids curves. The Process Simulator
shows the layout in a vertical perspective, as when fabrication has been completed. The Logic
Cell Compiler is a particularly sophisticated tool enabling the automatic design of a CMOS
circuit corresponding to user’s logic description. The cell is created in compliance with the
environment, design rules and fabrication specifications. It has a valuable screen to
understand the MOS characteristics, with a user interface that designers will like.

4.2 Special features of Microwind:-

>The logic editor and simulator are used to validate the architecture of the logic circuit before
the microelectronics design is started. It provides a user-friendly environment for hierarchical
design and fast simulation with delay analysis, which allows the design and validation of
complex logic structures. It handles both conventional pattern based logic simulation and
intuitive on screen mouse driven simulation. It gives the analysis of both current and power.

> The double-gate MOS is used for simulation of non-volatile memories such as EPROM,
EEPROM and FLASH. The command “UV exposure” erases floating gates and removes all
electrons. The programming is performed by a very high voltage supply on the gate (7V in
0.12μm), a 1.2V voltage difference between drain and source. Some electrons are sufficiently
accelerated to pass through the gate oxide by hot tunneling effect.

> The 2D-viewer of Microwind is a tool which is useful for understanding the building up of
the oxide structure. One can zoom the layout to study oxide and lateral (surface) MOS
structure.
> The user can analyze and view cross sectional view of silicon layers and 3D view of
circuits. One can draw real time images of the layout and navigate in full 3D on the surface or
inside the IC. The user can modify the viewing position in X, Y, Z and play with light
sources to create illustrative views of the layout.With the 3D-viewer one can view the step-
by-step fabrication of an arbitrary chosen part of the layout for example how contacts are
manufactured, how metal layers are made or how a polysilicon gate of the self-alignment
type is fabricated.
> No SPICE or external simulator is needed for verification of CMOS circuits. Microwind
program has in-built analog like simulator which supports level1, level3 and BSIM4 MOS
models.With features like fast time-domain, voltage and current estimation, very intuitive
post processing, frequency estimation makes Microwind a very efficient software. Even
power estimation of circuit simulation can be checked on-screen.

> Microwind possesses precision CMOS layout editors which can support technologies right
from 1.2 μm till 22 nm with unsurpassed illustration capabilities. Sub-micron, deep-
submicron, nanoscale technology are supported. With its enhanced editing commands and
layout control the user’s development times would be much shorter.

> It can generate a VERILOG description of the schematic for layout conversion.User can
check the gate oxide and the MOS lateral drain diffusion structure.

> It has the ability to label nodes and allow intuitive control of the simulation (supply clock,
pulse, PWL, maths).It has inbuilt interconnect analyzer to compute field between ground
planes and conductor.

> It also features the symbols, models and assembly support for 8051 and 16F84 controllers.
Designers can create logic circuits for interfacing with these controllers and verify software
programs. One can change the model parameters and see their effects on Id/Vd, Id/Vg, Id
(log)/Vg, threshold vs. length. The user can also fit the simulations with measurements he
made in test-chips fabricated in 0.35, 0.25 and 0.18µm.
 Chapter 5
Design Rules

5.1 Introduction:

Design rules describe how small features can be and how closely they can be packed
in a particular manufacturing process. Industrial design rules are usually specified in microns.
This makes migrating from one process to a more advanced process difficult because not all
rules scale in the same way.
Mead and Conway popularized lambda-based design rules based on a single
parameter- ‫ג‬.Lambda characterizes the resolution of the process and it is generally half of the
minimum drawn transistor channel length. This length is the distance between the source and
drain of a transistor and is set by the minimum width of a polysilicon wire. For example, a
180 nm or 0.18µm process has minimum polysilicon width of 0.18 microns and uses design
rules with 0.09=‫ ג‬cubic µm.

A conservative but easy-to-use set of design rules for layouts in an n-well process is as
follows:
• Metals and diffusions have minimum width spacing of 4‫ג‬.
• Contacts are 2‫ג‬2*‫ ג‬and must be surrounded by 1‫ ג‬on the layers above and below.
• Polysilicon uses a width of 2‫ג‬.
• Polysilicon overlaps diffusion by 2‫ ג‬where a transistor is desired and has a spacing of
1‫ ג‬away where no transistor is desired.
• Polysilicon and contacts have a spacing of 3‫ ג‬from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6‫ ג‬and avoids nMOS transistors by 6‫ג‬.

Figure 5. 1: simplified ‫ג‬-based design rules

In 0.12μm technology, the metal layers 1, 2, 3 and 4 have almost identical characteristics.
Concerning the design rules, the minimum size, w of the interconnects, is 3 lambda. The
minimum spacing is 4 lambda (Figure 5.1). In Microwind, each interconnect layer is drawn
with a different color and pattern.
Examples of minimum width and distance interconnects are reported in figure 5.2.

Figure 5.2: Metal layers, associated rules and patterns as appearing in the Microwind editor

These minimum width and spacing are critical dimensions. They define the limit
below which the probability of manufacturing error rises to an unacceptable level. If we draw
metal 1 lines with 2 lambda width and 2 lambda spacing, interconnect interruptions or short-
cuts may appear, as illustrated in figure. Prior to fabrication, the design rules must be checked
to ensure that the whole circuit complies with the width and spacing rules, to avoid unwanted
interruptions or bridges in the final integrated circuit. The Microwind command to get access
to the design rule checker is Analysis → Design Rule Checker. Still, there exists a
significant probability of manufacturing error even if the circuit complies with all design
rules. A wafer of 500 integrated circuits has a typical yield of 70% in mature technologies,
which means that 30% of the circuits have a fabrication error and must be rejected. The yield
may drop to a percentage as low as 20%, for example in the case of state-of-the art
technologies with all process constraints pushed to their limits, and very large silicon dies.
The manufacturing of interconnects which violate the minimum width and distance may
result in interruptions or short-cuts, which may have catastrophic consequences on the
behaviour of the integrated circuitas shown in figure 5.3.

Figure 5.3: interconnects which violate the minimum width and distance
 The practical design width for metal interconnects is usually a little higher than the
minimum value. In Microwind, the routing interconnects are drawn in 4 lambda width. The
pitch is the usual distance that separates two different interconnects. In 0.7μm, due to severe
constraints in the contact size, the pitch has been fixed to 10 lambda. In deep submicron
technology, improvements in contact sizing may reduce that pitch to 8 lambda. In 0.12μm
technology, this routing pitch is equivalent to 0.48μm.

Integrated circuit manufacturers usually specify this routing pitch in their non-
confidential technological descriptions, as one of the commercial arguments for designing
compact (and behind this, low cost) integrated circuits. Common industrial pitch in 0.12μm
CMOS process is around 0.4μm. The design styles in 0.7μm and 0.12μm are illustrated in
figure 5.4

Figure 5.4: Conductor parameters vs. technology