PCBA Debug Guide

PCIE Faults

Debug Guide

Rev 2.8

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PCBA Debug Guide

1. Revision History
Author/Revised
Revision Description Date
By
1.0 Draft release Luis Rodríguez 14 0ct 2005

2.0 Category C added Luis Rodríguez 24 Jan 2006

Updated category B
(Refer to the table)
(Modified the components to replace with
the CPUs bits 00010101: U4D1 instead of Luis Rodríguez
2.1 06 Mar 2006
U2E1 for the 1st repair, U7D1 instead of José C. Bravo
U2C1 in the 2nd repair and there are no 3rd
repair)

Updated category B
(Refer to the table) Luis Rodriguez
2.2 08 Mar 2006
(Added 2 nd rd
and 3 repair in failures with José C. Bravo
CPUs bits 01000100)
Updated category B
(Refer to the table) Luis Rodriguez
2.3 09 Mar 2006
(Added repair action for CPU bits José C. Bravo
00000000)
Updated category B
(Refer to the table) Luis Rodriguez
2.4 22 Mar 2006
(Added repair action for CPU bits José C. Bravo
10101111)
Updated category B
(Refer to the table) Luis Rodriguez
2.5 04 April 2006
(Added repair action for CPU bits 01010001 José C. Bravo
& 10110011)
Updated category B
(Refer to the table) Luis Rodriguez
2.6 09 May 2006
(Added repair action for CPU bits José C. Bravo
10010110)
Updated category A & C
(Added replacement of component in first
repair U2C1 & in second repair U4D1 in Luis Rodriguez
2.7 14 July 2006
category A ) José C. Bravo
(Added replacement of component in first
repair: U4D1 in category C)
Updated category B & C
(Refer to the table)
(Added repair action for CPU bits
00100000, 01000101, 01001111,
2.8 10010100, 01011000, 10101101 & Moisés Anzaldo 28 July 2006
10100010)
(Added replacement of component in first
repair: Fault Infineon R3G6 & R3G7)

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2. Table of Contents
1. Revision History ......................................................................................................................... 2
2. Table of Contents........................................................................................................................ 3
3. Introduction................................................................................................................................. 3
4. Scope.......................................................................................................................................... 3
5. Audience ..................................................................................................................................... 3
6. Process ........................................................................................................................................ 4
7. Category Grouping...................................................................................................................... 4
7.2 Category A Error Code 0x09................................................................................................ 4
7.2 Category B Error Code 0x0A ............................................................................................... 6
7.3 Category C Error Code 0x08................................................................................................ 9

3. Introduction
This document describes a process for diagnosing and repairing NO PCIE failures from
the PCBA tester. The process and groupings below outlines possible measurements to
determine the appropriate component, for repair or replacement. Core digital errors can
also be identified by 3 of the 4 LEDs on the “ring of light” flashing.

4. Scope
This document has been developed from experience gained on X803158-001 Xenon
XDK motherboards. The failure analysis process outlined in this document should be
used in conjunction with the “Motherboard Debug Guide Development Process”
document.

5. Audience
This document is aimed at Engineers and Technicians who are performing first pass
debug of core digital failures from the XBOX360 motherboard PCBA tester.

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PCBA Debug Guide

6. Process
7. Category Grouping
Note: Error Codes on front panel are in hexadecimal: 0xFF
Error Codes in the Functional Test are shown with 8 digits: 0x12345678
Bits get on the PCBA test points are 8 digits: 01010101

7.2 Category A Error Code 0x09

The PCI-E link failed to enter L0 in time during seqUnReset

Test Name: PowerGroupPowerUp, Variation: PCBA-TighterLimits

Error Code: 0x81600868
Error Facility: TESTER (FACILITY_MTE_POWER)
Error Description: Measured value lower than limit V12_CURRENT: 5.963584 less than
6.500000
Test Name: PowerGroupPowerUp, Variation: PCBA-TighterLimits
Error Code: 0x81600BE5
Error Facility: TESTER (FACILITY_MTE_POWER)
Error Description: The PCI-E link failed to enter L0 in time during seqUnReset. SMC
ErrorCode: 9

ƒ Replace U2C1 as a first repair

ƒ Replace U4D1 as a second repair

ƒ If the failure is still present, continue next repairs

• Check for proper voltage on V_GPUPCIE (U5C1 pin2), target is 1.25v, if

not present change U5U1

• Check for proper voltage on V_SBPCIE (U3P1 pin 2), target is 1.87v, if not
present change U3P1

• Check for PCIE CLK

• PCIE_CLK_DP on FT3P2, frequency of 100MHz
• PCIE_CLK_DN on FT3P1, frequency of 100MHz, as shown below

• Check C2C1, C2C2, C2C3, C2C4, C4D1, C4D2, C4D3 & C5D1

• Check GPU_CLK_DP/DN, frequency of 100MHz (junction between

R3C16 & R3C15)

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PCBA Debug Guide

PCIEX_CLK_DP

PCIEX_CLK_DN

If frequencies are not present then change U3B4

• Check CPU_RST_N (R7R4 pin 2) target is 1.24v, if not voltage change

U2C1

CPU_RST_N

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CPU_RST_N (via
near U2C1)

7.2 Category B Error Code 0x0A

Test Name: TcsBootStrappingDuration, Variation: PCBA
Error Code: 0x81510027

At this point of failure the V_CPUCORE is good, the PCI-E link has entered into a
known good state, and the SMC releases the CPU reset line CPU_RST_N.
CPU_RST_N is expected to go high. The SMC monitors the CPU initialization process
as it comes out of reset and begins to execute code. If the CPU fails to initialize properly
the SMC will enter the error state ERROR_NO_HANDSHAKE.

A typical problem found with this failure is that CPU programming code in flash is
corrupted. The CPU initializes and begins executing code from flash and falls on its
face. Change the Flash as a first repair.

The CPU accesses flash through the path of CPU Chip ↔ Front Side Bus ↔ North
Bridge chip ↔ Back Side Bus ↔ South Bridge chip ↔ Flash chip. See picture below.
Failure along any segment of this path will cause ERROR_NO_HANDSHAKE as the
CPU cannot execute code from flash.

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Note: At this early time the SMC does not double check the status of the Back Side Bus (BSB)
after a failure of the CPU to handshake. (A failure of the BSB is indicated with the previous error
code ERROR_NO_PCIE). It is possible that the BSB has failed after initial good status.

LAN/USB
AV Connector Power

FAN ASSEMBLY
Connector
Supply
Connector
Audio
LAN DAC SPDIF

South ANA
GPU
Clock

Bridge Gen

ODD
Voltage Regulators
SAT SMC B
A
ack
Bu Sid
ODD
s e
Pwr

GPU
North Front
CPU CPU
Side Bus
Bridge Voltage
FLASH

HDD
SATA RAM
Regulators

RAM RAM

USB
Game
Eject IR USB Memory USB Memory Binding Argon
Pad
Switch Rx Connector Connector Button Connector

• Check for proper control and power good signals.

CPU Clock Signal

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If CPU CLK (junction between R3C12 & R3C18) is not present or the signal is bad (e.g.
picture below), replace U3B4 as a first repair.

Bad CPU Clock Signal

• If ENET_RST_N (boards with U1B2) & AUD_RST_N signals are not present and
the others are normal, change U7D1.

CPU Bits:

Bit: 0 12345 6 7

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PCBA Debug Guide
Do measures on the test points behind U7D1 (bottom side)
e.g.
Bits order: 76543210
Value 64: 01000000
Value 175:10101111

Front panel Code CPU bits 1st repair 2nd repair 3rd repair
00000000
U7D1
(0)
00010100
U4D1 U7D1
(20)
00010101
U4D1 U7D1
(21)
00010110
U4D1 U7D1
(22)
00011000
U4D1 U7D1
(24)
00100000
U7D1
(32)
00101110
U4D1 U7D1
(46)
01000000
U3E1 U3D1 U4D1
(64)
01000100
U5F1/U5U1 U3E1/U3T1 U3D1/U3R1
(68)
01000101
U3D1/U3R1 U3E1/U3T1 U5F1/U5U1
0x0A (69)
01001111
U2E1 U7D1
(79)
01010001
U2E1
(81)
01011000
U2E1
(88)
10010100
U4D1
(148)
10010110
U2E1 U4D1
(150)
10101101
U2E1
(153)
10100010
U2E1
(162)
10101111
U4D1 U4F1/U4U1
(175)
10110011
U2E1
(179)

7.3 Category C Error Code 0x08

ƒ Replace U4D1 as a first repair

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ƒ If the failure is still present, continue next repairs

• Check for proper voltage on V_GPUPCIE (U5C1 pin2), target is 1.25v, if

not present change U5U1 (first check V_3P3 on U1F1 pin 4 replace as
necessary)

• Check for proper voltage on V_SBPCIE (U3P1 pin 2), target is 1.87v, if not
present change U3P1

• Check voltage V_MEM on DB3F1, expected value 1.8v, if the voltage is

not present: Measure resistance to GND, the expected value is 63Ω, if the
resistance is ok then check the signal VREG_1P8_EN on junction
between R3G5 & R3G1, in STBY mode is high, when the console is
turned on the signal goes low, this signal comes from the South Bridge if
is not present replace U2C1, if is present replace U4V1

• Fault because of the voltage V_MEM altered in units with memories

Infineon

Impedance Voltage in DB3F1 Repair without front panel

between R3G6& For memory short in code
R3G7 a GND Infineon DB3F1&GND
Normal value 600Ω a 800Ω 2.1V N/A N/A
Elevates R3G6& R3G7 Bigger a 5K Ω No connected Replace R3G6
No connected & R3G7

Elevate R3G6 1.17kΩ a 1.49 No connected Replace R3G6

No connected kΩ y R3G7
Elevate R3G7 2.20 kΩ a 2.40 0.7V Replace R3G6 0X08
kΩ y R3G7
Inverted 908Ω a 912 Ω 1.30V Replace R3G6 0X08
R3G6& R3G7 y R3G7

Any another value of impedance between R3G6 & R3G7 a GND replace
R3G6 & R3G7

Note: Units with memories Infineon first check R3G6 & R3G7 for a possible
bad repair, if the impedance on nodes V_MEM to GND is less than 5Ω (with
front panel code 0X08 or 0X14) replace memories and the GPU

• If the impedance on these nodes (V_MEM & GND) is less than 50Ω
replace memories

• If the impedance on these nodes (V_MEM & GND) is less than 0.3Ω
check in X- ray test memory and GPU possible short, change integrated in
short.

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