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Data-acquisition system uses fault protection

Catherine Redmond, Analog Devices, Limerick, Ireland
ensitive systems, such as those When a fault condition occurs, the

S in aircraft, must withstand fault

conditions, thereby avoiding
component and system damage, be-
VSS
voltage on the input of the channel
protector exceeds a voltage set by the
supply-rail voltage minus the MOS-
cause a sensor failure could cause a FET’s threshold voltage. For a positive
PMOS
catastrophic event to occur.A channel overvoltage, this voltage is VDD⫺
protector, comprising two n-channel NMOS NMOS VTN, where VTN is the threshold volt-
MOSFETs connected in series with a age of the NMOS transistor (typical-
p-channel MOSFET, can protect sen- PMOS
ly, 1.5V). In the case of a negative over-
sitive components from voltage tran- voltage, the voltage is VSS⫺VTP, where
sients in the signal path, whether or VDD VSS VDD VTP is the threshold voltage of the
not the power supplies are present A channel protector can protect sensi- PMOS device (typically, ⫺2V). When
Figure 1
(Figure 1). The channel protector tive circuitry from voltage transients. the input of the channel protector ex-
acts as series resistor during normal ceeds either of these voltages, the pro-
operation. If the input exceeds the pow- tions in which correct power sequencing tector clamps the output within them.
er-supply voltages, one of the MOSFETs cannot be guaranteed and for hot-inser- These devices offer bidirectional fault and
turns off, clamping the output within the tion rack systems. Figure 2 shows an overvoltage protection, so you can use the
supply rails, thus protecting the circuitry ADG465 channel protector with an input inputs or outputs interchangeably. Figure
in the event of overvoltage or supply-loss signal that exceeds the power-supply volt- 3 shows the voltages and MOSFET states
conditions. Because channel protectors age. The protector clamps the output sig- for a positive-overvoltage event.
work regardless of the presence of the nal, protecting the sensitive components The output load limits the current
supplies, they are also ideal for applica- that follow the channel protector. during the fault condition to VCLAMP/RL
(Figure 4). If the supplies are off, the
VDD VSS
protector limits the fault current to
nanoamps. Figure 5 shows how you can
Figure 2 VIN
VD1 VS1
VOUT use the ADG466 channel protector to
protect the sensitive inputs of an instru-
ADG465
VIN
VOUT mentation amp from a sensor fault. In
applications that require a multiplexer in
VDD
VDD

Data-acquisition system
OUTPUT CLAMPED
uses fault protection ......................................69
AT VDDⳮ1.5V
Take steps to reduce
antiresonance in decoupling ......................70
The channel protector clamps overvoltage transients to a safe level. Precision level shifter has
VDD–VTN excellent CMRR ..............................................72
13.5V
Celsius-to-digital thermometer works
with remote sensor ........................................74
POSITIVE NMOS PMOS NMOS
OVERVOLTAGE Quasiresonant converter uses
(20V)
a simple CMOS IC..........................................74
SATURATED NONSATURATED NONSATURATED
Simple circuit serves
Figure 3 VDD VSS VDD as milliohmmeter ..........................................78
15V –15V 15V
Publish your Design Idea in EDN. See the
NOTE: VTN = NMOS-THRESHOLD VOLTAGE (1.5V). What’s Up section at www.edn.com.

The voltages and MOSFET states appear like this during a positive-overvoltage event.

www.edn.com April 15, 2004 | edn 69

design
ideas
addition to channel protection, you can VD VG VS ⌬V
VDD
use the ADG439F fault-protected, four- 15V 13.5V
20V
channel analog multiplexer PMOS NMOS
Figure 4
(Figure 6). These multiplex-
N+ N+ N+ NONSATURATED
ers use a series n-channel, p-channel, n- OVERVOLTAGE EFFECTIVE OPERATION
RL VCLAMP
channel MOSFET connection. During OPERATION SPACE-CHARGE N-CHANNEL
(SATURATED) REGION IOUT
fault conditions, the inputs or outputs VG – VT =13.5V
VT = 1.5V P–
appear as open circuits, protecting the
sensor or signal source as well as the
output circuitry.왏 The output load limits the current to VCLAMP/RL during a fault condition.

ADG439F
ADG466

–
SENSOR 1 ADC DSP SENSOR 1
+ –
ADC DSP
IN AMP +

SENSOR 4 IN AMP

ANALOG OUT DAC REFERENCE

TO ACTUATOR ANALOG OUT DAC REFERENCE
Figure 5 Figure 6 TO ACTUATOR

In this circuit, the ADG466 channel protector guards the sensi- A multiplexer in a data-acquisition system protects the signal source as well
tive inputs of an instrumentation amplifier from a sensor fault. as the output circuitry.

Take steps to reduce antiresonance in decoupling

Dale Sanders, X2Y Attenuators, LLC, Farmington Hills, MI
o maintain power integrity on pc

T
10
boards, you need multiple capaci- 0
tors to decouple the power-distri- ⳮ10
ⳮ20
bution system. A typical configuration
VOLTAGE ⳮ30
might comprise five capacitors connect- (dB␮V) ⳮ40
ed in parallel between the power and the ⳮ50
ground traces or planes. To provide ⳮ60
broadband decoupling per- ⳮ70
Figure 2 ⳮ80
formance, assume the indi- 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz
vidual values of the capacitors are 470,
FIVE STANDARD CAPACITORS: 470, 1, 10, 100, ONE STANDARD 1206 1-nF CAPACITOR
1, 10, 100, and 220 nF (Figure 1). This 220-nF (801-nF TOTAL CAPACITANCE) ONE STANDARD 1206 1000-nF CAPACITOR
parallel network provides 801-nF total ONE STANDARD 1206 10-nF CAPACITOR ONE STANDARD 1206 470-nF CAPACITOR
capacitance to the power-distribution ONE STANDARD 1206 220-nF CAPACITOR
BOARD S21
system. If you measure each capacitor
POWER
Measurements with a vector-network analyzer reveal undesirable antiresonance effects.

0.801 ␮F
TOTAL
with a vector-network analyzer, you can POWER A
470 nF 1 nF 10 nF 100 nF 220 nF identify each capacitor’s SRF (self-res- G1 G2
400 nF
onant frequency). Figure 2 is a plot of (801 nF TOTAL)
each capacitor’s SRF, as well as the SRF B
GROUND of the overall parallel connection. Each RETURN
SRF can cause antiresonance in the par-
Figure 1
allel decoupling configuration. The
Figure 3
A typical decoupling configuration uses several antiresonance occurs when one ca-
multilayer-ceramic capacitors connected in pacitor is still capacitive, while another A 400-nF X2Y capacitor yields a total decou-
parallel. has become inductive. pling capacitance of 800 nF.

70 edn | April 15, 2004 www.edn.com

design
ideas
A way to considerably reduce the an- 10
tiresonance effects is to use a single 400- 0
ⳮ10
nF X2Y capacitor for decoupling. (Ca-
ⳮ20
pacitors using X2Y technology are ⳮ30
available, for example, from Johanson VOLTAGE
(dB␮V) ⳮ40
Dielectrics (www.johansondielectrics. ⳮ50
com). You measure the capacitance rat- ⳮ60
ⳮ70
ing for an X2Y component
Figure 4 ⳮ80
from line to ground; in oth- 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz
er words, from an A or a B terminal to FIVE STANDARD CAPACITORS: 470, 1, 10, 100, 1 X2Y 1206 400 nF BOARD S21
either of the G1 or G2 terminals in Fig- 220nF (801-nF TOTAL CAPACITANCE)
ure 3. So, the total capacitance a 400-nF
X2Y component supplies, connected as The single X2Y decoupling capacitor displays no antiresonance effects.
in Figure 3 would be double the capac-
itance rating, or 800 nF. Figure 4 shows pling as the standard decoupling con- sizes as standard capacitors (1812, 1210,
that a single X2Y capacitor with the figuration but without the antireso- 1206, 0805, and 0603), the use of X2Y
same total capacitance as in Figure 1 nance effects. In addition, because X2Y components saves pc-board space and
provides the same broadband decou- components come in the same package reduces layout complexity.왏

Precision level shifter has excellent CMRR

Ronald Mancini, Texas Instruments, Bushnell, FL
ost designers make VIN2⫺VIN1⫹VREF ⫹VNREF.

M level shifters with

op amps and 1%-
tolerance discrete resis- VIN1
–IN
25k 25k SENSE
to
Now, you need to elim-
inate the reference noise
obtain a clean level-
tors. Discrete-resistor shifted signal. You could
mismatching limits the connect the X end of C1 to
+V
op amp’s CMMR (com- ground to shunt the ref-
mon-mode rejection ra- _ erence noise to ground,
tio) to 40 dB, so you can- VOUT but this solution may be
25k
not use op amps in VIN2 + ineffective because the
+IN
circuits that require high source impedance of the
CMRR. Differential am- –V reference is low. When,
plifiers contain precision 25k however, you connect the
matched internal resis- INA133
X end of C1 to the VIN1 sig-
tors, so ICs such as the nal source, the differential
INA133 can readily VREF amplifier acts as a lowpass
achieve CMRRs of ap- filter and rejects the refer-
proximately 90 dB. They C1 ence noise. This circuit
can offer such high keeps the input imped-
CMRR by trim- Figure 1 X ance of the differential
ming internal matched amplifier low (approxi-
resistors. Assume that C1 allows the level shifter to act as a lowpass filter that rejects the reference noise. mately 25 k⍀ for the
each input in the circuit of INA133) to facilitate
Figure 1 has an associated noise voltage noise cancellation. Careful cabling and matching. Thus, you must keep the signal
(VN1, VN2, and VNREF). The transfer func- differentially coupling the signal into the source impedance low to prevent gain er-
tion of the amplifier circuit is differential amplifier’s inputs force the rors. The source impedance should be
V OUT ⫽(V REF ⫹V NREF )⫹(V IN2 ⫹V N2 )⫺ noise on the signal inputs to be equal less than 1/1000 the input impedance to
(VIN1⫹VN1). Note that the reference volt- (VN1⫽VN2). The input noise is a com- minimize gain error. If this situation
age shifts the output signal, either single mon-mode signal, so the differential am- doesn’t occur naturally, then it is best to
or differential. Once this level shifting oc- plifier rejects it to the best of its ability buffer the inputs.왏
curs, you can turn your attention to the (nominally, 90 dB). Now, VOUT⫽
72 edn | April 15, 2004 www.edn.com
design
ideas
Celsius-to-digital thermometer
works with remote sensor
Elana Lian and Chau Tran, Analog Devices, Wilmington, MA
ou can use a single- combination of R1 and R2

Y supply system to pre-

cisely measure the
temperature at a remote
R1
2k R3
50k
RF
50k
develops a 1V drop, and
you adjust R2 to provide a
nominal current of 353.15
location with less than R2
V ␮A. Thus, the current
1k DD
1⬚C error over a 0 to _ through the feedback re-
100⬚C range (Figure 1). IC1 OUT
VIN AD7476
DIGITAL-
DATA
sistor, RF, varies from ⫺80
The circuit includes T1, a +
AD8541
OUTPUT to ⫹20 ␮A as the temper-
low-cost AD590 tempera- ature varies from 0 to
GND
ture sensor; IC1, an LONG
R4 100⬚C. The voltage across
WIRES
AD8541 rail-to-rail am- 200k this resistor varies from
plifier; four resistors; a ⫺4 to ⫹1V. The 4V offset
trimming potentiometer; T1
causes the output voltage
and an ADC. You can – + of the amplifier to vary
AD590
omit the ADC if you need from 0 to 5V.
an analog output. You Figure 1
To guarantee the accu-
could replace the trim- This system precisely measures temperature at a remote racy of 1⬚C throughout
ming potentiometer with location, with less than 1⬚⬚C error over a 0 to 100⬚⬚C range. the range, you need to per-
an AD8400 or AD5273 form a calibration proce-
digital potentiometer for easier calibra- low-power, rail-to-rail operational am- dure. At a known temperature, such as
tion. The feedback resistor, RF, should be plifier. It has a high common-mode volt- 25⬚C, adjust trimming potentiometer R2
a precision resistor to minimize the scale- age range and extremely low bias cur- to obtain the desired voltage at the out-
factor error, but the accuracy of the re- rents. You can calibrate out its 1-mV put of the amplifier, 1.250V, or the de-
maining resistors is not critical. You can typical offset, the resistor, and AD590 er- sired code at the output of the ADC,
choose the grade of the AD590 sensor to rors. The output swing of the amplifier 400H. Once you perform the calibration,
achieve the required accuracy. is 25 mV to 4.965V with a single 5V pow- you can calculate the temperature in Cel-
The AD590 provides an output current er supply, limiting the output by about sius at any measured point inside the
proportional to absolute temperature (1 0.5⬚C on either end. range by multiplying the output voltage
␮A/K). In this application, the circuit off- This circuit can derive its power from by 20. Because the sensor has a current
sets and scales the output to provide a a single 5V power supply. The output of output, it is immune to voltage-noise
full-scale range of 0 to 5V with a scale fac- the AD590 varies from 273.15 to 373.15 pickup and voltage drops in the signal
tor of 50 mV/⬚C over the chosen tem- ␮A as the temperature varies from 0 to leads; you can thus use it at a remote lo-
perature range of 0⬚C—the freezing 100⬚C. The positive input of the AD8541 cation. You should use a twisted-pair or
point of water—to 100⬚C, the boiling has an offset of 4V to provide sufficient shielded cable.왏
point of water. The AD8541 is a low-cost, headroom for the AD590. The series

Quasiresonant converter uses a simple CMOS IC

Francesc Casanellas, Aiguafreda, Spain
igure 1 shows a flyback power sup- voltage. The converter works in the keeps the gate input high. When the

F ply that has low noise and uses a sim-

ple CMOS 4093 IC for its control.
The electrical noise of a converter arises
mainly when current switches on. Diode
recovery and charging parasitic capaci-
tances create high di/dt, which is the main
cause of noise. The converter in Figure 1
(pg 76) has a low noise level, because it
slowly switches current on at nearly zero
74 edn | April 15, 2004
boundary between discontinuous and
continuous mode and switches on when
the drain voltage is at its lowest value. To
avoid working with low gate voltages,
which would cause excessive MOSFET
losses, ZD1 conducts and enables the in-
put gate of the 4093 when the voltage is
high enough. When the supply starts, the
auxiliary nonisolated winding through D3
MOSFET is on, current increases linearly
until the base of Q5 starts to conduct, and
this transistor turns the MOSFET off. The
flyback operation then starts, and the pri-
mary energy charges the output capaci-
tors. During this phase of operation, D5
and R6 keep Q5 conducting and the MOS-
FET off. When the energy has discharged,
(continued on pg 78)
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design
ideas
VCC
C4
R4
D3

D6
R5 R3 C3
ZD1 + VOUT
10k D4 C7
4.7V
D5
D2 +
C5 5
33 ␮F 14 2222 R6
6 D1
ZD3 8.2k Q3
15V 14 Q1
1 8 R16
C1 3 10
1 ␮F 2 9
R15 100
7 4093 Q2 R17
R2 4.7k R7
12
4.7k 11 R13
13 2907 1k OC1
C6
Q5 47 pF 4N35
C2 R8 R10
100 ␮F R1 Q4 470
2369 22k C10
R9
1k 2369 R12
C9 R11
470k
1 nF
ZD2 C8

TL431
R14

Figure 1
Using a simple CMOS IC, this flyback power-supply circuit exhibits extremely low noise.

76 edn | April 15, 2004 www.edn.com

design
ideas
(continued from pg 74)
D5 stops conducting, as do the secondary
diodes, so no recovery problems exist.
The time constant of R5 and C5 keeps
the MOSFET off for a while. The output
capacitance of the MOSFET plus the
parasitic capacitance of the primary res-
onate with the primary inductance and
the voltage decreases. R5 and C5 allow the
MOSFET to turn on when the voltage
Simple circuit serves as milliohmmeter
AM Hunt, Lancaster Hunt Systems Ltd, Shepperton, UK
hen I was recently debugging a
W design, I discovered that a short
circuit existed from a ground
plane to a power plane. I did not have ac-
cess to a milliohmmeter or an equivalent
tester for locating this type of short cir-
cuit. So, I logged onto the Internet to find
an easily constructible milliohmmeter. I
78 edn | April 15, 2004
has reached the minimum value. The
values are valid only for this case. The
circuit of Figure 1 not only minimizes
turn-on losses, but also reduces electri-
cal noise. Voltage regulation uses tradi-
tional techniques, using a TL431. The
optocoupler current adds to the shunt
current. Because the MOSFET turns on
when current is zero, the gate resistor
may be high, so parasitic capacitances
found the answer in a manufacturer’s
data sheet, which outlined the basic four-
wire method of making low-resistance
measurements. The method uses a volt-
age-reference IC as the input stage for a
controlled constant-current source. A
quick dig in the old component bucket
revealed a supply of LM317 variable-volt-
charge slowly, further reducing switch-
ing noise. The circuit around Q4 is op-
tional; you can use it in most power sup-
plies. It kills the current glitch when Q3
turns on. It is more effective than the
usual RC circuit, and it allows a low duty
cycle at low loads. Note that many of the
component values in Figure 1 are un-
designated; you should determine these
values to fit the application.왏
age regulators. These ICs provide 1.25V
between their VOUT and VADJ terminals, a
constant voltage to attack the constant-
current problem. The other problem to
attack was the output-voltage range of
the constant-current source. The circuit
I was working on used a 3.3V supply, so
I had to limit the voltage to 3.3V. An
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design
ideas
S1A
LM317, configured as a DVM on a millivolt range.
Q1
constant-current source, BD636
The DVM reads a voltage
S1B
delivers an output voltage IC1
that is proportional to the
VIN V
equal to the in- LM317 OUT resistance under test. If you
put if the output Figure 1 VADJ calibrate the circuit as sug-
P1 P2
resistance is too high. Be- 100 10
gested, then the reading is
cause I wanted to use a 10⍀/V on the 100-mA
bench supply or a 9V bat- + +
9V R1 R2 range and 100⍀/V on the
BATTERY 68 6.8
tery, the voltage would fry 3V
OR BENCH 10-mA range.
– BATTERY – SUPPLY
any 3.3V logic on the To track down pc-board
board. Ideally, I wanted short circuits, attach the
voltage to be limited to unit with test points A and
A
1.5V. So, I came up with the B across the suspected
configuration in Figure 1. B
shorted signals. Attach one
IC1 controls the base of DVM probe to test point A
the npn Darlington transis- Make your own milliohmmeter, using a voltage-regulator IC and some resistors. and use the other to
tor, Q1. The IC regulates the probe the circuit. Con-
voltage across the selected resistor to form tween test points A and B and measuring stant voltage along a trace indicates that
the constant-current source. The current the voltage across the resistor using a no current is flowing and that the trace is
source delivers either 10 or 100 mA, de- DVM (digital voltmeter). I used 5 and not the source of the short circuit. Look
pending on which emitter resistor is in the 10⍀ and set one S2 position for 10 mA for high readings on the trace with the
circuit. The purpose of S1 is to give longer and the other for 100 mA. To measure a low reading and low readings on the trace
battery life. You can calibrate the current small resistance, you attach test points A with the high reading, to locate the
source by strapping a resistive load be- and B across the resistance. You set the source of the short circuit.왏

80 edn | April 15, 2004 www.edn.com