HybridPack 1

HybridPACK™
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with

HybridPACK™1 Module
Application Note
V2.0, 2010-04
System Engineering
Edition 2010-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Evaluation Kit for Applications with HybridPACK™1 Module
Revision History: 2010-04, V2.0

Previous Revision: V1.1
Page Subjects (major changes since last revision)
All Many editorial changes due to next generation Hybrid Kit for HybridPACK™1
Trademarks of Infineon Technologies AG

A-GOLD™, BlueMoon™, COMNEON™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™,
CIPOS™, CoolMOS™, CoolSET™, CONVERPATH™, CORECONTROL™, DAVE™, DUALFALC™, DUSLIC™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, E-GOLD™, EiceDRIVER™,
EUPEC™, ELIC™, EPIC™, FALC™, FCOS™, FLEXISLIC™, GEMINAX™, GOLDMOS™, HITFET™,
HybridPACK™, INCA™, ISAC™, ISOFACE™, IsoPACK™, IWORX™, M-GOLD™, MIPAQ™, ModSTACK™,
MUSLIC™, my-d™, NovalithIC™, OCTALFALC™, OCTAT™, OmniTune™, OmniVia™, OptiMOS™,
OPTIVERSE™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, QUADFALC™, RASIC™, ReverSave™,
SatRIC™, SCEPTRE™, SCOUT™, S-GOLD™, SensoNor™, SEROCCO™, SICOFI™, SIEGET™,
SINDRION™, SLIC™, SMARTi™, SmartLEWIS™, SMINT™, SOCRATES™, TEMPFET™, thinQ!™,
TrueNTRY™, TriCore™, TRENCHSTOP™, VINAX™, VINETIC™, VIONTIC™, WildPass™, X-GOLD™, XMM™,
X-PMU™, XPOSYS™, XWAY™.
Other Trademarks
AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is
licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of
Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION.
MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of
Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc.,
USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™
of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™
of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™,
PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™,
WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2009-10-19
Application Note 3 V2.0, 2010-04

Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 How to Order Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Support for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Key Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Driver Board (6ED100HP1-FA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.4 DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Cooling Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Evaluation Driver Board for the HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Key Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Mechanical Dimensions of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Operation of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1 Switching Mode Power Supply (SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.2 Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.3 IGBT Switch-off Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.4 Maximum Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.5 Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.6 Short Circuit Protection and Clamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.7 Fault Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.8 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.9 DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 Switching Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Definition of Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8 Schematics, Layout and Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.2 Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.8.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 Logic Board for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1 External Connector (X1-SIG1) Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 Connector to the Driver Board (K1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4.1 Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4.1.1 Boot Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.1.2 Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table of Contents
4.6 Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.7 Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.8 Resolver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.9 Encoder Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.10 Hall Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.11 GMR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.11.1 GMR SSC Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11.2 GMR Encoder Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11.3 GMR Hall Sensor Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.12 Definition of Layers for the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.13 Schematics, Layout and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.13.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.13.2 Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.13.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.13.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

List of Figures
List of Figures
Figure 1 The Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2 Serial number in the suitcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 Block Diagram of Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 Dimensions of the Hybrid Kit for HybridPACK™1 - front view (all dimensions are in mm). . . . . . . 12
Figure 5 Dimensions of the Hybrid Kit for HybridPACK™1 - side view (all dimensions are in mm) . . . . . . . 12
Figure 6 HybridPACK™1 IGBT Six-Pack Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7 DC-Link Capacitor for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 Technical drawing of the DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 Example of Water Cooling Element for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 Water Cooling System Technical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11 Driver Board Mounted on the Top of the HybridPACK™1 Module. . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 External Connector on the Driver Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13 Dimensions of the Driver Board (in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14 PCB Mounting Stand-offs of HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15 Hybrid Kit for the HybridPACK™1 Evaluation Driver Board Block Diagram. . . . . . . . . . . . . . . . . . 20
Figure 16 Schematic of the Input Logic Block of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17 Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter) . . . 22
Figure 18 Temperature of Gate Resistors vs. Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19 Desaturation Protection and Active Clamping Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20 a) Short Circuit without Active Clamp (DC Voltage=71V, Voltage Overshoot=612V)
b) With Active Clamp Function (DC Voltage=280V, Voltage Overshoot=596V) 25
Figure 21 Fault Output of a Single Driver IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22 Fault Output During: a) Normal Operation b) Operation under Short Circuit . . . . . . . . . . . . . . . . . 26
Figure 23 Characteristics of the Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 24 Characteristics of the DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25 Copper and Isolation for Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26 Schematics Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 27 SMPS - Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28 External Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 29 Fault Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 30 Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 31 IGBT Driver - Bottom Transistor of Phase U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 32 IGBT Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 33 DC Voltage & Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 34 Assembly Drawing of the Driver Board (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 35 Assembly Drawing of the Driver Board (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 36 Driver Board - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 37 Driver Board - Layer-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 41 Driver Board - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 42 Logic Board for Hybrid Kit for the HybridPACK™1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 43 Block Diagram of the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 44 External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 45 Overvoltage and Wrong Polarity Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 46 HW Boot Configuration of TC1767 DIP-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 47 The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2) . . . . . . . 47
Figure 48 GMR SSC Interface - Proposal Using TLE5012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

List of Figures
Figure 49 Picture of Possible Physical Implementation of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 50 Definition of the Layers for the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 51 Schematics Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 52 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 53 JTAG Debug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 54 Connector (external) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 55 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 56 Resolver Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 57 Level Shifter for Adapting Logic Levels for Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 58 Level Shifter for Adapting Logic Levels for Resolver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 59 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 60 Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 61 Microcontroller TC1767 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 62 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 63 GMR SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 64 Temperature Sense of the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 65 Connector to the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 66 Assembly Drawing of the Logic Board (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 67 Assembly Drawing of the Logic Board (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 68 Logic Board - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 69 Logic Board - Layer-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 73 Logic Board - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

List of Tables
List of Tables
Table 1 Key Data of DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2 Key Data and Characteristic Values (Typical Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board . . . . . . . . . . . . . . 39
Table 4 External Connector Pin Assignment Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5 User Startup Modes for TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 6 Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7 Bill of Materials for Logic Board for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . 64

Introduction
1 Introduction
The Hybrid Kit for HybridPACK™1 shown in Figure 1 was developed to support customers during their first steps
in designing applications with HybridPACK™1 IGBT module. The following chapters provide a detailed description
of the main components and their functionality. This information is intended to enable the customers to copy,
modify and qualify the design for production, according to their specific requirements.
The boards Hybrid Kit for HybridPACK™1 Evaluation Driver Board (further refered as “Driver Board” ) and
Hybrid Kit for HybridPACK™1 Logic Board (further refered as “Logic Board”) provided by Infineon
Technologies are subjected to functional testing only.
Due to their purpose the system is not subjected to the same procedures regarding Returned Material Analysis
(RMA), Process Change Notification (PCN) and Product Withdraw (PWD) as regular products.
See Legal Disclaimer and Warnings for further restrictions on Infineons warranty and liability.
1.1 How to Order Hybrid Kit for HybridPACK™1

Hybrid Kit for HybridPACK™1 and Hybrid Kit for HybridPACK™1 Evaluation Driver Board (that can be
ordered separately) have Infineon Technologies SAP numbers and can be ordered via Infineon Sales Partners.
• SAP ordering number for Hybrid Kit for HybridPACK™1 : SP000806996
Information can also be found at the Infineon Technologies web page: www.infineon.com
Figure 1 The Hybrid Kit for HybridPACK™1

Introduction
1.2 Support for Hybrid Kit for HybridPACK™1

The new Hybrid Kits for HybridPACK™1 are labeled with a serial number inside the suitcase. That provides
better support for you and a better issue tracking for us. If you need any support with the hardware or software just
let us known your issue and your serial number and we will try to help you as best we can. Where you can find the
serial number inside the suitcase is shown on Figure 2.
Figure 2 Serial number in the suitcase

Design Features
2 Design Features
The Hybrid Kit for HybridPACK™1 is made up of two PCBs (Driver Board and Logic Board) mechanically and
electrically suitable to be used with an IGBT Module HybridPACK™1 (included), a DC-link capacitor and a cooler.
All these components build a complete main inverter for (H)EV applications up to 20kW.
Debug Logic Board

IGBT driver IGBT driver IGBT driver Connector
1ED020I12-FA 1ED020I12-FA 1ED020I12-FA
Watchdog Supply
IGBT driver IGBT driver IGBT driver

1ED020I12-FA 1ED020I12-FA 1ED020I12-FA Microcontroller
Supply EEPROM
C C TC1767
PWM Vdc, Temp
o o
Logic n Vdc meas.
n
n n I, U, V current
TempIGBT
e e measurement
SMPS DC-voltage c c Resolver
IGBT temp t FAULT t Level CAN / RS232
measurement interface
mesurement o Signals o Shifter Encoder / Sensor
(isolated)
r RST r
Resolver
6ED100HP1-FA Driver Board
Connector
IGBT module HybridPACK™1
Current U CAN RS232 A/D IO Supply

Current V
Current W
Encoder
Motor Resolver
3~
Sensor
Figure 3 Block Diagram of Hybrid Kit for HybridPACK™1

Figure 3 show the complete block diagram for the system and the following sections provide an overview of the
single components including main features, key data, pin assignments and mechanical dimensions.
2.1 Main Features

Complete main inverter for (H)EV applications up to 20kW.
• Automotive qualified IGBT module HybridPACK™1
– 650V/400A IGBT & Diode chip set
• Automotive qualified Driver IC 1ED020I12-FA
– Based on coreless transformer technology
– Up to 1200 V and 2A driving capability
– VCE sat - detection
• TriCore™ family 32-bit microcontroller TC1767: member of the AUDO FUTURE product family designed for
automotive applications
• Possibility of different motor position interfaces: encoder, resolver and GMR (Giant Magneto resistance))

Design Features
2.2 Dimensions
Figure 4 and Figure 5 shows the dimensions of a complete Hybrid Kit for HybridPACK™1.
Figure 4 Dimensions of the Hybrid Kit for HybridPACK™1 - front view (all dimensions are in mm)
Figure 5 Dimensions of the Hybrid Kit for HybridPACK™1 - side view (all dimensions are in mm)

Design Features
2.3 Key Components

For detailed technical information about the different components please refer to the different web pages on the
Infineon Internet.
2.3.1 Driver Board (6ED100HP1-FA)

The 6ED100HP1-FA is a six channel IGBT driver board, specially designed for the HybridPACK™1 IGBT module.
The main features and a detailed description of the board, including schematics and layout, can be found in
Chapter 3.
2.3.2 Logic Board

The Logic Board contains all necessary components for the control of the system. Furthermore it offers the
connections to the motor positioning system (encoder, resolver or GMR) and to the current measurement system.
For a detailed description of the board please refer to Chapter 3.
2.3.3 HybridPACK™1
(see Figure 6) is a power module designed for mild Hybrid Electrical Vehicle (HEV) applicationswith a maximum
supply voltage of 450 V and a power range up to 20kW. Designed for a junction operation temperature at 175°C,
the module accommodates a six-pack configuration of 3rd generation Trench-Field-Stop IGBT and matching
emitter controlled diodes and is rated up to 400A/650V. It is based on Infineon Technologies leading
TRENCHSTOP™ IGBT Technology, which offers lowest conduction and switching losses.
HybridPACK™1 is a baseplate module and can be screwed directly to a water- or air-cooled heat sink. For a
compact inverter design the driver stage PCB can easily be soldered on top of the module. All power connections
are realized with screw terminals. For detailed technical information of the module refer to the datasheet.
Figure 6 HybridPACK™1 IGBT Six-Pack Module

Design Features
2.3.4 DC-Link Capacitor

The power electronic capacitor B25655J4307K from the company Epcos AG (see Figure 7) is strongly
recommended (included). Table 1 shows the main features of the capacitor. For dimensions of the DC-Link
Capacitor have a look on Figure 8. Please refer to the Epcos datasheet for further details.
Figure 7 DC-Link Capacitor for HybridPACK™1
Table 1 Key Data of DC-Link Capacitor

Characteristics Maximum ratings Test Data
CR 300 µF ±10% Vs 600 V VTT 675V DC, 10 s
VR 450 V DC î 1.2 kA Rins ·C ≥ 10000 s
WR 30 Ws Is 4.8 kA tan δ (50 Hz) ≤ 8 · 10-4
Imax 80 A (dV/dt)max 4 V/µs
Lself 25 nH (dV/dt)s 16 V/µs
-4
tan δ0 2 · 10
Rs 0.8 mΩ
Climatic Category Design Data Mean Life Expentancy

0/110/21(IEC 68-1/2)
Tmin - 40 °C Dimensions l × w × h 140 × 72 × 50 mm tLD 15000h
Tmax + 110 °C Approx. weight 750 g αFQ 300fit
Max. Rel. Humidity ≤ 95% Impregnation Resin Filled
Tstg - 45 … +110°C Terminals Flat Copper
Clearance 9 mm
Values after Test Ca, IEC 68-2 Creepage distance 9 mm
(21 days, 40°C, 93% rel. humidity)
ΔC/C ≤ 5% Plastic Case
-4
Δtanδ ≤ 4 ·10
Rins ·C ≥ 3000s

Design Features
Figure 8 Technical drawing of the DC-Link Capacitor

Design Features
2.3.5 Cooling Element

For applications requiring higher power or higher operation temperature a usage of cooling element is
recommended. Figure 9 shows the low cost water cooling system that is included in the Hybrid Kit for
HybridPACK™1 which is screwed directly to HybridPACK™1 - Figure 10 shows the technical drawings of it. A
heat sink for air cooling is also a possible solution, but it will be larger than this water heat sink.
Figure 9 Example of Water Cooling Element for HybridPACK™1
Figure 10 Water Cooling System Technical Drawings

Evaluation Driver Board for the HybridPACK™1
3 Evaluation Driver Board for the HybridPACK™1
Figure 11 Driver Board Mounted on the Top of the HybridPACK™1 Module
3.1 Main Features

The Hybrid Kit for HybridPACK™1 Evaluation Driver Board offers the following features:
• Six channel IGBT driver
• Electrically and mechanically suitable for 600 V IGBT Module HybridPACK™1
• Includes DC/DC power supply
• Isolated voltage measurement
• Short circuit protection with toff < 6 µs
• Under Voltage Lockout of IGBT driver IC
• Positive logic with 5 V CMOS level for PWM and Fault signals
• One fault signal for each driver (LED signaling) and their combination for each leg
• Design according to IEC-60664-1

3.2 Key Data

All values given in the Table 2 (bellow) are typical values, measured at TA = 25 °C
Table 2 Key Data and Characteristic Values (Typical Values)

Parameter Value Unit
VSUPPLY – Voltage Supply +[8..18] V
VPWM – PWM Signals for Top and Bottom IGBT (Active High) 0 / +5 V
VFAULT – /FAULT Detection Output (Active Low) 0 / +5 V
IFAULT – Max. /FAULT Detection Output Load Current 10 mA
VRST – /RST Input (Active Low) 0 / +5 V
ISUPPLY – Supply Current Consumption (Idle Mode) (VSUPPLY=12V) 260 mA
VOUT – Drive Voltage Level 15/-8 V
IG – Maximum Peak Output Current ±10 A
PDC/DC – Maximum DC/DC Output Power of SMPS unit 30 W
1)
fS – Maximum PWM Signal Frequency 20 kHz
tPDELAY – Propagation Delay Time 200 ns
tPDISTO – Input to Output Propagation Distortion 15 ns
tMININ – Minimum Pulse Suppression for Turn-on and Turn-off2) 30 ns
VDESAT – Desaturation Reference Level 9 V
dmax – Maximum Duty Cycle 100 %
VCES – Maximum Collector – Emitter Voltage on IGBT 600 V
3)
TOP – Operating Temperature (Design Target) -40…+125 °C
TSTO – Storage Temperature (Design Target) -40…+125 °C
4)
VIORM – Maximum Repetitive Insulation Voltage (1ED020I12-FA Driver IC) 1420 VPEAK
5)
VISODRIVER – Maximum Insulation Test Voltage (1ED020I12-FA Driver IC) 4500 Vrms
VISOBOARD – Maximum Insulation Test Voltage (Evaluation Board) 2500 Vrms
1) The max. switching frequency for the HybridPACK™1module should be calculated separately. Limiting factors are: max.
DC/DC output power of 4.6W per channel and max. PCB board temperature measured around gate resistors of 75°C for
used FR4 material. For detailed information see Chapter 3.5.3
2) Minimum value tMININ given in 1ED020I12-FA IGBT driver datasheet
3) Maximum ambient temperature strictly depends on load and cooling conditions
4) 1ED020I12-FA datasheet - complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01.Basic Insulation
5) 1ED020I12-FA datasheet - complies with UL 1577
3.3 External Connector Pin Assignment

Figure 12 shows the pin assignment for the external connector (K1) on the Driver Board. The connector is a
MMS-112-01-L-DV from Samtec, proper matching parts are the TW series for PCB connection or the TCMD series
for cable connection. It includes all necessary signals to get the board into operation, that is, supply, control and
monitoring.

1 2V
1 2V
K1
1 2
3 1 2 4 GND_DIG
5 3 4 6 GND_DIG V ANA5 0
G ND_DIG +5.0 V
7 5 6 8
9 7 8 10
V DC 11 9 10 12 T EM P_ IGB T
G ND_A NA1
13 11 12 14 RST _ INn
FLT Wn 15 13 14 16 P WM WT
17 15 16 18 P WM WB
FLT V n 19 17 18 20 P WM VT
21 19 20 22 P WM VB
FLT Un 23 21 22 24 P WM UT
FLT n 23 24 P WM UB
M MS -1 1 2-0 1 -L -DV
Figure 12 External Connector on the Driver Board

Pins 1 to 6 provide the power supply. The Driver Board must be supplied with an external regulated DC power
supply. The input voltage must be kept between 8 V and 18 V and the current consumption will depend on different
factors (Logic Board, PWM frequency, etc.). Pins 7-8 provide 5 V analogue power supply which can be used to
supply different devices in case of using the Hybrid Kit for HybridPACK™1 as driver board in an inverter such as
current measurement, ADC or the motor interface.
To pins 9, 10, 15 and 19 are connected monitoring signals: DC-link voltage measurement and temperature of the
three different phases inside of the IGBT module.
Pins 12, 13, 14, 16, 17, 18, 20, 21, 22 and 23 contain the logic signals for controlling the 6 drivers on the board,
that are the PWM signals, Fault detection and Reset signal.
3.4 Mechanical Dimensions of the Driver Board

The Driver Board has placed components on both sides of the PCB. The maximum height of the Parts and the
dimensions of the PCB is shown in Figure 13
Figure 13 Dimensions of the Driver Board (in mm)

The Driver Boards should be fastened by self taping screws and soldered to the auxiliary connectors on top of the
IGBT module. The contact joints (solder points) between PCB and module auxiliary contacts should be
mechanically relieved in order to disburden the solder connection as far as possible. Relieve of the contact points
is carried out by mounting the PCB directly onto the module at the ten mounting stand-offs (see Figure 14) using
self-tapping screws (thread forming with 2.5mm diameter) or similar assembly material. The screws should be
mounted in the sequence showed in Figure 14.
Figure 14 PCB Mounting Stand-offs of HybridPACK™1
3.5 Operation of the Driver Board

Figure 15 shows the block structure of the Driver Board. The following chapter describes these blocks in detail.
15V/-8V
15V/-8V
DC LINK
VOLTAGE
MEASUREMENT
SMPS IGBT IGBT IGBT

15V/-8V
15V/-8V (x3) Driver Driver Driver
UT VT WT
5V
5V 5V 5V
RESET
FAULT U
LOGIC
FAULT V
FAULT W
5V 5V 5V
IGBT
FAULT W
FAULT U
FAULT V
FAULT
RESET
MODUL
IGBT IGBT IGBT TEMP
Driver Driver Driver
UB VB WB
12V
INPUT
LOGIC
Connector (PWM)
IGBT MODUL TEMPERATURE

DC LINK VOLTAGE MEASUREMENT
Figure 15 Hybrid Kit for the HybridPACK™1 Evaluation Driver Board Block Diagram

3.5.1 Switching Mode Power Supply (SMPS)

The Driver Board has an integrated DC/DC converter which generates the required secondary isolated
unsymmetrical supply voltage of +15/-8V. Top and bottom driver voltages are independently generated by using
one unipolar input voltage of 12 V.
An additional supply voltage (5V) is generated and forwarded to the external connector (K1) so it can be used to
supply external components in the system (current measurement, motor interface, etc.)
For circuit details please refer to Figure 27.
3.5.2 Input Logic

The Driver Board is a dedicated system for a six-pack HybridPACK™1 IGBT configuration - therefore it is
necessary to use 6 separated PWM signals. The schematics on Figure 16 shows the input logic block with +5V
positive logic. The block is made up of RC filters for each PWM signal in order to reduce noise. Additionally these
signals are pulled-down in order to avoid unwanted switching-on of the drivers. Please have in mind that the Hybrid
Kit for HybridPACK™1 does not provide dead time automatically (meaning that hardware alone provides no dead
time) - it is up to the user to generate the PWM signals with the correct dead time (by means of software).
R88
PWM _WT
100 R C85 R89
1 00p F/100 V /COG 1 5k
GND_DIG1
R90 G ND_DIG1
PWM _WB
100 R C86 R91
1 00p F/100 V /COG 1 5k
GND_DIG1
R92 G ND_DIG1
PWM _VT P WM WT
100 R C87 R93 P WM WB
1 00p F/100 V /COG 1 5k
P WM VT
GND_DIG1 P WM VB
R94 G ND_DIG1 P WM UT
PWM _VB
P WM UB
100 R C88 R95
1 00p F/100 V /COG 1 5k
GND_DIG1
R96 G ND_DIG1
PWM _UT
100 R C89 R97
1 00p F/100 V /COG 1 5k
GND_DIG1
R98 G ND_DIG1
PWM _UB
100 R C90 R99
1 00p F/100 V /COG 1 5k
GND_DIG1
G ND_DIG1
Figure 16 Schematic of the Input Logic Block of the Driver Board
3.5.3 IGBT Switch-off Behavior

Due to the stray inductances of the system a voltage overshoots occur during the switching-off the IGBT. Such
overshoots are added to the DC-link voltage, so that the maximum blocking voltage of the IGBT or capacitor might
be exceeded causing damages in both components (DC link capacitor and IGBT module). In order to avoid such
risks an active clamping circuit is used (see Chapter 3.5.6).
Without such protection methods the maximum current would be limited by the DC-link voltage and the voltage
overshoots at switching-off. The voltage overshoots can be minimized by increasing the gate resistor, which will
reduce the di/dt value. Figure 17 shows the maximal switch-off current at different DC-link voltages for a different
values of the gate resistor. These results were obtained with the DC-link capacitor described in Chapter 2.3.4.

900
800
700
600
500
Ic (A)
400
Ic nominal
300
200
100
0
0 50 100 150 200 250 300 350 400 450
Rgoff=2.2Ohm Rgoff=3.8Ohm Rgoff=5.6Ohm Icnom
DC-Link voltage (V)

Figure 17 Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter)
3.5.4 Maximum Switching Frequency

The IGBT switching frequency is limited by the available power and by PCB temperature. According to theory the
power losses generated in the gate resistors are a function of a gate charge, voltage step at the driver output and
switching frequency. The energy is dissipated mainly through the PCB and raises the temperature around the gate
resistors. When the available power of the DC/DC converter is not exceeded, the limiting factor for the switching
frequency is the absolute maximum temperature for the FR4 material. The allowed operation temperature is
105 °C.
Generally the power losses generated in the gate resistors can be calculated according to Equation (1):
P dis = P RGext + P RGint = ΔV out ⋅ f S ⋅ Q ge (1)
In Equation (1) f S represents the switching frequency, ΔV out represents the voltage step at the driver output,
P dis is the dissipated power, Q ge is the IGBT gate charge value corresponding to +15V/-8V switching operation.
This value can be approximately calculated from the datasheet value by multiplying it by 0.77, that is
Q ge = 3.31μC . Therefore the maximum frequency limited by the available power will be:
f Smax = 4.6 W ⁄ ( 23V ⋅ 3.31μC ) = 60.4 kHz
Figure 18 shows experimentally determined board temperature dependencies with switching frequency (at 25 °C
ambient temperature). From Figure 18 it can be concluded that the maximum switching frequency is limited by
PCB temperature.

75,0
70,0
gate resistor temperature (°C)
65,0
60,0
55,0
50,0
45,0
40,0
35,0
1,0 5,0 9,0 13,0 17,0 21,0 25,0 29,0 33,0 37,0 41,0 45,0 49,0
switching frequency (kHz)
Figure 18 Temperature of Gate Resistors vs. Switching Frequency
3.5.5 Booster
Two transistors per driver IC are used to amplify the driver ICs signals. On this way the driving IGBTs are supplied
with sufficient current even if driver ICs alone can’t deliver enough current. One NPN transistor is used for
switching the IGBT on and another PNP transistor for switching the IGBT off.
The transistors are dimensioned to have enough peak current to drive HybridPACK™1 modules. Peak current can
be calculated like in Equation (2):
ΔV out
I peak = ----------------------------------------------------- (2)
R Gint + R Gext + R Driver
For circuit details please refer to Figure 31.
3.5.6 Short Circuit Protection and Clamp Function

The short circuit protection of the Driver Board basically relies on the detection of a voltage level higher as 9 V on
the DESAT pin of the 1ED020I12-FA driver IC and the implemented active clamp function. Thanks to this operation
mode, the collector-emitter overvoltage, which is a result of the stray inductance and the collector current slope,
is limited. Depending on the stray inductance, the current and the DC voltage the voltage overshoot during turn
off changes. Figure 19 shows the parts of the circuit needed for the desaturation function and the active clamping
function.

D5_ UB D4_ UB
VN
VP
ZLL S 10 0 0 ZLL S 10 0 0
C13 _ UB
1 00 p F/1 00 V /CO G R28 _ UB D6_ UB
G ND COL
COL
1K
G F1 M D3_ UB
G ND S MCJ4 4 0A
C15 _ UB C16 _ UB
4 u7 /25 V /X7 R 4 u7 /25 V /X7 R
C17 _ UB
1 00 n /5 0 V/X 7 R
D9_ UB
U4 ZLL S 10 0 0 D1_ UB
17 6 T 1_ UB 2 1 R0 / S M P-1 R0 0 -1 .0 E S1 D
16 /RS T V CC2 1 R0 / S M P-1 R0 0 -1 .0
/FL T 3 1 0 R2 2 / S MP -R2 2 0-1 .0
DES AT R33 _ UB R32 _ UB R38 _ UB
R31 _ UB
13 3
IN+ 4 7R_ 08 0 5_ T K1 00 _ 1% _ 0.1 25 W
7
O UT ZXT N2 0 10 Z G
14 8 T 2_ UB 3
IN- CLA MP R30 _ UB R36 _ UB R37 _ UB
5 1 1 R0 / S M P-1 R0 0 -1 .0
15 T LS ET 1 R0 / S M P-1 R0 0 -1 .0
RDY 4 G ND 2 0 R2 2 / S MP -R2 2 0-1 .0
18 G ND2
V CC1 ZXT P2 0 12 Z
12 1
11 G ND1 V EE 2 2 R35 _ UB 0R
19 G ND1 V EE 2 9
20 G ND1 V EE 2 10 C21 _ UB
G ND1 V EE 2 C20 _ UB 4 u7 /25 V /X7 R
C19 _ UB 4 u7 /25 V /X7 R G ND
G ND
1 ED0 20 I12 FTA 3 3p F/1 0 0V /COG
VN
D10 _ UB
MM 3 Z9 V 1T 1 G
C23 _ UB
1 00 n /5 0 V/X 7 R
G ND
Figure 19 Desaturation Protection and Active Clamping Diodes

In the case of a short circuit the collector-emitter saturation voltage will rise and the driver detects the short circuit
occurrence - to protect the IGBT it has to be turned off. As a consequence of IGBT turn-off process there will occur
an voltage overshoot due to the stray inductance of the module and the DC-link. This voltage overshoot has to be
lower than the maximum IGBT blocking voltage. Therefore the Driver Board has an active clamping function
whereby the clamping will increase the voltage for the booster and also increase the voltage directly on the gate.
The typical turn-off waveform under short circuit condition and room temperature of a HybridPACK™1 module
without any additional protective functions is shown in Figure 20 a). Typical waveform under short circuit condition
with active clamp function at room temperature is shown in Figure 20 b). As it can be seen, the voltage overshoot
without active clamping at a DC voltage of 71 V is close to the maximum IGBT blocking voltage of HybridPACK™1
(650V), which could damage the devices. With active clamping the voltage overshoot can be reduced and the DC
voltage increased without damaging the IGBT module (at 280 V DC voltage can be observed voltage overshoot
of approximately 596 V, Figure 20 b). In design are implemented 440 V clamping diodes. The level of the
clamping voltage must be adjusted depending on the application.

Figure 20 a) Short Circuit without Active Clamp (DC Voltage=71V, Voltage Overshoot=612V)
b) With Active Clamp Function (DC Voltage=280V, Voltage Overshoot=596V)
3.5.7 Fault Output

When a short circuit occurs the voltage VCE is detected by the desaturation protection of the 1ED020I12-FA and
the IGBT is switched off. The fault is reported to the primary side of the driver as long as there is no reset signal
applied to the driver. The fault signal (/FLT) is active low - the schematic of design implemented in Driver Board
can be seen on Figure 21.

V DIG 50
+5.0 V
R29 _ UB
4 k7
U4
17 6
RST n 16 /RS T V CC2
C14 _ UB /FLT 3
DES AT
4 70 p F/5 0 V/X 7R
13
IN+ IN+ 7
14 O UT 8
IN- IN- CLA MP
V DIG 50
+5.0 V 5
15 T LS E T
RDY 4
18 G ND2
R34 _ UB V CC1
4 k7 12 1
11 G ND1 V EE 2 2
19 G ND1 V EE 2 9
FLT n 20 G ND1 V EE 2 10
V DIG 50 G ND1 V EE 2
+5.0 V
1 ED0 20 I12 FTA
C22 _ UB
1 00 n/50 V/X 7 R
G ND_DIG1
G ND_DIG1
Figure 21 Fault Output of a Single Driver IC
Short circuit occurs
Ready signal
Fault signal
UGE
a) b)
Figure 22 Fault Output During: a) Normal Operation b) Operation under Short Circuit
The fault signal (/FLT) will be in low state if a short circuit occurs until /RST signal is pulled down.
On the Driver Board each of the drivers has its own fault signal (FAULT_UTn, FAULT_UBn, FAULT_VTn,
FAULT_VBn, FAULT_WTn, FAULT_WBn). As it can be seen in Figure 29, a LED will warn in the case of a
DESAT-FAULT condition at a IGBT. The fault signals are connected to a logic circuit and the output of this are a
combined fault and one fault for each phase, which is forwarded to the external connector (K1).
3.5.8 Temperature Measurement

The IGBT module HybridPACK™1 includes one integrated NTC (Negative Temperature Coefficient) sensor which
simplify the thermal measurements in inverters significantly.
The NTC is located on the same ceramic substrate together with the IGBT and diode chips for the middle phase.
The module is filled with silicon gel for isolation purpose and under normal operation conditions the requirements
for isolation voltages are met. The NTC isolation capability is tested with 2.5kV AC in final test for 1 minute for
100% of module production.

The NTC is connected to the main connector K1 (pin 10) by means of the circuit showed in Figure 33. Figure 23
shows the relationship between IGBT module base plate temperature of the three phases and output voltage of
IGBT module temperature block (TEMP_IGBT, K1.10)
4,5
4,0
Temp_IGBT (V)
3,5
3,0
2,5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
module temperature (°C)

Figure 23 Characteristics of the Temperature Measurements
Note: This temperature measurement is not suitable for the short circuit or short term overload detection and
should be used only for the module protection against long term overload or malfunction of the cooling system.
3.5.9 DC Voltage Measurement

On the Hybrid Kit for HybridPACK™1 the voltage at the DC link is measured by means of a isolation amplifier
which offers the necessary galvanic isolation (see Figure 33).
The output of this circuit is connected to the external connector (Vdc, K1.9). Figure 24 shows the relationship
between DC link voltage and Vdc output signal.

4500
4000
y = 7,2171x + 1294,4
3500
3000
VDC (mV)
2500
2000
1500
1000
500
0
0 50 100 150 200 250 300 350 400
DC-Link Voltage (V)

Figure 24 Characteristics of the DC Voltage Measurement
3.6 Switching Losses

Switching losses can be different comparing to the values given in the HybridPACK™1 IGBT module datasheet.
Main reason for this discrepancy is that switching voltages used on the Driver Board (+15V for turn-on and -8V for
turn-off) differ from HybridPACK™1 characterisation switching voltages (+15V/-15V).
Turn-on losses are expected to be close to the values of the datasheet of HybridPACK™1, but as mentioned, this
will be different for the turn-off losses. In general the turn-off losses depend on the stray inductances of the DC-
link and increase linear with the DC-link voltage. In the case of the Driver Board the turn-off losses do not increase
linearly because of the fact that the active clamping feature increases the turn-off losses due to decrease of the
di/dt.
3.7 Definition of Layers of Driver Board

The Driver Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 25.
1 Copper 1 Isolation
2 1: 35 µm 2 1-2: 0.5 mm
2: 35 µm 2-3: 0.5 mm
3 3
3-4: 0.5 mm
3: 35 µm
4 4 4-5: 0.5 mm
4: 35 µm
5
5-6: 0.5 mm
5
5: 35 µm
6 6
6: 35 µm
Figure 25 Copper and Isolation for Layers of Driver Board

3.8 Schematics, Layout and Bill of Material

To meet the individual customer requirements and to make the Driver Board for the HybridPACK™1 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
are included in this chapter.
3.8.1 Schematics
IGB T _DRIV E R_UT V P1 5 _UTV N8_ UT IGB T _M ODULE

+15 .0 V -8 .0V
IN+ VP
IN- COL COL UT
S MP S RST n G G UT
FLT n G ND G NDUT
1 2V in VN G ND_UT
IGB T _DRIV E R
IGB T _DRIV E R_UB V P1 5 _UB V N8_ UB

+15 .0 V -8 .0 V
IN+ VP
S MP S IN- COL
RST n G G UB
FLT n G ND G NDUB
VN G ND_UB
IGB T _DRIV E R
IGB T _DRIV E R_VT V P1 5 _V T V N8_ VT

+15 .0 V -8 .0 V
CONNE CTO R IN+ VP

INP UT_L OG IC IN- COL COL VT
RST n G G VT
P WM UT P WM _UT P WM UT FLT n G ND G NDVT
P WM UB P WM _UB P WM UB VN G ND_V T
P WM VT P WM _V T P WM VT
P WM VB P WM _V B P WM VB IGB T _DRIV E R
P WM WT P WM _WT P WM WT
12V P WM WB P WM _WB P WM WB
G ND_DIG V P1 5 _V B V N8_ VB
INP UT_L OG IC IGB T _DRIV E R_VB
+15 .0 V -8 .0 V
IN+ VP
TEMP_IGBT
IN- COL
RST_INn
G ND_DIG1
RST n G G VB
FLTWn
FLTUn
FLTVn
FLTn
FLT n G ND G NDVB
VDC
VN G ND_V B
CONNE CTO R IGB T _DRIV E R
IGB T _DRIV E R_WT V P1 5 _WT V N8_ WT

+15 .0 V -8 .0 V
IN+ VP
IN- COL COL WT
RST n G G WT
FLT n G ND G NDWT
VN G ND_WT
IGB T _DRIV E R
IGB T _DRIV E R_WB V P1 5 _WB V N8_ WB

+15 .0 V -8 .0 V
IN+ VP
POWER_VCC
IN- COL
FAUL T_ L OGIC RST n G G WB
FLT n G ND G NDWB
Temp0
Temp1
VN G ND_WB
IGB T _DRIV E R
RST _ INn
FAUL T_ UT n IGB T _M ODULE
FAUL T_ VT n
FAUL T_ Un FAULT_ WT n
FAUL T_ Vn
FAUL T_ Wn FAUL T_UB n
FAUL T_ n FAUL T_ VB n
FAULT_ WB n
RST n M EA SURE
FAUL T_ L OGIC T em p0
T em p1
T EM P_IGB T
V DC P OWER_ VCC
M EA SURE
Figure 26 Schematics Block Overview

V P1 5_UT
D4 +15 .0V
E S1 A D5 C893
4 u7 /25V /X7R
+ C89 4 1SM B59 29B T3 G
2 2u /35 V /T4 91 V z=1 5V
UT_PS
1k6
1k6
1k6
C895 G ND_UT
4 u7 /25V /X7R V N8 _UT
R143
R144
R145
-8.0 V
V P1 5_WT
D6 +15 .0V
WT _ PS
1 2V i n E S1 A D7 C89 6
4u7 /25 V /X7 R
T F1 + C89 7 1 SM B5 929 B T3G
11 2 2u /35 V /T49 1 V z= 1 5V
G ND_WT
4u7/25V/X7R
1k6
1k6
1k6
C89 8
V N8 _WT
R146
R147
R148
Q4 -8.0V V P1 5 _V T
4u7F/50V/X7R/C1210C475K5RACTU
IPD9 0P 0 3P 4L-04 +15.0V
12 D9
D8 3 V T_ PS
1 2V _ PROT
4u7/25V/X7R4u7/25V/X7R
E S1A D10 C89 9
47uF_25V_SVPD/ASVPD
B ZV 5 5-C13
R14 9 D11 + C900 1 SM B5 9 29 B T3 G
10K 1 SM B3 0AT 3 G 2 2u/35 V /T4 9 1 V z= 15V
4
1 7
1k6
1k6
1k6
C90 1G ND_V T
V N8_ VT
C902
C903
R150
R151
R152
+ + D12 -8.0 V
G ND_DIG1 G ND_DIG1 E S1 A
V P15 _V B
D13 +15 .0V
G ND_DIG1 G ND_DIG1 8 V B_ PS
D14 13
4u7/25V/X7R4u7/25V/X7R
E S1 A D15 C904
C90 5 + C90 6 1 SM B5 929B T3G

R15 3 1 00 n F/100 V /X7 R 2 2u /35 V /T4 9 1 Vz= 1 5V
1 0K 1 SM B5 9 29B T3 G
IC2 2 2 14
1k
1k6
1k6
G ND_DIG1 C907 G ND_V B
8 5 V N8 _VB
V in
R155
R156
R157
R154 8 0K 6 -8.0 V
7 R19 7 Q5
2 FA/S D 6 1 V P1 5 _WB
3 COM P DR 7 R5_ 08 0 5_ T K1 00 _ 1% _0.1 25 W D16 +15 .0V
4 FB 1 3 WB _PS
4u7/25V/X7R 4u7/25V/X7R
5 A GND Isen 6
19K6
UNDER_ VO L _DET E CT ION C90 8 IPD1 44 N06 NG

P GND
3
10n/50 V /X7 R 9 E S1 A D17 C909

R158
T2 L M3 478 MM
22n/50V/X7R
1 2V _ PROT 1 B SS 13 8 N G ND_DIG1 + C91 0 1 SM B5 929B T3G

P OWER_ UP
C911
2 2u /35 V /T4 9 1 Vz= 1 5V

2
D32
1k6
1k6
1k6
G ND_DIG1 C912 G ND_WB
B ZV 5 5-C18 R15 9 10 V N8_ WB
1uF/50V/C1206F105K5RACTU
UNDER_ VO L _DET E CT ION 15
R160
R161
R162
5 9K -8.0 V
R163
4k75
V P15 _UB
G ND_DIG1 G ND_DIG1 D18 +15 .0V
10n/50V/X7R
UB_ PS
0R025
L _47 u_ 1 A_E PCOS _ B8 2 47 2 P
4u7/25V/X7R4u7/25V/X7R
100nF/50V/C0805F104K5RACTU
16
C914
R164
L1 E S1A D19 C91 5

C913
C917
G ND_DIG1
470pF/10V/X7R
1uF/50V/C1206F105K5RACTU
C916
G ND_DIG1 T ra fo _p l an ar_sm ps_ 8W_HP 1_ o pt + C91 8 1 SM B5 9 29 B T3 G

G ND_UB
C919
R16 5 G ND_DIG1 G ND_DIG1 2 2u /35 V /T4 9 1 Vz= 15V

1K5 / 1 % / 100 p pm
1k6
1k6
1k6
C92 0 G ND_UB
V N8_ UB
IC1 R16 9
R167
R166
R168
G ND_DIG1 GND_DIG1 -8.0 V
8 4 C921 11K / 1 % / 100 p pm V DIG 50
7 VS FB 5 2 20 n F/C08 0 5F2 24K 5RA C +5.0 V
3 EN B DS
22nF/50V/X7R
680R/PRC221 1W TK100 1%
COM P R17 0
GND_EP
L _4 7 u_ 1A_ E PCOS _ B8 2472 P V DIG 50 V ANA5 0

100uF/12.5V/A700X107M12RATE015
6
C922
+5.0 V 0 R / SM K-R0 00 +5.0 V
680R/PRC221 1W TK100 1%
220nF/220nF/C0805F224K5RAC
1 B UO 2 L2 D21 R171 R17 2

S YNC G ND L 3 805
C924
+ 1 206
22K / 1% / 100ppm
C923
T LE 8 366 EV R_S MK -R00 0
100n/50V/X7R
+
9
D31 C93 6 E S1 A o pt MURAT A _B LM 21P 2 21S N

2 2u /16 V /X7 R G ND_DIG1 + +
R173
R174
S L23 _3 0 V_ 2A_ SM B C92 5 C92 6 C927 C928
2 2u /16 V /X7 R
R175
2 2u /16 V /X7 R 1 00 n/5 0V/X 7 R

G ND_DIG1
G ND_DIG1
G ND_DIG1 G ND_DIG1 G ND_DIG1 R17 6 o pt

GND_DIG1 G ND_A NA1
G ND_DIG1
Figure 27 SMPS - Power Supply
1 2V
1 2V
K1
1 2
3 1 2 4 GND_DIG
5 3 4 6 GND_DIG V ANA5 0
G ND_DIG +5.0 V
7 5 6 8
9 7 8 10
V DC 11 9 10 12 T EM P_ IGB T
G ND_A NA1
13 11 12 14 RST _ INn
FLT Wn 15 13 14 16 P WM WT
17 15 16 18 P WM WB
FLT V n 19 17 18 20 P WM VT
21 19 20 22 P WM VB
FLT Un 23 21 22 24 P WM UT
FLT n 23 24 P WM UB
M MS -1 1 2-0 1 -L -DV
Figure 28 External Connector

V DIG50 RST n RST _INn

+5.0 V
V DIG50
R17 7 +5.0 V
1 5K_ 060 3_ T K1 00 _ 1%_ 0.0 63 W R17 8
1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W
FAUL T_ UB n
6
C92 9 R17 9
V DIG50 1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p t D22 A 4 K7 _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
4
+5.0 V BAS 16ST 6B
1
10k
GND_DIG1 5
FAUL T_ Un
10k
6
R18 0 BCR10P N 3 T 6A
6
1 5K_ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
D22 B 2 10k D30 A
R18 1
BAS 16S B AS16 S
1
10k 1
FAUL T_ UT n BCR10 PN
1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W C93 0
1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p t
V DIG 50 GND_DIG1
+5.0 V
GND_DIG1
R18 2
1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.063 W VDIG50
+5.0 V
R18 3
FAUL T_ VB n
4
1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W C93 1 R18 4
1 0n F_0 4 02_ X7 R_50 V_ CER_oD22
pt C 4 K7 _ 06 0 3_ T K1 00 _ 1% _ 0.0 63 W
4
VDIG50 B AS16 S T 7B
3
+5.0 V 10k
5
FAUL T_ Vn
GND_DIG1 10k
6
D23 A B CR10 PN 3 T 7A
R18 5 B AS16 S
1 5K _ 06 0 3_ T K1 00 _ 1% _ 0.0 63 W 2 10k
R18 6
5
10k 1
FAUL T_ VT n BCR10P N D30 B
VDIG50 1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W C93 2 BAS 16S
2
+5.0 V 1 0n F_0 4 02_ X7 R_50 V_ CER_o p t
G ND_DIG1
R18 7 GND_DIG1 VDIG50

1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W +5.0 V
R18 8
FAUL T_ WBn VDIG 50 R18 9
5
+5.0 V 1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W C93 3 4 K7 _06 0 3_ T K1 00 _ 1%_ 0.0 63
4
1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p tD23 B T 8B
BAS16 S 10k
2
5
FAUL T_ Wn
R19 0 10k
6
1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W GND_DIG1 D23 C B CR10 PN 3 T 8A
B AS16 S
R19 1 2 10k
4
FAUL T_ WT n 10k 1 D30 C
1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W C93 4 BCR10P N BAS 16 S
3
1 0n F_0 4 02_ X7 R_50 V_ CER_o p t
VDIG 50 V DIG 50 VDIG50 V DIG 50
VDIG 50 +5.0 V VDIG50 +5.0 V VDIG50 +5.0 V +5.0 V G ND_DIG1
R19 8
+5.0 V +5.0 V +5.0 V
T 3A T 3B T 4A T 4B T 5A T 5B GND_DIG1 FAUL T_ n
BCR183S BCR18 3 S BCR18 3 S BCR18 3 S BCR18 3 S B CR18 3 S
1
10k 10k 10k 10k 10k 10k 4 K7_ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W

2 5 2 5 2 5
10k 10k 10k 10k 10k 10k
6 <PACKAGE> 3 6 <PACKAGE> 3 6 <PA CKAGE > 3
<PA CKAGE > <PACKA GE> <PACK AGE>
R25 R19 2 R19 3 R194 R19 5 R19 6

2 20 R_06 03 _ TK10 0 _1 % _0 .06 3 W 2 20 R_0 6 03 _ TK100 _1 % _0 .06 3 W 2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W 2 20 R_0 6 03 _ TK10 0 _1 % _0 .06 3W 2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W 2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W
D24 D25 D26 D27 D28 D29
GND_DIG1 GND_DIG1 GND_DIG1 G ND_DIG1 GND_DIG1 GND_DIG1
Figure 29 Fault Logic
R88
PWM _WT
100 R C85 R89
1 00p F/100 V /COG 1 5k
GND_DIG1
R90 G ND_DIG1
PWM _WB
100 R C86 R91
1 00p F/100 V /COG 1 5k
GND_DIG1
R92 G ND_DIG1
PWM _VT P WM WT
100 R C87 R93 P WM WB
1 00p F/100 V /COG 1 5k
P WM VT
GND_DIG1 P WM VB
R94 G ND_DIG1 P WM UT
PWM _VB
P WM UB
100 R C88 R95
1 00p F/100 V /COG 1 5k
GND_DIG1
R96 G ND_DIG1
PWM _UT
100 R C89 R97
1 00p F/100 V /COG 1 5k
GND_DIG1
R98 G ND_DIG1
PWM _UB
100 R C90 R99
1 00p F/100 V /COG 1 5k
GND_DIG1
G ND_DIG1
Figure 30 Input Logic

D5_ UB D4_ UB
VN
VP
ZLL S 10 0 0 ZLL S 10 0 0
C13 _ UB
1 00 p F/1 0 0V /CO G R28 _ UB D6_ UB
G ND COL
COL
1K
G F1 M D3_ UB
V DIG 50 G ND S MCJ4 4 0A
+5.0 V C15 _ UB C16 _ UB
4 u7 /2 5V /X7 R 4 u7 /2 5V /X7 R
C17_ UB
R29 _ UB 1 00 n /50 V/X 7 R
4 k7 D9_ UB
U4 ZLL S 10 0 0 D1_ UB
17 6 T 1_ UB 2 1 R0 / S M P-1 R0 0 -1 .0 E S1 D
RST n 16 /RS T V CC2 1 R0 / S M P-1 R0 0 -1 .0
C14 _ UB /FLT 3 1 0 R2 2 / S MP -R2 2 0-1 .0
DES AT R33 _ UB R32 _ UB R38 _ UB
4 70 p F/5 0 V/X 7R
13 R31 _ UB 3
IN+ IN+ 7
14 O UT 8 G
IN- T 2_ UB 3
V DIG 50 IN- CLA MP R30 _ UB R36 _ UB R37 _ UB
+5.0 V 5 1
15 T LS E T
RDY 4 G ND 2
18 G ND2
R34 _ UB V CC1
4 k7 12 1
11 G ND1 V EE 2 2 R35 _ UB 0R
19 G ND1 V EE 2 9
FLT n 20 G ND1 V EE 2 10 C21 _ UB
V DIG 50 G ND1 V EE 2 C20 _ UB 4 u7 /2 5V /X7 R
+5.0 V 4 u7 /2 5V /X7 R G ND
G ND
1 ED0 20 I12 FTA C19 _ UB
3 3p F/10 0 V/COG
VN
C22 _ UB D10 _ UB
M M3 Z9 V 1T 1G
1 00 n /50 V/X 7 R C23 _ UB
1 00 n /50 V/X 7 R
G ND_DIG1
G ND
G ND_DIG1
Figure 31 IGBT Driver - Bottom Transistor of Phase U
P OWER_ VCC
COL WT COL VT COL UT
G WT G VT GUT
C79 R82 C80 R83 C81 R84
1 0n /5 0V /X7 R 1 0K 1 0n/5 0V /X7 R 1 0K 1 0n /5 0V /X7 R 1 0K
G NDWT G NDVT GNDUT
Q 3A Q 3B Q3C
P ACKA G E = 1 P ACKA G E = 1 P ACKA G E = 1
P 1
6 25 22
7 9 11
8 10 12
24
T em p1
P ha se_ W 3 P ha se_ V 4 P ha se_ U 5

23
T em p0
13 15 17
14 16 18
N 2 19 N
FS4 0 0R0 6A 1 E3 _o p tFS4 0 0R0 6A 1 E3 _o p tFS4 0 0R0 6A 1 E3 _o p t
G WB G VB G UB
C82 R85 C83 R86 C84 R87
1 0n /5 0V /X7 R 1 0K 1 0n/5 0V /X7 R 1 0K 1 0n /5 0V /X7 R 1 0K
G NDWB G NDVB G NDUB
Figure 32 IGBT Module

P OWER_ VCC
R4 4 K0 2 / 0 .1%
R1 R2 R3
5 90 K 5 90 K 5 90 K
HV_ VB_ VD
C1 3 30 p F/5 0 V/COG
R5 R6 R7
V ANA5 0 5 90 K 5 90 K 5 90 K
+5.0 V V ANA5 0 +5V V B V B_ 1 3
+5.0 V +5V
C11 3 R8
1 0n /5 0V /X7 R 3 K9
C2 C3
1 00 n /50 V/X7 R 500V->199mV
1 00 n /50 V/X 7 R V B_ 1 2
1
G ND_A NA1 IC3
8
IC4 R15 A CP L -7 8 2T R9 R10
Vdd2
Vdd1
2 K / 0.1 % 3 9R 1 58 R
V+
2 G ND_ANA1 G ND_V B
1 IN-A 7 2 V B_ 1 1
V DC OUT A 3 O UT +IN+
R12
IN+A 2 K / 0.1 % 6 3 C5 GND_V B
R11 C6 O UT - IN- 1 0n /5 0V /X7 R
GND2
GND1
1 0K / 0 .1 % p /50 V/C0 G
1 50
R12 9 o pt
6
7 IN-B
T EM P_ IGB T
4
OUT B 5 G ND_A NA1
IN+B G ND_A NA1
V-
G ND_V B
AD8 5 52 A RZ
4
G ND_A NA1 G ND_V B
G ND_A NA1 V ANA5 0

+5.0 V
R13 6 0 R
R13 7
1 0K 5 /1 %
T em p1
C11 6
T em p0
V P1 5 _V B +5V V B
+15 .0 V +5V
IC6 1 u/2 5 V/X7R
R130
10K5/1%
10n/50V/X7R
3 4 C12 2
I Q
C121
1 0n /5 0V /X7 R
C89 1 1 2 C93 5
1 00 n /50 V/X 7 R INH G ND 5
G ND 4 u7 _ X7 R_1 6 V_ CE R/C1 20 6 F4 7 5K 4 RA
T LE 4 29 6 -2 G V5 0
G ND_A NA1
G ND_V B G ND_V B
Figure 33 DC Voltage & Temperature Measurement
3.8.2 Assembly Drawing

Figure 34 Assembly Drawing of the Driver Board (Top)

Figure 35 Assembly Drawing of the Driver Board (Bottom)

For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 34 and
Figure 35.
3.8.3 Layout
Layout of the Driver Board is shown on Figure 36 (Top Layer), on Figure 37 (Layer-2), on Figure 38 (Layer-3),
on Figure 39 (Layer-4), on Figure 40 (Layer-5) and on Figure 41 (Bottom Layer).

Figure 36 Driver Board - Top Layer
Figure 37 Driver Board - Layer-2


Figure 41 Driver Board - Bottom Layer

3.8.4 Bill of Materials
Table 3 Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board
Reference Value / Device Package
C15_WT,C15_WB,C15_VT,C15_VB,C15_UT, 4u7/25V/X7R C1206
C15_UB,C16_WT,C16_WB,C16_VT,C16_VB,
C16_UT,C16_UB,C20_WT,C20_WB,C20_VT,
C20_VB,C20_UT,C20_UB,C21_WT,C21_WB,
C21_VT,C21_VB,C21_UT,C21_UB,C868,C87
1,C874,C880,C885,C889
C17_WT,C17_WB,C17_VT,C17_VB,C17_UT, 100n/50V/X7R C0603
C17_UB,C22_WT,C22_WB,C22_VT,C22_VB,
C22_UT,C22_UB,C23_WT,C23_WB,C23_VT,
C23_VB,C23_UT,C23_UB,C821
C79,C80,C81,C82,C83,C84 22n/50V/X7R C0603
C822 10u/16V/X7R C1206
C827,C830,C835,C891 100n/16V/X7R C0402
C828,C831 150p/50V/C0G C0402
C832 330p/50V/COG C0402
C833,C881,C886,C894,C895 10n/50V/X7R C0402
C866,C869,C872,C877,C882,C887 4u7/50V/X7R C1210
C867,C870,C873,C879,C883,C888 22u/35V D
C875,C876 22u/63V C0810
C878 100nF/100V/X7R C1206
C884 22n/50V/X7R C0402
C890,C907 22u/16V/X7R C1210
C896,C898,C899 10n/50V/X7R C0603
C897,C906 100n/50V/X7R C0805
C900,C901,C902,C903,C904,C905 100pF/100V/COG C0603
C908,C910,C911,C913,C914,C916 10n/50V/X7R C0603
C909,C915 1u/16V/X7R C0603
C912 1u/16VV/X7R C0603
D3_WT,D3_WB,D3_VT,D3_VB,D3_UT,D3_U P6SMB510A SMB
B
D4,D6,D8,D10,D11,D14,D16,D18 ES1A DO214
D4_WT,D4_WB,D4_VT,D4_VB,D4_UT,D4_U ES1D DO214
B
D5,D7,D9,D13,D15,D17 1SMA5929BT3G DO214
D6_WT,D6_WB,D6_VT,D6_VB,D6_UT,D6_U MURA160T3G DO214
B
D9_WT,D9_WB,D9_VT,D9_VB,D9_UT,D9_U SMBJ14CA SMB
B

Table 3 Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board (cont’d)
D12 1SMB5935BT3 SMB
D19 BZV55/C13 SMD
D20 1SMB30AT3 SMB
D21,D22,D23 LED_LSM676-MQ D0805
K1 MMS-112-01-L-DV 24POL
L1 MURATA_BLM21P221SN L0805
Q4 FS800R06KE3 HybridPACK™1
Q5 IPD144N06NG TO252
Q10 IPD90P03P4L-04 TO252
Q11,Q12 BCR183S SOT363
Q13 BCR10PN SOT363
R14_WT,R14_WB,R14_VT,R14_VB,R14_UT, 0R R0603
R14_UB,R206,R207,R214
R28_WT,R28_WB,R28_VT,R28_VB,R28_UT, 1K R0603
R28_UB
R28 10K R0805
R29_WT,R29_WB,R29_VT,R29_VB,R29_UT, 4K7 R0603
R29_UB
R31_WT,R31_WB,R31_VT,R31_VB,R31_UT, 47R R0805
R31_UB
R32_WT,R32_WB,R32_VT,R32_VB,R32_UT, 2R7 R2512
R32_UB,R33_WT,R33_WB,R33_VT,R33_VB,
R33_UT,R33_UB
R34_WT,R34_WB,R34_VT,R34_VB,R34_UT, 4.75 kΩ R0402
R34_UB,R193
R82,R83,R84,R85,R86,R87,R182 10K R0402
R127,R510 2K /0.1% R0603
R132 4K / 0.1% R0603
R133,R134,R135,R136,R137,R138 590K R1206
R139 3K9 R0603
R145,R146 10K 0.1% R0603
R169,R170,R171,R173,R174,R175,R178,R17 1.6 kΩ R1206
9,R180,R183,R185,R186,R190,R191,R192,R
196,R197,R198
R184 80K6 R0402
R187 19K6 R0603
R194 0R025 R2010
R199,R533 0R R1210
R201 59K R0603
R203,R205,R208,R209,R211,R213 10K/1% R0603

Table 3 Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board (cont’d)
R204,R210,R212 Opt R0603
R408 158R R0603
R509 39R R0603
R511,R513,R515,R521,R523,R525,R527,R52 15k R0603
9,R531
R512,R514,R516 1K R0603
R517,R518,R519 220R R0603
R520,R522,R524,R526,R528,R530 100R R0603
R534 Opt R1210
R535 226K R0603
R536 5K1 R0603
R537 47K R0603
T1 TRANSFORMER2
T1_WT,T1_WB,T1_VT,T1_VB,T1_UT,T1_UB ZXTN2010Z SOT89
T2_WT,T2_WB,T2_VT,T2_VB,T2_UT,T2_UB ZXTP2012Z SOT89
U4,U5,U6,U7,U8,U9 1ED020I12-FA PG-DSO-20
U18,U33,U34 AD8552ARZ SO-8
U19 ACPL-782T DIP-8
U30 LM3478MM MSOP-8
U56 TLE4296GV50 SCT595
U57 74LVC1G11GW SOT363
U58 MAX6457UKD3A-T SOT23-5

Logic Board for Hybrid Kit for HybridPACK™1
4 Logic Board for Hybrid Kit for HybridPACK™1
Figure 42 Logic Board for Hybrid Kit for the HybridPACK™1

Logic Board (Figure 42) contains all the components for the control of the Hybrid Kit for the HybridPACK™1.
Furthermore it offers the interface for all the other elements which build a complete inverter system: motor interface
(encoder, resolver, sensors), current sense interface, communication (CAN and RS232) and additional analogue
(x3) and digital (x4) inputs/outputs. Figure 43 shows the block structure of the Logic Board and the following
chapters describe these blocks in detail.
Debug Logic Board

Connector
Watchdog Supply
Microcontroller
Supply EEPROM
C C TC1767
PWM Vdc, Temp
o o
n Vdc meas.
n
n n I, U, V current
TempIGBT
e e measurement
c c Resolver
t Level CAN / RS232
FAULT t interface
o Signals o Shifter Encoder / Sensor
r RST r
Resolver
6ED100HP1-FA Driver Board
Connector
IGBT module HybridPACK™1
Current U
CAN RS232 A/D IO Supply
Current V
Current W
Encoder
Motor Resolver
3~
Sensor
Figure 43 Block Diagram of the Logic Board
4.1 External Connector (X1-SIG1) Pin Assignment

Connector X1-SIG1 (Harwin M80-5125042P) provides the interface to all the external systems: motor (encoder,
resolver, sensors), current sense, communication (CAN and RS232) and extra analogue and digital
inputs/outputs. Figure 44 shows the pin assignment of the connector X1-SIG1. For the description of the signals
see Table 4.

S2 2 1 ADC_IN1
S6 4 3 ADC_IN2
S3 6 5 ADC_IN3
Motor Interface
S1 8 StatorTemp
7 (Resolver)
R1 GND_ANA1
10 9 Motor Interface
(Encoder)
R2 12 11 DIO_1
Motor Interface
VANA50 DIO_2 (Hall Sensor)
14 13
GND_ANA1 DIO_3 Motor Interface
16 15 (iGMR Sensor)
I_U VDIG50
18 17 Phase Current
Sense
I_V GND_DIG1
20 19
I_W 22 iGMR_CSn- Communication
21
iGMR_CSn+ iGMR_Ren_DE+ General Purpose

24 23
Ana/Dig IN/OUT
iGMR_DATA- iGMR_Ren_DE-
26 25
Power Supply
iGMR_DATA+ PosA/iGMR_A+
28 27
iGMR_CLK- PosA/iGMR_A- Not Connected

30 29
iGMR_CLK+ 32 31 PosB/iGMR_B+
CAN1_L PosB/iGMR_B-
34 33
CAN1_H 36 PosZ/iGMR_Z+
35
ASC_TX PosZ/iGMR_Z-
38 37
ASC_RX PosU/iGMR_U
40 39
GND_DIG1 PosV/iGMR_V
42 41
+12V PosW/iGMR_W
44 43
+12V GND_DIG1
46 45
GND_DIG1 VDIG50
48 47
GND_DIG1
50 49
Harwin M80-5125042P
Figure 44 External Connector Pin Assignment
Table 4 External Connector Pin Assignment Logic Board v1.3b

Pin Number Pin Name Type Description
1 ADC_IN1 I/O General Purpose Analog I/O
2 S2 Input Resolver Sine (high)
4 S6 Input Resolver Sine (low)
6 S3 Input Resolver Cosine (high)
7 StatorTemp Input Motor Temperature Measurement
8 S1 Input Resolver Cosine (low)
9 GND_ANA1 Supply Analog Ground
10 R1 Output Resolver Excitation (high)
11 DIO1 I/O General Purpose Digital I/O
12 R2 Output Resolver Excitation (low)

Table 4 External Connector Pin Assignment Logic Board v1.3b (cont’d)

Pin Number Pin Name Type Description
14 VANA50 Supply +5.0V Analog Power Supply
16 GND_ANA1 Supply Analog Ground
17 VDIG50 Supply +5.0V Digital Power Supply
18 I_U Input Current Sense Phase U
19 GND_DIG1 Supply Digital Ground
20 I_V Input Current Sense Phase V
21 iGMR_CSn- Output iGMR Chip Select (differential signal)
22 I_W Input Current Sense Phase W
23 iGMR_REn_DE+ Output iGMR Read Enable (differential signal)
24 iGMR_CSn+ Output iGMR Chip Select (differential signal)
25 iGMR_REn_DE- Output iGMR Read Enable (differential signal)
26 iGMR_DATA- I/O iGMR Data (differential signal)
27 PosA/iGMR_A+ Input Encoder Phase A (differential signal)
28 iGMR_DATA+ I/O iGMR Data (differential signal)
29 PosA/iGMR_A- Input Encoder Phase A (differential signal)
30 iGMR_CLK- Output iGMR SSC Clock (differential signal)
31 PosB/iGMR_B+ Input Encoder Phase B (differential signal)
32 iGMR_CLK+ Output iGMR SSC Clock (differential signal)
33 PosB/iGMR_B- Input Encoder Phase B (differential signal)
34 CAN1_L I/O Low line I/O CAN Signal
35 PosZ/iGMR_Z+ Input Encoder Phase Z - index (differential signal)
36 CAN1_H I/O High line I/O CAN Signal
37 PosZ/iGMR_Z- Input Encoder Phase Z - index (differential signal)
38 PosZ Output RS-232 Transmitter Output
39 PosU/iGMR_U Input Hall Sensor Phase U
40 ASC_RX Input RS-232 Receiver Input
41 PosV/iGMR_V Input Hall Sensor Phase V
43 PosW/iGMR_W Input Hall Sensor Phase W
44 KL_30_IN Supply +12.0V Power Supply
46 KL_30_IN Supply +12.0V Power Supply
47 VDIG50 Supply +5.0V Digital Power Supply
49 NC NC Not Connected

4.2 Connector to the Driver Board (K1)

See Chapter 3.3.
4.3 Power Supply

The complete system (Driver Board and Logic Board) must to be supplied with and external regulated DC power
supply connected to connector X1-SIG1 (+12.0V on pins 44 and 46 and GND_DIG1 on pins 48 and 50) on the
Logic Board. The input voltage should be kept between 8 V and 18 V and the current consumption will vary
depending on different factors, i.e. PWM frequency.
This supply line will be forwarded to the Driver Board through the connector K1. On both boards a protection circuit
will avoid damages in case of overvoltage or wrong polarity (see Figure 45).
K L_ 30_ IN
+12 .0V
Q4
IPD90P 0 3P 4 L-0 4
K L_ 3 0
D2 +12 .0 V
B ZV 5 5/C13 D3
R128 1 SM B3 0 AT 3
1 0K
G ND_DIG1 GND_DIG 1
Figure 45 Overvoltage and Wrong Polarity Protection Circuit

The supply block (see Figure 52) generates all the necessaries supplies for the components on the logic board
(5V, 3.3 V and 1.5 V). Furthermore the 5 V (analogue and digital) are connected to the external connector (X1-
SIG1) for supplying external systems (i.e. current sensor).
The Logic Board use the Infineon Technologies TLE7368E Micro Controller Power Supply IC. After applying the
main power supply the IC13 will be switched-on. As soon as 5 V/3.3V/1.5V power supplies reached their correct
values the signal POWERrstn (RO_1 and RO_2 outputs of IC12) will be activated waking-up the microcontroller.
For further details of the TLE7368E please refer to the datasheet.
4.4 Microcontroller
The microcontroller block (uC block in overview given in Figure 51) contains following elements:
• TC1767 (Figure 61) is a 32-Bit Microcontroller member of the Infineon Technologies AUDO FUTURE product
family designed for automotive applications. TriCoreTM CPU providing high-end microcontroller performance
combined with sophisticated DSP capabilities (please refer to datasheet for further details)
• Input filter (see Figure 60): passive filters for digital and analogue signals and voltage dividers for voltage level
adaptation
• EEPROM (Figure 62): 256kB Electrically-Erasable Programmable Read-Only Memory optimized for use in
automotive applications where low-power and low-voltage operations are essential (for more details refer to
AT25256A-10TQ-2.7 datasheet). The communication with the microcontroller is done through SSC0 interface
(high-speed synchronous serial interface, SPI-compatible)
• RS-232 & CAN Transceivers (see Figure 59)
4.4.1 Configuration of TC1767

The TC1767 can be configured with the respect to the different boot modes and with the respect to the different
interfaces (serial/parallel) to the resolver and iGMR position sensors.

4.4.1.1 Boot Configuration of TC1767
.1
.7
.6
.5
.4
.3
.2
.0
P0
P0
P0
P0
P0
P0
P0
P0
LOW ON
HIGH 1 2 3 4 5 6 7 8
Figure 46 HW Boot Configuration of TC1767 DIP-Switch
The picture above (Figure 46) shows the definition of the boot HW configuration switch (DIP-Switch SW1 on
Figure 61). The meaning of the switches will be described in the following Table 5.
The ON position of the switch is equal to a logical LOW at the dedicated pin.
Table 5 User Startup Modes for TC1767

CFG[7...0] Type of Boot TC1767 11) 2 3 4 5 6 7 8
11XXX11X2) Internal Start from Flash OFF OFF X3) X X OFF OFF X
010XX110 Bootstrap Loader Mode, Generic Bootloader at ON OFF ON X X OFF OFF ON
CAN pins
10101110 Bootstrap Loader Mode, ASC Bootloader OFF ON OFF ON OFF OFF OFF ON
10100110 Alternate Boot Mode, ASC Bootloader on fail OFF ON OFF ON ON OFF OFF ON
1011X11X Alternate Boot Mode, Generic Bootloader at OFF ON OFF OFF X OFF OFF X
CAN pins on fail
All others Reserved; don’t use this combination
1) 1 to 8 are the DIP-Switch numbers
2) The shadowed line indicates the default settings.
3) ’x’ represents the don’t care state.
4.4.1.2 Selecting Serial/Parallel Interface

DIP-4 switch (SW2 on Figure 59) is used to select serial/parallel interface for the communication with resolver or
iGMR position sensor - please refer to Table 6.
Table 6 Selecting Serial/Parallel Interface

SW2[4...1] Inetrface to the Resolver/iGMR 41) 3 2 1
2) 3)
0000 iGMR enabled (SPI and Incremental mode) OFF OFF OFF OFF
Resolver in Parallel Mode
1111 Resolver in Serial Mode ON ON ON ON
iGMR disabled
All others Reserved; don’t use this combination
1) 1 to 4 are the DIP-Switch numbers
2) 0 is equal to open switch, “1” is equal to closed switch
3) ’x’ represents the don’t care state.

Figure 47 The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2)
4.5 Watchdog
The Logic Board contains a pin-selectable watchdog timer that supervises the microcontroller activity and
signalizes when the system is operating improperly. During normal operation, the microcontroller (GPTA39)
should repeatedly toggle the watchdog input (WDI, see Figure 55) before the selected watchdog time-out period
elapses to report that the system is processing code properly. If this does not occurs, the supervisor asserts a
watchdog output (WDO) which will reset the microcontroller via PORSTn (external power-on hardware reset).
The state of the three logic control pins (SET0, SET1 and SET2) determines watchdog timing characteristics (see
table in Figure 55). The jumper J1 allows disabling the watchdog functionality in a very easy way.
4.6 Phase Current Sensing

Phase current sensing signals should be connected to the Logic Board connector X1-SIG1 to the pins I_U, I_V
and I_W (Figure 60). The Logic Board is designed to work with current transducers (not provided with the Hybrid
Kit) with voltage output proportional to the current (usually deploying Hall effect - like LEM sensors). User can take
+5V (analog) available on the X1-SIG1 pins to supply current transducers. The exact type of current transducer
will depend on many parameters in application, but usually the most important is the motor current consumption.
Please notice that if you control 3-phase balanced synchronous system it is enough to measure just 2 phases,
since the 3rd phase current can be calculated as algebraic combination out of the 2 measured currents. The
microcontroller is able to convert synchronously two phase currents, it’s recommended to do an accurate current
measurement.
4.7 Temperature Sense

The Logic Board includes a temperature sensor (IC54, LM50-CIM3) which is located on the bottoside of the board.
With the sensor it is possible to measure the ambient temperature between Logic Board and Driver Board. For
schematics and output voltage values of the circuit see Figure 64. If you need any further information about the
device please refer to the data sheet.
4.8 Resolver Interface

The Logic Board includes a 12-Bit Resolver-to-digital converter (meaning A/D converter) which integrates an on-
board programmable sinusoidal oscillator that provides sine wave excitation for resolvers (pins R1 and R2 on
connector X1-SIG1). For more details please refer to the data sheet of the component (AD2S1200YST) and the
schematics of the circuit see Figure 56. With resistors (R155, R156, R157, R158, R159 and R160) user can trim
the LMH6672 (dual op-amp) output voltage values (resolver excitation). On the Logic Board is given additional
possibility to trim the resolver excitation with potentiometers (R483, R484, R485 - not populated, user should
solder them if needed). Please refer to data sheet of used resolver to trim this values properly. The resolver
response should be connected between pins S1 and S3 (sine) and S2 and S6 (cosine) on the connector X1-SIG1.

4.9 Encoder Interface

If encoder is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1
should be connected: the phase A should be connected between pins PosA/iGMR_A+ and PosA/iGMR_A-, the
phase B should be connected between pins PosB/iGMR_B+ and PosB/iGMR_B- and phase Z (index or zero
marker) should be connected between pins PosZ/iGMR_Z+ and PosZ/iGMR_Z- .
4.10 Hall Sensor Interface

If Hall sensor is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1
should be connected: the phase U should be connected to pin PosU/iGMR_U, the phase V should be connected
to pin PosV/iGMR_V and phase W should be connected to pin PosW/iGMR_W .
4.11 GMR Interface

As mentioned on the beginning of the Chapter 4, the Logic Board supports GMR interface by means of a bi-
directional SSC (SPI compatible), encoder (or incremental) and Hall sensor interface. It is explicitly recommended
to use Infineon Technologies TLE5012 GMR-based angular sensor for rotor position sensing. The TLE 5012 is a
360° angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine
angle components with monolithic integrated Giant Magneto Resistance. For more details about TLE5012 please
refer to the data sheets on Infineon Technologies internet pages.

4.11.1 GMR SSC Interface Mode
R9 R 10 R1 1
3k 3 3 k3 3k 3
U1 06 03 0 60 3 06 03
2 R1
3 R in1 + 10 0R 06 03
Ro ut 1
R in1 - 1
6
R in2 +
5
Ro ut 2
7 R2
R in2 - 10 0R 06 03
10 X15
R in3 +
11
R4 Ro ut 3 9 1
R in3 - 2
1k 3
0 60 3 R3
4
14 10 0R 06 03
13 R in4 + 5
U2 U3 Ro ut 4 15 6
R in4 - 7
6 2 8 16
VDD SC K VCC VCC 8
3 4
CSQ 7 EN 9
4 2 D O+ 12 R6 R7 R8 10
1 DATA D in 6 8 EN_ n 11
C LK D O- GN D 3k 3 3 k3 3k 3 12
5 1 06 03 0 60 3 06 03
I FA 8 5 DE 13
I FB RE D S9 0C 03 2BTM 14
3
R ou t
7
G ND
TL E5 01 2 4 H ea de r_ 7x2
G ND R5
DS9 2LV0 10 ATM 5 4R 06 03
U4
1 2
1A 1Y 3
1Z
7 6
2A 2Y
2Z 5
9 10
3A 3Y
11
1 0u /1 0V/X7 R/ LMK31 6B7 10 6KL
3Z
10 0n /1 6V/ X7R/ EMK10 7B71 04 KA
1 00n /1 6V/ X7R /EMK10 7B7 104 KA

0 60 3
0 60 3
10 0n/ 16 V/X7 R/ EMK1 07 B710 4KA
10 0n/ 16 V/X7 R/EMK1 07 B710 4KA

06 03
1 206
06 03
15 14
4A 4Y
1 0p/ 25 V/X7 R
0 60 3
10p /2 5V/ X7R

06 03
13
4Z
C3
C5
C1
C2
C4
16
4 VCC
C6
G
C7
12
G
8
GN D
AM26 LS3 1C DR
Figure 48 GMR SSC Interface - Proposal Using TLE5012

The schematics of SSC interface on the Logic Board is shown on Figure 63. Signals on connector X1-SIG that
are used for SSC interface are: iGMR_CSn+/iGMR_CSn- (Chip Select, differential signals),
iGMR_REn_DE+/iGMR_REn_DE- (Read Enable, differential signals), iGMR_DATA+/iGMR_DATA- (Serial Data,
differential signals) and iGMR_CLK+/iGMR_CLK- (SSC Clock, differential signals) - all signals are listed in
Table 4. On Figure 48is presented the schematics of possible technical solution (implemented by Infineon
Technologies System Engineering) for usage of TLE5012. The PCB with TLE5012 and a few additional
components is mounted perpendicular to the electric motor shaft - just as shown on Figure 49.
Figure 49 Picture of Possible Physical Implementation of the GMR Sensor

4.11.2 GMR Encoder Interface Mode

Infineon Technologies iGMR sensor TLE5012 can be used with encoder interface as well. This working mode is
referred as IIF Interface mode in theTLE5012 data sheet. To avoid signal integrity and EMC problems, within
Hybrid Kit it is expected that the 2 phase signals (A and B) and zero (index) signal are provided differentially. On
the connector X1_SIG (Figure 44) encoder inputs are: PosA/iGMR_A+ and PosA/iGMR_A (phase A),
PosB/iGMR_B+ and PosB/iGMR_B (phase B) and PosZ/iGMR_Z and PosZ/iGMR_Z (phase Z - index) - please
refer to the Table 4. Please refer to the TLE5012 data sheet to get iGMR sensor running in incremental mode.
4.11.3 GMR Hall Sensor Interface Mode

TLE5012 supports Hall sensor interface mode as well (iGMR emulates Hall sensor mode). For this purpose to the
connector X1-SIG inputs PosU/iGMR_U (phase U), PosV/iGMR_V (phase V) and PosW/iGMR_W (phase W)
should be connected. Please notice (on Figure 60) that the pull-up resistors to 3.3 V (R491, R492 and R493) are
already provided on the Logic Board. For more details on Hall sensor mode please refer to the TLE5012 data
sheet.
4.12 Definition of Layers for the Logic Board

The Logic Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 50.
1 Copper 1 Isolation
2 1: 35 µm 2 1-2: 0.5 mm
2: 35 µm 2-3: 0.5 mm
3 3
3-4: 0.5 mm
3: 35 µm
4 4 4-5: 0.5 mm
4: 35 µm
5
5-6: 0.5 mm
5
5: 35 µm
6 6
6: 35 µm
Figure 50 Definition of the Layers for the Logic Board

4.13 Schematics, Layout and Bill of Materials

To meet the individual customer requirements and to make the Logic Board for the HybridPACK™1 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
for the Logic Board are included in this chapter.
4.13.1 Schematics
uC
T DO
T DO T DI T DO
T DI T MS T DI
T MS T CK T MS
T CK T RSTn T CK
T RS Tn B RKINn T RSTn
B RK INn B RKOUT n B RKINn
OCDS1
B RKOUT n B RKOUT n
Rese tn
Rese tn Rese tn
WAT CHDOG
DEBUG WDO WDI WDI
WAT CHDOG
S UPPL Y
CONNE CTO R POWERrstn
SUP PL Y P osA/iG MR_ A+

P osA /iGMR_ A+ P osA/iG MR_ A- P osA/iG MR_ A+
PosA /iG MR_ A- P osA/iG MR_ A- CONNE CTO R_ Drive rBo a rd
P osB/iG MR_ B+
P osB /iGMR_ B+ P osB/iG MR_ B+ L EV E L_ SHIFTER
P osB/iG MR_ B-
PosB /iG MR_ B- P osZ/iG MR_ Z+ P osB/iG MR_ B-
P osZ/iG MR_ Z+ P osZ/iG MR_ Z- P osZ/iG MR_ Z+
PosZ/iG MR_ Z- P osZ/iG MR_ Z- PWM UT _ uc
P osU/iG MR_ U P WM UT n PWM UB_ uc P WM UT _ uC P WM UT P WM UT
P osU/iGMR_ U P osU/iG MR_ U PWM UBn PWM VT _ uc P WM UB _ uC PWM UB P WM UB
P osV/iG MR_ V P WM VT n PWM VB_ uc P WM VT _ uC P WM VT P WM VT
P osV /iG MR_ V P osV/iG MR_ V P WM VB n PWM WT _u c P WM VB _ uC P WM VB P WM VB
P osW/i G MR_ W P WM WT n PWM WB _u c P WM WT _u C P WM WT P WM WT
PosW/i G MR_ W P osW/i G MR_ W P WM WBn P WM WB _u C PWM WB P WM WB
i GM R
FLT Un_ u c
i GM R_DAT A+ i GM R_DAT A + FLT _ Un FLT V n_ u c FLT Un_ u C FLT Un FLT Un
i GM R_DAT A - i GM R_DAT A - i GM R_DI_u C i GM R_DI_u C FLT _ Vn FLT Wn _ uc FLT Vn_ u C FLT V n FLT V n
i GM R_CLK+ i GM R_CLK + i GM R_ROUT _u C i GM R_ROUT _u C FLT _ Wn FLT n _u C FLT Wn _ uC FLT Wn FLT Wn
i GM R_CLK- i GM R_CLK - i GM R_CLK _ uC i GM R_CLK_ uC FLT _ n RST n _u c FLT n _u C FLT n FLT n
i GM R_CSn + i GM R_CSn + i GM R_CS_ u C i GM R_CS_ u C RST n RST _ INn _u C RST _ INn RST _ INn
i GM R_CSn - i GM R_CSn - i GM R_RE_ u C i GM R_RE_ u C
i GM R_REn _ DE + i GM R_REn _ DE+ i GM R_INDE X_ u C i GM R_INDE X_ u C
i GM R_REn _ DE- i GM R_REn _ DE- L EV E L_ SHIFTER
I_ U i GM R
I_ U I_ V I_ U
I_ V I_ W I_ V
I_ W I_ W
CAN1 _L
CAN1 _L CAN1 _H CAN1 _L
CAN1 _H A SC_ TX CAN1 _H VDC_ uC
A SC_ TX A SC_ RX A SCTX VDC_ uC V DC
ASC_ RX A SCRX
S ta to rT e mp
S ta to rT e mp S ta to rT e mp
Reso l ve r
A T EM P_ IGB T _W T EM P_ HP2 _ W
S1 A B A T EM P_ IGBT _U T EM P_ HP2 _ U
S1 S3 S1 B NM B T EM P_ IGB T _V T EM P_ HP2 _ V
S3 S2 S3 NM NM
S2 S2 T EM P_ BOARD
S6 A D2 S12 0 0_ SA M PL En _ uC
S6 R1 S6 A D2 S 12 0 0_ SA M PL En A D2 S12 0 0_ RE SET n _u C A D2 S12 0 0_ SA M PL E_ u C
R1 R2 R1 AD2 S 12 0 0_ RES ET n A D2 S12 0 0_ RE SET n _u C
R2 R2 A D2 S12 0 0_ CS n _u C CONNE CTO R_ Drive rBo a rd
AD2 S12 0 0_ CSn A D2 S12 0 0_ SO E _u C A D2 S12 0 0_ CS n _u C T EM P_ Boa rd T em p_ B oa rd
A D2 S12 0 0_ SO E A D2 S12 0 0_ SO E_u C
A D2 S12 0 0_ RDVEL n _u C
A D2 S 12 0 0_ RDVEL n A D2 S12 0 0_ FS1 _u C A D2 S12 0 0_ RDVEL n _u C
A D2 S 12 0 0_ FS1 A D2 S12 0 0_ FS2 _u C A D2 S12 0 0_ FS1 _u C
A D2 S 12 0 0_ FS2 A D2 S12 0 0_ FS2 _u C
L EV E L_ SHIFTER_ RESOL V ER
T EM P_ BOARD
E Nn SERIAL _ PA RAL LE L _M ODE _u C
A D2 S12 0 0_ DO S SERIAL _ PA RAL LE L _M ODE_u C A D2 S12 0 0_ DO S _u C S ERIAL _ PA RA L LE L _M ODE_u C
A D2 S 12 0 0_ DO S A D2 S12 0 0_ L OT A D2 S 12 0 0_ DO S A D2 S12 0 0_ DO S _u C A D2 S12 0 0_ L OT _u C A D2 S12 0 0_ DO S_u C
A D2 S 12 0 0_ L OT A D2 S12 0 0_ DB 1 1_ SO A D2 S 12 0 0_ L OT A D2 S 12 0 0_ L OT _u C AD2 S12 0 0_ DB1 1_ S O_ u C A D2 S12 0 0_ L OT _u C
A D2 S 12 0 0_ DB 1 1_ S O A D2 S12 0 0_ DB 1 0_ SCL K A D2 S 12 0 0_ DB 1 1_ S O A D2 S 12 0 0_ DB 1 1_ S O_ u C A D2 S 12 0 0_ DB 1 0_ SCL K _u C A D2 S12 0 0_ DB 1 1_ SO_ u C
A D2 S 12 0 0_ DB 1 0_ S CL K A D2 S12 0 0_ DB 9 A D2 S 12 0 0_ DB 1 0_ S CL K A D2 S 12 0 0_ DB 1 0_ S CL K _u C A D2 S12 0 0_ DB 9 _u C A D2 S12 0 0_ DB 1 0_ SCL K_u C
AD2 S12 0 0_ DB9 A D2 S12 0 0_ DB 8 A D2 S 12 0 0_ DB 9 AD2 S12 0 0_ DB9 _u C A D2 S12 0 0_ DB 8 _u C A D2 S12 0 0_ DB 9 _u C
AD2 S12 0 0_ DB0 A D2 S 12 0 0_ DB 0 AD2 S12 0 0_ DB0 _u C A D2 S12 0 0_ DB 0 _u C
Reso l ve r L EV E L_ SHIFTER_ RESOL V ER

A DC_ IN1 A DC_ IN1
A DC_ IN2 A DC_ IN2
A DC_ IN3 A DC_ IN3
DIO _ 1 DIO_ 1
DIO _ 2 DIO_ 2
DIO _ 3 DIO_ 3
uC
CONNE CTO R
Figure 51 Schematics Block Overview

V DIG50 V DIG 33 V DIG 15

+5.0 V +3.3 V +1.5 V
Q _S TB Y Q_S TB Y V DIG 33
D5 D6
+1.0 V +1.0 V +3.3 V
K L_ 30
+12 .0V
IC13
22u/16V/X7R/F_1463575
22u/16V/X7R/F_1463575
22u/16V/X7R/F_1463575
T LE 7 36 8E V SW S S12 _1 A _If_ 20 V_V r S S1 2 _1A _If_20V_ V r
R47 3 +5.4 V
100uF_35V_MAL214097001E3
220nF/100V/C3216X7R2A224KT5
34 33 10K WE_74 4 77 0 94 70
100uF_35V_MAL214097001E3
11 IN_ S TB Y Q _S TB Y 3 5
C1135
C1136
C86
S EL _ ST BY M ON_S T BY 2 6 L3 T yp XX L
S W1 2 7
680n/50V/F_1414702
20 S W2
21 IN1
C1150
C1152
+ 22 IN2 +
14 IN3
C93
C92
D1
C1+ M BRS34 0T 3 G ND_DIG1 G ND_DIG1 G ND_DIG1
C11 51 28
1 00n /50 V/X 7 R1 2 B ST
13 C1- G ND_DIG1 G ND_DIG1
C2- 29 V DIG 50 V ANA5 0
C11 53 FB 5 +5.0 V +5.0 V
1 00n /50 V/X 7 R1 5 IN_ LDO 2 L1
G ND_DIG1 16 C2+ V DIG 50 V DIG 33 M URAT A _B L M2 1P G 22 1 SN
CCP +5.0 V +3.3 V V DIG 15
22u/16V/X7R/F_1463575
V DIG 33 C11 56 30 4 +1.5 V
22u/16V/X7R/F_1463575
+3.3 V 2 20n /25 V/X 7 R/F_14 14 626 Q _L DO1 6 2
4u7/10V/X7R
100n/50V/X7R
Q _L DO2
32 1
C1154
C1155
G ND_DIG1 Q2
23 DRV _ EX T
C85
B DP 9 49
9 S EL _ Q2 3
C1142
R47 4 1 0K
K L_ 30 R47 5 1 0K 10 E N_ u C 31
+12.0 V E N_ IGN FB_ E XT Q _T 2 Q _T 1 V DIG 33
+5.0 V +5.0 V +3.3 V
24 8 G ND_DIG1
WDI Q _T 2 7 G ND_DIG1
25 Q _T 1 3 G ND_A NA1
WDO RO_ 1 4 R47 6 V DIG 33 V ANA3 3
2 RO_ 2
GND_A1
GND_A2
GND_A3
GND_A4
1 0K +3.3 V +3.3V
GND_P
RT L9
PAD
1n/16V/X7R
M URAT A _B L M2 1P G 22 1 SN
C1159
P OWERrstn C11 5 7 C11 58

C12 3
37
18
19
17
36
10u /10V /X7R 100 n /16 V/X 7 R 10u /1 0V /X7 R

R113
S MK -R0 0 0 / Isab el l enh uette
G ND_DIG1 G ND_DIG1 K L_ 3 0_ IN
K L_ 3 0 +12 .0 V
+12 .0 V
M URAT A _B L M2 1P G 22 1 SN V re f5 0 G ND_DIG1 GND_A NA1 G ND_A NA1
IC5 3 +5.0 V
2
M AX 614 3A A SA 5 0
6
C1166
C1167
L 10 V DIG50 Q4 V DIG 15 V ANA1 5

IN
+5.0 V O UT IPD9 0P 0 3P 4 L-0 4 Q _S TB Y Q _T 2 Q_T 1 +1.5V +1.5 V

7 +1.0 V +5.0 V +5.0 V
S HDN K L_ 30
3 5 D2 +12 .0V
4.7u/50V/X7R/C1210F475K5
100n/50V/X7R/C0805F104K5
T EM P T RIM L 11
1
C1145
C1144
C1146
M URAT A _B L M2 1P G22 1 SN
1u/25V/X7R/F_1637035
4u7/10V/X7R/F_9402195
4u7/10V/X7R/F_9402195
GND
8 I.C._1 B ZV 5 5/C13 D3
I.C._8 R128 1 SM B3 0 AT 3
1 0K
4
R48 6 0 R / 0.1 % G ND_DIG1 G ND_DIG1 GND_DIG1
G ND_RE F1 G ND_A NA1 G ND_DIG1 G ND_DIG1
Figure 52 Power Supply
V DIG 33
+3.3 V
R1 R2 R3 R4 R5
1 0K 1 0K 1 0K 1 0K 1 0K
K 3-O CDS
2 1
4 3 T MS
6 5 T DO
8 7
Rese tn 10 9 T DI
B RK OUT n 12 11 T RS Tn
14 13 T CK
16 15 B RK INn
HEA DE R 8 X 2 R6
1 0K
G ND_DIG1
Figure 53 JTAG Debug Connector

G ND_DIG1 G ND_A NA1

1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
C11 6 9 C11 7 0 C11 7 1 C11 7 2 C11 7 3 C11 7 4 C11 7 5 C11 7 6 C11 7 7 C11 7 8 C11 7 9 C11 8 0 C11 8 1 C11 8 2 C11 8 3 C11 8 4 C11 8 5
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
K2
P1 1 2 P2
ADC_IN1 3 1 2 4 S2
P3 P4
ADC_IN2 5 3 4 6 S6
P5 P6
GND_DIG1 GND_ANA1
ADC_IN3 7 5 6 8 S3
P7 P8
S ta to rT e mp 9 7 8 10 S 1 V ANA5 0
P9 P 10
11 9 10 12 R1 +5.0 V
P 11 P 12
DIO _ 1 13 11 12 14 R2
V DIG 50 DIO _ 2 P 13 P 14
GND_ANA1
+5.0 V DIO _ 3 P 15 15 13 14 16 P 16
P 17 17 15 16 18 P 18
19 17 18 20 I_U
P 19 P 20
21 19 20 22 I_V
P 21 P 22
i GM R_ CSn - 23 21 22 24 I_W
P 23 P 24
i GM R_ REn _ DE + 25 23 24 26 i GM R_ CSn +
P 25 P 26
i GM R_ REn _ DE - 27 25 26 28 i GM R_ DAT A -
P 27 P 28
P osA /i G MR_ A+ 29 27 28 30 i GM R_ DAT A +
P 29 P 30
P osA /i G MR_ A- 31 29 30 32 i GM R_ CLK -
P 31 P 32
P osB /i G MR_ B+ 33 31 32 34 i GM R_ CLK +
P 33 P 34
P osB /i G MR_ B- 35 33 34 36 CAN1_ L
P 35 P 36
P osZ/iG MR_ Z+ 37 35 36 38 CAN1_ H
P 37 P 38
P osZ/iG MR_ Z- 39 37 38 40 A SC_T X
P 39 P 40
P osU/i G MR_ U 41 39 40 42 A SC_RX
P 41 P 42
P osV /i G MR_ V 43 41 42 44
P 43 P 44 G ND_DIG1
P osW/i G MR_ W 45 43 44 46
P 45 P 46
P 47 47 45 46 48 P 48
GND_DIG1
49 47 48 50 P 50
49 50 G ND_DIG1
VDIG 50
1n/50V/X7R_opt C1187
1n/50V/X7R_opt C1188
1n/50V/X7R C1189
1n/50V/X7R C1190
1n/50V/X7R C1191
1n/50V/X7R C1192
1n/50V/X7R C1193
1n/50V/X7R C1194
1n/50V/X7R C1195
1n/50V/X7R C1196
1n/50V/X7R C1197
C1201
C1202
C1209
C1203
C1204
C1205
C1206
C1207
C1208
+5.0 V Harwi n M 80 -51 2 50 4 2P KL_ 3 0_ IN
+12 .0V
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
1n/50V/X7R_opt
C ap a ci t or s f o r E SD Pr o te c ti o n o fG ND_DIG1
uC G ND_DIG1
Figure 54 Connector (external)
s et 2 s et 1 se t 0 t de l ay , tw d
0 0 0 1ms
0 0 1 1 0 ms
0 1 0 3 0 ms
V DIG 33 0 1 1 D is a bl e d
+3.3 V 1 0 0 1 00 m s
1 0 1 1s
1 1 0 1 0s
1 1 1 6 0s
C12 1 0
1 00 n /1 6 V/X 7 R
R14 9 R15 0 R15 1 IC2 3

o pt 4 K7 4 K7 8 1
V cc WDI WDI
2
G ND_DIG1 G ND 3
4 NC
5 S ET 0
6 S ET 1 7
S ET 2 WDO W\D\O\
1
MA X 63 6 9K A -T
J1
1
Jum p er
R15 3 R15 4
2
4 K7 o pt
2
G ND_DIG1
Figure 55 Watchdog

V ANA5 0
+5.0 V
C116 3
G ND_A NA1
T P5 100 n/16V/X7 R
T estp ad _SM D_ Etti nge r IC4 A P ACKAG E = 1
4
LT16 39 HS
3 V+
S1 + 1 R10 2 S in
2 0R
11- V -
R10 3
opt
T P6 GND_A NA1 KL_ 30
T estp ad _SM D_ Etti nge r IC4 B P ACKAG E = 1 +12 .0V T LE 4266 GSV10
LT16 39 HS G ND_A NA1 IC25 M URAT A _B L M21PG 221 SN
5 1 3
S3 + 7 I Q
S in L O
C1112
R10 4
6 0R L8
GND
- 2
R10 5 V ANA5 0 INH C1111 C14 3 C144
opt +5.0V 2 2u F/16 V/X 7 R 2 2uF/16 V/X 7R 100n /25 V/X 7R
100n/50V/X7R/C0805F104K5
4
T P7
T P9
T estpad_ SM D_ E tti n ge r IC4 C P ACKAG E = 1
LT16 39 HS G ND_A NA1
10n/16V/X7R
10 G ND_DIG1 G ND_DIG1 G ND_DIG1
10n/16V/X7R
10uF/10V/X7R
4u7/16V/X7R
S2 + 8 R10 6 Cos
9 0R T estpad _SM D_ Etti n
C77
C78
C75
C76
- R483
R10 7 5 K_ pot_0,2 5W_20% _Bo urn s_3 314J_op t G ND_ANA1
opt
T P8
T estp ad _SM D_ Etti nge r IC4 D P ACKAG E = 1 GND_A NA1 G ND_A NA1
LT16 39 HS G ND_A NA1 GND_A NA1 R15 6
12 V DIG 50
S6 + 14 R10 8 CosL O +5.0 V 2 K4/0.1 %
13 0R G ND_A NA1
- T P1
T P4
8
R10 9 T estp ad _SM D_E tti n ge r C121 6 IC6
10n/16V/X7R
opt opt R15 5 T estp ad _SM D_E tti n ge r
4u7/25V/X7R
+Vs
2
CosLO
SinLO
V ANA5 0 2 K4/0.1% IN-1 1
Cos
Sin
R2
C80
C79
R11 0 3 O UT 1
G ND_A NA1 +5.0V
IN+1
5K_pot_0,25W_20%_Bourns_3314J_opt
o pt
C121 7
V DIG 33 opt T P3
+3.3 V GND_DIG1 T P2 R15 7 R15 8 T estp ad _SM D_E tti n ge r
C116 4 6
T estp ad _SM D_E tti n ge r G ND_A NA1
44
43
42
41
40
39
38
37
36
35
34
IC8 390/0 .1 % IN-2
2 K4/0.1% 7
G ND_DIG1 1 33 5 O UT 2 R1
R484
Sin
CosLO AD2S 120 0_RE S ET n
SinLO
AVdd
EXC
EXC
Cos
AGND
AGND
REFBYP
REFOUT
DVd d RES ET IN+2

5
IC3 0 100n /16 V/X 7R 2 32
-Vs
3 RD FS2 31 AD2S 120 0_FS2
A D2 S 12 00_ CSn AD2S 120 0_FS1 R15 9
VCC
1 6 4 CS FS1 30 LMH66 72
S 120 0_ SA M PL En AD2S 120 0_L OT 3K3 /0.1%
4
1A 1Y 5 S AM PL E L OT 29
3 4 A D2 S 12 00_ RDV EL n 6 RDV EL DOS 28 AD2S 120 0_DO S
A D2 S 12 00_ SO E n
GND
D2 S 120 0_ SO E 2A 2Y 7 S OE DIR 27
A D2 S 12 00_DB 11_ S O 8 DB1 1/S O NM 26 NM
G ND_A NA1
XTALOUT
A D2 S 12 00_ DB 10_ SCL K 9 DB1 0/S CLK B 25 B

R47 1 A D2 S 12 00_ DB 9 A G ND_A NA1 R160
2
DB9 A
DGND
CLKIN
74L V C2 G04 GW 10 24
DVdd
10K A D2 S 12 00_ DB 8 DB8 CPO

DB6
DB5
DB4
DB3
DB2
DB1
DB0
11 23 2K4 /0.1%
A D2 S 12 00_ DB 7 DB7 DGND
G ND_DIG1
12
13
14
15
16
17
18
19
20
21
22
AD2S 120 0Y ST
R48 5
G ND_DIG1 5 K_ pot_0,2 5W_20% _Bo urn s_3 314J_op t
AD2S1200_DB5
AD2S1200_DB0
AD2S1200_DB6
AD2S1200_DB4
AD2S1200_DB3
AD2S1200_DB2
AD2S1200_DB1
G ND_DIG1 U1
1 2
V DIG50 1 2
+5.0V
HCM 49 8 .1 9 2M A BJ-UT
20pF/50V/COG
20pF/50V/COG
10n/16V/X7R
C84
C83
4u7/25V/X7R
C81
C82
G ND_DIG1 G ND_DIG1
Figure 56 Resolver Interface
R73 1 0K
G ND_DIG1 G ND_DIG1 G ND_DIG1

V DIG50
R74
R75
R76
R77
R78
R79
+5.0 V
R71
R80
R88
1K
1K
1K
1K
1K
1K
1K
10K
G ND_DIG1
IC2 P WM WT
1 24
1K
48 1 DIR 2 DIR 25
1 OE 2 OE P WM WB
47 2
P WM WT _u C 46 1 A0 1 B0 3
P WM WB _u C 44 1 A1 1 B1 5 P WM VT
P WM VT _u C 43 1 A2 1 B2 6
P WM VB _u C 41 1 A3 1 B3 8
P WM UT _u C 40 1 A4 1 B4 9 P WM VB
P WM UB _u C 38 1 A5 1 B5 11
RST _INn _u C 37 1 A6 1 B6 12 RST _INn
1 5K V DIG 50 P WM UT
1 A7 1 B7 R90
+5.0 V
36 13
FLT Un_ u C 35 2 A0 2 B0 14
FLT V n_ u C 1K R92 P WM UB
33 2 A1 2 B1 16
FLT Wn _ uC 32 2 A2 2 B2 17 FLT Un
FLT n _u C 30 2 A3 2 B3 19 C64
29 2 A4 2 B4 20
2 A5 2 B5 1 00 n /1 6 V/X 7 R
27 22
V DIG 33 26 2 A6 2 B6 23 V DIG 50 G ND_DIG1 1 5K V DIG 50
2 A7 2 B7 R93
+3.3 V +5.0 V +5.0 V
31 7
42 V CCA V CCB 18 1K R95
C65 4 V CCA V CCB 28 C66
1 00 n /1 6 V/X 7 R 10 G ND G ND 34 1 00 n /1 6 V/X 7 R FLT V n
15 G ND G ND 39 C68
21 G ND G ND 45
G ND G ND 1 00 n /1 6 V/X 7 R
1 5K V DIG 50
R96
G ND_DIG1 7 4A L VC16 4 24 5 DG G G ND_DIG1 +5.0 V
1K R98
FLT Wn
C70
1 00 n /1 6 V/X 7 R
1 5K V DIG 50
R99
G ND_DIG1 +5.0 V
1K R10 0
FLT n
C71
1 00 n /1 6 V/X 7 R
G ND_DIG1
Figure 57 Level Shifter for Adapting Logic Levels for Driver Board

R49 7 0 R
S ERIAL _ PA RA LLE L _M ODE _u C E Nn
R45 6 1 K IC2 9
1 24 R49 8 0 R_ o pt
G ND_DIG1 48 1 DIR 2 DIR 25 G ND_DIG1
1 OE 2 OE G ND_DIG1
47 2
46 1 A0 1 B0 3
44 1 A1 1 B1 5
A D2 S 12 0 0_ DB 9 _u C 43 1 A2 1 B2 6 A D2 S 120 0_DB 9
A D2 S 12 0 0_ DB 8 _u C 41 1 A3 1 B3 8 A D2 S 120 0_DB 8
A D2 S 12 0 0_ DB 7 _u C 40 1 A4 1 B4 9 A D2 S 120 0_DB 7
A D2 S 12 0 0_ DB 6 _u C 38 1 A5 1 B5 11 A D2 S 120 0_DB 6
A D2 S 12 0 0_ DB 5 _u C 37 1 A6 1 B6 12 A D2 S 120 0_DB 5
A D2 S 12 0 0_ DB 1 0_ S CLK _u C 1 A7 1 B7 A D2 S 120 0_DB 1 0_ S CL K
36 13
A D2 S 12 0 0_ LOT _u C 35 2 A0 2 B0 14 A D2 S 120 0_L OT
A D2 S 12 0 0_ DO S _u C 33 2 A1 2 B1 16 A D2 S 120 0_DO S
A D2 S 12 00_ DB 1 1_ SO_ u C 32 2 A2 2 B2 17 A D2 S 120 0_DB 1 1_ S O
A D2 S 12 0 0_ DB 4 _u C 30 2 A3 2 B3 19 A D2 S 120 0_DB 4
A D2 S 12 0 0_ DB 3 _u C 29 2 A4 2 B4 20 A D2 S 120 0_DB 3
A D2 S 12 0 0_ DB 2 _u C 27 2 A5 2 B5 22 A D2 S 120 0_DB 2
A D2 S 12 0 0_ DB 1 _u C 26 2 A6 2 B6 23 A D2 S 120 0_DB 1
A D2 S 12 0 0_ DB 0 _u C 2 A7 2 B7 A D2 S 120 0_DB 0
V DIG 33 31 7 V DIG 50
+3.3 V 42 V CCA V CCB 18 +5.0 V
4 V CCA V CCB 28
10 G ND G ND 34
15 G ND G ND 39
21 G ND G ND 45
G ND G ND
74L V CH1 6T 24 5 DL
C11 3 2 C11 3 3
1 00 n/16 V/X 7 R 1 00 n /16 V/X 7R
G ND_DIG1
Figure 58 Level Shifter for Adapting Logic Levels for Resolver IC
V DIG33
+3.3 V
L5
M URAT A _B L M2 1P 2 21 S N
IC1 6
E H2 6 45 E TT TS -20 .0 00 M
4 1
u c_ T C1 7 67 V DC T RI
FLT _ Un 3 2
FLT _ Un P 1_ 5 Clk O UT GND
FLT _ Vn
FLT _ Vn P 1_ 6
FLT _ Wn
FLT _ Wn P 1_ 7 GPT A8 P WM UT n
GPT A9 P WM UB n
FLT _ n
FLT _ n GPT A2 0
GPT A18 P WM VT n
10n/16V/X7R
22uF/6.3V/X7R
C104
100n/16V/X7R
GPT A19 P WM VB n
C105
C106
P 1_ 9 P WM WT n
T RS Tn
T RS Tn T RS Tn
T CK
T CK T CK GPT A27 P WM WB n
V DIG33 T DI
T DI T DI
+3.3 V T DO
T DO T DO
T MS
T MS T MS
B RK OUT n
B RK OUT n B RK OUT n
B RK INn GND_DIG1
B RK INn B RK INn
R10 1 WDI
1 0K GPT A39
Rese tn
Rese tn P ORST n
RST n
RST n P 3_ 1 3
INP UT_ FIL T ER S CL K 0

M RS T0
P osA /iG MR_ A+ P osA /iG MR_ A+ P 0_ 1 2 P 0_ 1 2 M TS R0
P osA /iG MR_ A- P osA /iG MR_ A- P 0_ 1 4 P 0_ 1 4 S LS O0
P osB /iG MR_ B+ P osB /iG MR_ B+ P 0_ 1 1 P 0_ 1 1
EEPROM
P osB /iG MR_ B- P osB /iG MR_ B-

SO
SI
CSn
SCK
P osZ/iG MR_ Z+ P osZ/iG MR_ Z+

P osZ/iG MR_ Z- V DIG50 V DIG33
P osZ/iG MR_ Z- +5.0 V +3.3V
P osU/iG MR_ U P osU/iG MR_ U P 4_ 2 P 4_ 2 E EP RO M
P 2_ 0 P 2_ 0
P osV /iG MR_ V P osV /iG MR_ V P 2_ 2 P 2_ 2 T XDCA N1
100n/16V/X7R
22uF/6.3V/X7R
100n/16V/X7R
RXDCA N1
P osW/i G MR_ W
C108
P osW/iG MR_ W
C109
C107
T XD0 A
RXD0 A
A A P 1_ 8 P 1_ 8 P 5_ 0 A D2S 12 0 0_ DB 0 _u C
B B P 1_ 1 0 P 1_ 1 0 P 5_ 1 A D2S 12 0 0_ DB 1 _u C
NM NM P 4_ 3 P 4_ 3 P 5_ 2 A D2S 12 0 0_ DB 2 _u C
A D2S 12 0 0_ DB 3 _u C G ND_DIG1 GND_DIG1 CAN1 _H
P 5_ 3
P 5_ 4 A D2S 12 0 0_ DB 4 _u C GND_DIG1
DIO_ 1 A D2S 12 0 0_ DB 5 _u C FL1 R13 1
DIO_ 1 P 4_ 1 P 4_ 1 P 5_ 5 IC1 7
DIO_ 2 DIO_ 2 P 4_ 0 P 4_ 0 P 5_ 6 A D2S 12 0 0_ DB 6 _u C 6 0R
3
5
DIO_ 3 A D2S 12 0 0_ DB 7 _u C T LE 6 25 0 GV 33 B 82 7 89 C01 0 4N0 01

DIO_ 3 P 2_ 5 P 2_ 5 P 5_ 7 CAN_ TX 1 1
A D2S 12 0 0_ DB 8 _u C
V33V
Vcc
P 5_ 8 CAN_ RX 1 4 T xD 7 1 4
P 5_ 9 A D2S 12 0 0_ DB 9 _u C RxD CANH 6
A D2S 12 0 0_ DO S _u C R13 3
V DC_ uC V DC A N2 9 A N2 9 P 5_ 1 2 5 K1 8 CANL C11 0
GND
P 5_ 1 3 A D2S 12 0 0_ L OT _u C INH 2 3
T EM P_ IGB T _U A D2S 12 0 0_ RDV EL n _u C R13 2 4 .7n /50 V /X 7 R
T EM P_ IGB T _U A N1 A N1 P 5_ 1 5
T EM P_ IGB T _V T EM P_ IGB T _V A N2 A N2 P 3_ 1 0 A D2 S 12 0 0_ RE S ET n _u C 6 0R
T EM P_ IGB T _W A D2S 12 0 0_ FS1 _u C G ND_DIG1
2
T EM P_ IGB T _W A N3 A N3 P 3_ 1 1
T EM P_ B oa rd T EM P_ B oa rd A N4 A N4 P 3_ 1 2 A D2S 12 0 0_ FS2 _u C
S ta to rT e mp S ta to rT e mp A N5 A N5 CAN1 _L
GND_DIG1
I_ U I_ U A N1 5 A N1 5
I_ V I_ V A N1 4 A N1 4 IC5 2
I_ W I_ W A N1 3 A N1 3 GPT A3 A D2S 12 0 0_ SA M PL E_ u C
M AX 32 3 2E IPWRQ1 C11 1
100n/16V/X7R
A N3 1 A N3 1 1 2
C1+ V+
C112
A DC_ IN1 A DC_ IN1 A N1 7 A N1 7 3 1 00 n /16 V/X 7R

A DC_ IN2 A DC_ IN2 A N1 8 A N1 8 P 5_ 1 1 A D2 S 12 0 0_ DB 1 1_ S O_ u C C1- C11 3
100n/16V/X7R
A DC_ IN3 A DC_ IN3 A N1 9 A N1 9 P 5_ 1 0 A D2 S 12 0 0_ DB 1 0_ S CL K _u C 4 6

V DIG33 C2+ V-
C114
+3.3 V
5 1 00 n /16 V/X 7 R
C2- GND_DIG1
T XDOA R13 4 11 14
S W2 A SCTX
In pu t_Fil ter 10 T 1in T 1o u t 7
S W DIP -4 /S M T 2in T 2o u t 1 3
RXDOA 12
9 R1o u t R1in 8 A SCRX
R13 5
1K R2o u t R2in 1K V DIG33
+3.3 V
GND_DIG1 GND_DIG1
iGMR 15 16
100n/16V/X7R
i GM R S e ri a l M od e /E n co d er Mo d e: GND V cc
( sw i tc h p i n 1 o p en (O F F) ) - > i G MR _ IN D EX _ uC lo w i GM R_INDE X_ u C
C115
A D2 S 12 0 0_ SO E _u C
i GM R d i sa b le d : ( sw i tc h p i n 1 c l os e d ( ON ) ) S ERIAL _ PA RA L LE L _M ODE _u C
S CL K 1 i GM R_CLK _ uC
M RS T1 i GM R_ROUT _u C
R es o lv e r S er i al (2 , 3, 4 i s O N )
- u C _T C 17 6 7. S CL K 1 d ri v es A D2 S 12 0 0_ CS n _u C GND_DIG1
S LS O1
- M R ST 1 a s i n pu t , d ri v en by Re s ol v er S LS O2 i GM R_CS_ u C
- S E RI A L_ P AR A LL E L_ M OD E _u C i s P 3_ 8 i GM R_RE_ u C
De f au l t i s s er i al mo d e P 2_ 1 2 i GM R_DI_u C
- A D 2S 1 20 0 _C S n_ u C
u c_ T C1 7 67
Figure 59 Microcontroller

G ND_DIG1 V DIG 50
Temperature and DC Bus Measurements General Purpose Analogue IN Encoder Inputs/iGMR Inputs +5.0 V
C11 6 0
R18 0
V ANA5 0 (iGMR Emulates Encoder) G ND_DIG1 P 0_ 1 2
+5.0 V
1K
16
R19 1 IC3 3 1 00 n /16 V/X 7 R R18 3
C10 4 3 C10 4 4 C10 4 5 4 2K
T EM P_ IGB T _U A N1
Vcc
G+
R17 7 1 0p /5 0V /X7 R 1 0p /5 0V /X7 R 1 0p /5 0V /X7 R1 2 G-
6 8K C18 0 1 0K
C10 4 0 R42 9 2
R19 4 1 n/5 0 V/X 7R P osA /iG MR_ A+ G ND_DIG1
o pt 1 A+ 3
ADC_ IN1 A N1 7 1 1Y
R17 8 P osA /iG MR_ A-
5 1K C17 3 1 0p /5 0V /X7 R 1 00 R 1 B-
C10 41 R43 0 6
G ND_A NA1 R18 1 1 n/5 0 V/X 7R P osB /iG MR_ B+ R18 7
R19 8 o pt 2 A+ 5
7 2Y P 0_ 1 4
T EM P_ IGB T _V A N2 V ANA5 0 P osB /iG MR_ B-
+5.0 V 1 0p /50V /X7 R 1 00 R 2 B- 1K
C10 4 2 R43 1 10
6 8K C18 3 G ND_A NA1 P osZ/iG MR_ Z+ R19 0
R20 2 1 n/5 0 V/X 7R 3 A+ 11 2K
o pt R18 6 9 3Y
P osZ/iG MR_ Z- 3 B-
1 0K 1 0p /5 0V /X7 R
R18 8 1 00 R 14 G ND_DIG1
G ND_A NA1 4 A+ 13
ADC_ IN2 A N1 8 15 4Y
R20 5 C11 47 C11 4 8 C11 4 9
5 1K C17 8 4 B- R19 7
1 0p /5 0V /X7 R 1 0p /5 0V/X7 R 1 0p /5 0V /X7 R
GND
T EM P_ IGB T _W A N3
R19 2 1 n/5 0 V/X 7R P 0_ 1 1
6 8K C18 7 o pt
R20 8 1 n/5 0 V/X 7R V ANA5 0 A M2 6C3 2Q D 1K
8
o pt +5.0 V R20 1
G ND_A NA1 2K
VANA5 0
R17 4
+5.0 V G ND_A NA1 R19 5
1 0K 1 0K G ND_DIG1 G ND_DIG1
R17 5 R19 9
S ta to rT emp A N4 ADC_ IN3 A N1 9
V DIG33
6 8K C17 2 5 1K C18 4 Hall Sensor/iGMR Inputs (iGMR Emulates Hall Sensor) +3.3 V
R17 6 1 n/5 0 V/X 7R R20 3 1 n/5 0 V/X 7R
o pt o pt Assumed Open-Collector output from Hall sensor
G ND_A NA1 G ND_A NA1
R49 1 R49 2 R49 3
2 K7 2 K7 2 K7
T EM P_ B oa rd A N5
R49 4
P osU/iG MR_ U P 4_ 2
D7 C12 13
1K B AT 5 4-0 4W o pt
R18 4
V DC A N2 9
G ND_DIG1
R49 5
6 8K C17 6
R18 5 1 n/5 0 V/X 7R P osV /iG MR_ V P 2_ 0
o pt
D8 C12 14
1K B AT 5 4-0 4W o pt
G ND_A NA1
G ND_DIG1
R49 6
V ANA5 0 P osW/i G MR_ W P 2_ 2
+5.0 V
Phase Current Sense General Purpose 1K
D9 C12 15
BAT 5 4-0 4W o pt
Digital IN/OUT
L 12
R21 5 M URAT A _B L M2 1P G 22 1 SN R17 9 Emulated encoder outputs out of AD2S1200
G ND_A NA1 DIO_ 1 P 4_ 1 R23 4 G ND_DIG1
C11 6 1
IC3 1 A A P 1_ 8
3 K3 L T1 6 39 HS G ND_A NA1 5 1K C17 4
4
R21 4 R21 7 R18 2 1 00 p /50 V/X 7 R 1K

1 00 n /16 V/X 73R V+ P ACKA G E = 1 9 1K R23 7
I_ U + 1
C10 6 4 AN1 5 2K G ND_DIG1
6 K8 6 K8 3 30 0 p/1 0 V/C0G 2
- V-
C19 1 R47 7 R47 8 GND_DIG1
6 80 0 p/1 0 V/C0G G ND_DIG1
11
G ND_A NA1
G ND_A NA1 o pt 0R R23 8
R18 9 B P 1_ 1 0
R47 2 DIO_ 2 P 4_ 0
G ND_A NA1 1K
G ND_A NA1 5 1K C17 9 R23 9
3 K3 IC3 1 B P ACKA G E = 1 R19 3 1 00 p /50 V/X 7 R 2K
R22 3 R22 8 L T1 6 39 HS A N1 4 9 1K
5 R22 4
I_ V + 7
C10 6 5 G ND_DIG1
6 K8 6 K8 3 30 0 p/1 0 V/C0G 6 GND_DIG1 R24 0
-
C19 4 R48 0 R47 9 0 R_ o pt NM P 4_ 3
6 80 0 p/1 0 V/C0G R22 9 R19 6
G ND_A NA1
G ND_A NA1 o pt 0R DIO_ 3 P 2_ 5 1K
R24 1
R21 8 0R A N3 1 5 1K C18 2 2K
G ND_A NA1 R20 0 1 00 p /50 V/X 7 R
9 1K
3 K3 IC3 1 C P ACKA G E = 1 G ND_DIG1
R23 0 R23 5 L T1 6 39 HS
10 GND_DIG1
I_ W + 8
C10 6 7 AN1 3
6 K8 6 K8 3 30 0 p/1 0 V/C0G 9
- G ND_A NA1
C19 6 R48 1 R48 2
6 80 0 p/1 0 V/C0G IC3 1 D P ACKA GE = 1
G ND_A NA1
G ND_A NA1 o pt 0R L T1 6 39 HS
12
+ 14
13
-
Figure 60 Input Filter

V ANA5 0 V ANA3 3 V ANA1 5 V ANA3 3 V re f5 0 G ND_A NA1 IC2 4 F

+5.0 V +3.3 V +1.5 V +3.3 V +5.0 V S AK -TC1 76 7 -2 5 6F1 33 HL IC2 4 G
IC2 4 E A na l og Inp u ts G ND_A NA1 S AK -TC1 76 7 -2 5 6F1 33 HL
S AK -TC1 76 7 -2 5 6F1 33 HL 67 48 P ort 0: G PT A , S CU
A na l og P owe r S up p l y 66 A N0 A N1 6 4 7 CFG 0 1 45
54 52 A N1 65 A N1 A N1 7 4 6 A N1 7 1 46 P 0.0 /IN0 /HWCFG 0/O UT 0/O UT 5 6
CFG 1
24 V _DDM V _A REF0 26 A N2 64 A N2 A N1 8 4 5 A N1 8 1 47 P 0.1 /IN1 /HWCFG 1/O UT 1/O UT 5 7
CFG 2
23 V _DDMF V _FA RE F A N3 63 A N3 A N1 9 4 4 A N1 9 1 48 P 0.2 /IN2 /HWCFG 2/O UT 2/O UT 5 8
CFG 3
47n/16V/X7R
V _DDAF A N4 62 A N4 A N2 0 4 3 G PT A3 1 66 P 0.3 /IN3 /HWCFG 3/O UT 3/O UT 5 9
CFG 4
V_FAGND
V_AGND0
A N5 61 A N5 A N2 1 4 2 1 67 P 0.4 /IN4 /HWCFG 4/O UT 4/O UT 6 0
V_SSMF
C14 8 V_SSM C14 9 CFG 5
C146
1 00 n /16 V/X 7 R 1 00 n /16 V/X 7 R 36 A N6 A N2 2 4 1 CFG 6 1 73 P 0.5 /IN5 /HWCFG 5/O UT 5/O UT 6 1
47n/16V/X7R
47n/16V/X7R
A N7 A N2 3 CFG 7 1 74 P 0.6 /IN6 /HWCFG 6/REQ 2/O UT 6 /OUT6 2

60 40 1 49 P 0.7 /IN7 /HWCFG 7/REQ 3/O UT 7 /OUT6 3
G ND_A NA1 G PT A8
C147
59 A N8 A N2 4 3 9 1 50 P 0.8 /IN8 /OUT8 /OUT 64

G PT A9
C145
53
25
51
27
58 A N9 A N2 5 3 8 1 51 P 0.9 /IN9 /OUT9 /OUT 65

P ackag e = 1 G ND_A NA1 A N1 0 A N2 6 3 7 P 0.1 0/IN10 /OUT 10 /OUT 66
57 1 52
56 A N1 1 A N2 7 3 5 P 0_ 1 1 1 68 P 0.1 1/IN11 /OUT 11 /OUT 67
G ND_A NA1 G ND_RE F1 P 0_ 1 2
55 A N1 2 A N2 8 3 4 1 69 P 0.1 2/IN12 /OUT 12 /OUT 68
A N1 3 50 A N1 3 A N2 9 3 3 A N2 9 1 75 P 0.1 3/IN13 /OUT 13 /OUT 69
G ND_A NA1G ND_A NA1 G ND_A NA1 A N1 4 P 0_ 1 4
49 A N1 4 A N3 0 3 2 1 76 P 0.1 4/IN14 /REQ 4/O UT 1 4/O UT 7 0
A N1 5 A N1 5 A N3 1 A N3 1 P 0.1 5/IN15 /REQ 5/O UT 1 5/O UT 7 1
G ND_RE F1 31 29
A N3 2 A N3 4 2 8 P ackag e = 1
30
G ND_A NA1 A N3 3 A N3 5 G ND_A NA1
G ND_A NA1 P ackag e = 1
IC2 4 H
P ort 1: G PT A , S SC1 , A DC0 , OCDS IC2 4 J
1 16 IC2 4 I Po rt 3: G PT A, A SC0 /1 , SS C0/1 , S CU, CA N
B RK OUT n 1 19 P 1.0 /IN1 6/O UT 1 6/O UT 7 2/B RK IN/B RK O UT 1 36
P ort 2: G PT A , S SC0 /1, ML I0 , M SC0 RXD0 A
93 P 1.1 /IN1 7/O UT 1 7/O UT 7 3 74 1 35 P 3.0 /OUT8 4 /RX D0 A
G PT A1 8 98 P 1.2 /IN1 8/O UT 1 8/O UT 7 4 P 2_ 0 75 P 2.0 /IN3 2/O UT 3 2/O UT 2 8/T CL K 0 T XD0 A 1 29 P 3.1 /OUT8 5 /TX D0
G PT A1 9 1 07 P 1.3 /IN1 9/O UT 1 9/O UT 7 5 76 P 2.1 /IN3 3/T RE A DY 0 A/O UT 33 /S LS O0 3 /SL SO 1 3 S CL K 0 1 30 P 3.2 /OUT8 6 /SCLK 0
G PT A2 0 1 08 P 1.4 /IN2 0/E MG S TO P/O UT 2 0/O UT 7 6 P 2_ 2 77 P 2.2 /IN3 4/O UT 3 4/O UT 2 9/T VA L ID0 A M RS T0 1 32 P 3.3 /OUT8 7 /MRST 0
P 1_ 5 1 09 P 1.5 /IN2 1/O UT 2 1/O UT 7 7 78 P 2.3 /IN3 5/O UT 3 5/O UT 3 0/T DA T A0 M TS R0 1 26 P 3.4 /OUT8 8 /MT SR0
P 1_ 6 1 10 P 1.6 /IN2 2/O UT 2 2/O UT 7 8 79 P 2.4 /IN3 6/RCL K 0A /OUT 36 /OUT 31 S LS O0 1 27 P 3.5 /SL S O0 0/S L SO 10 /SL S O0 0 &S L SO 10
P 1_ 7 94 P 1.7 /IN2 3/O UT 2 3/O UT 7 9 P 2_ 5 80 P 2.5 /IN3 7/O UT 1 10 /OUT 37 /RRE ADY0 A S LS O1 1 31 P 3.6 /SL S O0 1/S L SO 11 /SL S O0 1 &S L SO 11
P 1_ 8 95 P 1.8 /IN2 4/IN48 /MT S R1 B/O UT 2 4/O UT 4 8 81 P 2.6 /IN3 8/RVA L ID0 A/O UT 1 11 /OUT 38 S LS O2 1 28 P 3.7 /SL S I0 1 /OUT8 9 /S L SO 0 2& SL S O1 2
P 1_ 9 96 P 1.9 /IN2 5/IN49 /MRS T1 B/O UT 2 5/ O UT 4 9 G PT A3 9 1 64 P 2.7 /IN3 9/RDA T A0 A /O UT3 9 P 3_ 8 1 38 P 3.8 /SL S O0 6/O UT 9 0/T XD1
P 1_ 1 0 97 P 1.1 0/IN26 /IN5 0 /OUT2 6 /O UT5 0 /S L SO 1 7 1 60 P 2.8 /SL S O0 4/S L SO 14 /EN0 0 1 37 P 3.9 /OUT9 1 /RX D1 A
G PT A2 7 73 P 1.1 1/IN27 /IN5 1 /SCLK 1 B/O UT 2 7/O UT 5 1 1 61 P 2.9 /SL S O0 5/S L SO 15 /EN0 1 P 3_ 1 0 1 44 P 3.1 0/O UT 9 2/REQ 0
72 P 1.1 2/IN16 /OUT 16 /AD0 EM UX 0 M RS T1 1 62 P 2.1 0/IN10 /OUT 0/M RS T 1A P 3_ 1 1 1 43 P 3.1 1/O UT 9 3/REQ 1
71 P 1.1 3/IN17 /OUT 17 /AD0 EM UX 1 S CL K 1 1 63 P 2.1 1/IN11 /OUT 1/S CL K 1A /FCL P0 B P 3_ 1 2 1 42 P 3.1 2/O UT 9 4/RXDCAN0 /RX D0 B
1 17 P 1.1 4/IN18 /OUT 18 /AD0 EM UX 2 P 2_ 1 2 1 65 P 2.1 2/IN12 /OUT 2/M TS R1A /SO P0 B P 3_ 1 3 1 34 P 3.1 3/O UT 9 5/T XDCAN0 /T X D0
B RK INn P 1.1 5/B RKIN/B RKO UT P 2.1 3/IN13 /OUT 3/S LS I1 1/S DI0 RXDCA N1 1 33 P 3.1 4/O UT 9 6/RXDCAN1 /RX D1 B
T XDCA N1 P 3.1 5/O UT 9 7/T XDCAN1 /T X D1
S AK -TC1 76 7 -2 5 6F1 33 HL P ackag e = 1 S AK -TC1 76 7 -2 5 6F1 33 HL P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL P ackag e = 1
IC2 4 L
P ort 5: G PT A , M LI0 V DIG 33
1 +3.3 V
IC2 4 K P 5_ 0 2 P 5.0 /IN2 6/IN40 /OUT 8/O UT 4 0
P 5_ 1 S W1
P ort 4: G PT A , S CU 3 P 5.1 /IN2 7/IN41 /OUT 9/O UT 4 1
86 P 5_ 2 4 P 5.2 /IN2 8/IN42 /OUT 10 /OUT 42
P 4_ 0 P 5_ 3 R49 9 1 00 k CFG 7 R16 1 1K
87 P 4.0 /IN2 8/IN52 /OUT 28 /OUT 52 5 P 5.3 /IN4 3/O UT 1 1/O UT 4 3 R50 0 1 00 k CFG 6 R16 2 1K
P 4_ 1 88 P 4.1 /IN2 9/IN53 /OUT 29 /OUT 53 P 5_ 4 6 P 5.4 /IN2 9/IN44 /OUT 12 /OUT 44
P 4_ 2 P 5_ 5 R50 1 1 00 k CFG 5 R16 3 1K
90 P 4.2 /IN3 0/IN54 /OUT 30 /OUT 54 /EX T CL K1 7 P 5.5 /IN3 0/IN45 /OUT 13 /OUT 45 R50 2 1 00 k CFG 4 R16 4 1K
P 4_ 3 P 4.3 /IN3 1/IN55 /OUT 31 /OUT 55 /EX T CL K0 P 5_ 6 8 P 5.6 /IN3 1/IN46 /OUT 14 /OUT 46
P 5_ 7 R50 3 1 00 k CFG 3 R16 5 1K
13 P 5.7 /IN4 7/O UT 1 5/O UT 4 7 R50 4 1 00 k CFG 2 R16 6 1K
S AK -TC1 76 7 -2 5 6F1 33 HL P ackag e = 1 P 5_ 8 P 5.8 /OUT8 9 /RDAT A 0B
14 R50 5 1 00 k CFG 1 R16 7 1K
P 5_ 9 15 P 5.9 /OUT9 0 /RV AL ID0B
P 5_ 1 0 R50 6 1 00 k CFG 0 R16 8 1K
16 P 5.1 0/O UT 9 1/RRE A DY 0 B
P 5_ 1 1 17 P 5.1 1/O UT 9 2/RCL K 0B
P 5_ 1 2 18 P 5.1 2/O UT 9 3/S L SO 07 /TDA TA 0
P 5_ 1 3 T yco _1 -1 57 1 98 3 -1
19 P 5.1 3/S L SO 16 /T VA LID0 B
9 P 5.1 4/O UT 9 4/T RE A DY 0 B
P 5_ 1 5 P 5.1 6/O UT 9 5/T CL K 0 G ND_DIG1
S AK -TC1 76 7 -2 5 6F1 33 HL P ackag e = 1
V DIG 15
+1.5 V
L7
V DIG 33
+3.3 V V DIG 33 B 82 4 22 A 11 0 3K
+3.3 V
C15 1
B CR1 83 S P ACKA G E = 1 1 0u /1 0V /X7 R
1
R171
4K7
Q 6A
10k
IC2 4 B V DIG 33
2 S AK -TC1 76 7 -2 5 6F1 33 HL +3.3 V
O sci l l ato r G ND_DIG1
LED_LSM676-MQ
10k
6
1 02 1 05
Clk X TA L 1 V _DDOS C 1 06 L6
1 03 V _DDOS C3 1 04
X TA L 2 V SS OS C B 82 4 22 A 11 0 3K
P ackag e = 1
D4
V DIG 33 C15 0
+3.3 V 1 0u /1 0V /X7 R
R172
220R
V DIG 33
+3.3 V G ND_DIG1
G ND_DIG1
R169
10K
IC2 4 C
S AK -TC1 76 7 -2 5 6F1 33 HL IC2 4 D
G en e ra l Co n tro l G ND_DIG1 S AK -TC1 76 7 -2 5 6F1 33 HL
1 21 1 22
R173
10K
P ORST n O CDS / JTA G Co ntro l

P ORST E SR0 1 14
1 18 1 20 T RS Tn 1 15 T RS T
T ES TM O DE E SR1 T CK 1 11 T CK /DA P 0
T DI 1 13 T DI/B RK IN
P ackag e = 1 T DO T DO /DA P2 /B RK OUT
1 12
0R_opt
T MS T MS /DA P1
R170
P ackag e = 1
G ND_DIG1
V DIG 15
V DIG 33 +1.5 V
+3.3 V IC2 4 A P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
11 10
20 V _DDP V _DD 21
69 V _DDP V _DD(S B ) 68
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
83 V _DDP V _DD 84
91 V _DDP Dig i tal Ci rcu i try V _DD 89
1 00 V _DDP V _DD 99
1 24 V _DDP V _DD 1 23
1 39 V _DDP P owe r S up p l y V _DD 1 53
1 54 V _DDP V _DD 1 70
1 71 V _DDP V _DD 1 41
C1110
C160
C163
C164
C165
C166
C167
C168
C169
C170
C152
C153
C154
C155
C156
C157
C158
C159
C171
V _DDP V _DDFL 3
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
G ND_DIG1
22
70
85
12
82
92
101
125
140
155
172
G ND_DIG1 V DIG 33
+3.3 V
G ND_DIG1 C16 1
1 00 n /1 6 V/X 7 R
G ND_DIG1
Figure 61 Microcontroller TC1767 Pin Assignment

V DIG 33
+3.3 V
R7 R8
1 0K 1 0K R9
1 0K
IC1
100n/16V/X7R
8 6
4 V CC S CK 5 S CK
G ND SI 2 SI
7 SO SO
C29
3 HOL D 1
WP CS CSn
A T2 5 25 6 A-1 0T Q -2 .7
R10
o pt
GND_DIG1
Figure 62 EEPROM
V DIG 33
+3.3 V
C11 2 7 G ND_DIG1
G ND_DIG1
C11 2 8
1 00 n /1 6 V/X 7 R 1 0p /16 V /X7 R
8
IC2 6 DS9 2 LV 01 0 i GM R_ DAT A +

VCC
2 V DIG 33
i GM R_ DI_u C 3 DIN 7
i GM R_ ROUT _u C R44 7 +3.3 V
ROUT DO/RI+ 6
DO/RI- 1 00 R
1
GND
5 DE C11 2 9
i GM R_ INDE X_ u C RE
i GM R_ DAT A - GND_DIG1
4
R48 8 C11 3 0
1 00 n /1 6 V/X 7 R
16
1K 1 0p /16 V /X7 R IC3 2
G ND_DIG1
Vcc
G ND_DIG1 4
EN
G ND_DIG1 12
E N*
2
1 Dou t1+ i GM R_ CLK +
i GM R_ CLK _ uC Din 1 3
Dou t1- i GM R_ CLK -
6
7 Dou t2+ i GM R_ REn _ DE +
Din 2 5
Dou t2- i GM R_ REn _ DE -
V DIG 33
+3.3 V 10
9 Dou t3+ i GM R_ CSn +
Din 3 11
C11 3 1 Dou t3- i GM R_ CSn -
14
G ND_DIG1 15 Dou t4+
Din 4 13
1 00 n /1 6 V/X 7 R Dou t4-
GND
5
IC2 8 7 4L V C2 G0 4 GW
VCC
1 6
i GM R_ RE_ u C
8
1A 1Y
3 4 DS9 0 LV 03 1 A
GND
i GM R_ CS_ u C 2A 2Y
G ND_DIG1
2
R48 9 R49 0
1K 1K
G ND_DIG1
GND_DIG1 G ND_DIG1
Figure 63 GMR SSC Interface
V ANA5 0 U ni t t e mp e ra t ur e s e ns o r ( Am b ie n t)
+5.0 V P os i ti o n: bo t to m o f L o gi c B o ar d
T em p = 10 m V/ ° C + 5 0 0m V
T em p @ -4 0 C: +1 0 0m V
T em p @ +1 2 5C : + 1 ,7 5 0V
L PF : - 3 dB @ 3 2H z
1
IC5 4
100n/50V/X7R
V CC R48 7
2
C1211
V ou t T em p_ B oa rd
G ND 2 70 K
L M5 0 CIM3
3 C12 1 2
2 2n /5 0V /X7 R
G ND_A NA1
Figure 64 Temperature Sense of the Logic Board

K L_ 3 0
+12 .0 V K L_ 3 0
K1 +12 .0 V
1 2
3 1 2 4
5 3 4 6 G ND_DIG1
G ND_A NA1 GND_DIG1 7 5 6 8
9 7 8 10
V DC 11 9 10 12 T EM P_ HP2 _ U
13 11 12 14 RST _ INn
FLT Wn 15 13 14 16 P WM WT
T EM P_ HP2 _ W 17 15 16 18 P WM WB
FLT V n 19 17 18 20 P WM VT
T EM P_ HP2 _ V 21 19 20 22 P WM VB
FLT Un 23 21 22 24 P WM UT
FLT n 23 24 P WM UB
T W-1 2-0 6-L -D-4 7 5-S M-A
Figure 65 Connector to the Driver Board
4.13.2 Assembly Drawing
Figure 66 Assembly Drawing of the Logic Board (Top)

Figure 67 Assembly Drawing of the Logic Board (Bottom)

For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 66 and
Figure 67.
4.13.3 Layout
Layout of the Logic Board is shown on Figure 68 (Top Layer), on Figure 69 (Layer-2), on Figure 70 (Layer-3), on
Figure 71 (Layer-4), on Figure 72 (Layer-5) and on Figure 73 (Bottom Layer).

Figure 68 Logic Board - Top Layer
Figure 69 Logic Board - Layer-2


Figure 73 Logic Board - Bottom Layer

4.13.4 Bill of Materials
Table 7 Bill of Materials for Logic Board for Hybrid Kit for HybridPACK™1
C29,C64,C68,C70,C71,C106,C107,C109,C11 100n/16V/X7R C0402
1,C112,C113,C114,C115,C123,C148,C149,C
152,C153,C154,C155,C156,C157,C158,C159,
C160,C161,C163,C164,C165,C166,C167,C16
8,C169,C170,C171,C1110,C1210
C65,C66,C1127,C1129,C1131,C1132,C1133, 100n/16V/X7R C0603
C1160,C1161,C1163,C1164
C75 4u7/16V/X7R C1206
C76,C77,C80,C81,C104 10n/16V/X7R C0402
C78 10uF/10V/X7R C1206
C79,C82 4u7/25V/X7R C1206
C83,C84 20pF/50V/COG C0402
C85,C1151,C1153 100n/50V/X7R C0603
C86,C1135,C1136,C1154,C1155 22u/16V/X7R/F_1463575 C1210
C92 220nF/100V/C3216X7R2A2 C1206
24KT5
C93,C1152 100uF_35V_MAL21409700 C1010_CAP_Pin1_Plus
1E3
C105,C108 22uF/6.3V/X7R C1206
C110 4.7n/50V/X7R C0603
C143,C1111 22uF/16V/X7R C1210
C144 100n/25V/X7R C0603
C145,C146,C147 47n/16V/X7R C0402
C150,C151,C1157,C1158 10u/10V/X7R C1206
C172,C173,C176,C178,C180,C183,C184,C18 1n/50V/X7R C0402
7,C1169,C1170,C1171,C1173,C1174,C1175,
C1176,C1177,C1178,C1179,C1180,C1183,C1
184,C1185,C1189,C1190,C1191,C1192,C119
3,C1194,C1195,C1196,C1197
C174,C179,C182 100p/50V/X7R C0402
C191,C194,C196 6800p/10V/C0G C0603
C1040,C1041,C1042,C1043,C1044,C1045,C1 10p/50V/X7R C0603
147,C1148,C1149
C1064,C1065,C1067 3300p/10V/C0G C0603
C1112,C1167 100n/50V/X7R/C0805F104 C0805
K5
C1128,C1130 10p/16V/X7R C0603
C1142 4u7/10V/X7R C1210

Table 7 Bill of Materials for (cont’d)Logic Board for Hybrid Kit for HybridPACK™1
C1144,C1146 4u7/10V/X7R/F_9402195 C1206
C1145 1u/25V/X7R/F_1637035 C0603
C1150 680n/50V/F_1414702 C1206
C1156 220n/25V/X7R/F_1414626 C0603
C1159 1n/16V/X7R C0402
C1166 4.7u/50V/X7R/C1210F475K C1210
5
C1172,C1181,C1182,C1187,C1188,C1201,C1 1n/50V/X7R_opt C0402
202,C1203,C1204,C1205,C1206,C1207,C120
8,C1209
C1211 100n/50V/X7R C0805
C1212 22n/50V/X7R C0603
R10,R103,R105,R107,R109,R110,R176,R181 Opt R0603
,R185,R192,R194,R202,R203,R208,R477,R4
80,R481,C1213,C1214,C1215,C1216,C1217
D1 MBRS340T3 SMC
D2 BZV55/C13 SOD80C_Pin1_Cathode
D3 1SMB30AT3 SMB
D4 LED_LSM676-MQ Vishay_TLMK2300
D5,D6 SS12_1A_If_20V_Vr DO214AC_SMA_Pin1_Cathode
D7,D8,D9 BAT54-04W SOT323
FL1 B82789C0104N001 EPCOS_B82789C0
IC1 AT25256A-10TQ-2.7 TSSOP8
IC2 74ALVC164245DGG TSSOP48
IC4,IC31 LT1639HS SO14
IC6 LMH6672 SO8
IC8 AD2S1200YST LQFP44_P0_8
IC13 TLE7368E SO36-38
IC16 EH2645ETTTS-20.000M Ecliptek_EH2645
IC17 TLE6250GV33 SO8
IC23 MAX6369KA-T SOT23-8
IC24 SAK-TC1767-256F133HL LQFP176_p0_50
IC25 TLE4266GSV10 SOT223
IC26 DS92LV010 SO8
IC28,IC30 74LVC2G04GW SOT363
IC29 74LVCH16T245DL SSOP48
IC32 DS90LV031A SO16-1
IC33 AM26C32QD SO16-1
IC52 MAX3232EIPWRQ1 TSSOP16

IC53 MAX6143AASA50 SO8
IC54 LM50CIM3 SOT23
J1 Jumper Jumper_2way
K1 TW-12-06-L-D-475-SM-A Samtec_TW-12-06-L-D-475-SM-
A
K2 Harwin M80-5125042P Harwin_M80-5125042P
K3-OCDS HEADER 8X2 tyco_1761686-6
L1,L8,L9,L10,L11,L12 MURATA_BLM21PG221SN L0805
L3 WE_7447709470 WE-PD_744770
L5 MURATA_BLM21P221SN L0805
L6,L7 B82422A1103K L1210
Q2 BDP949 SOT223
Q4 IPD90P03P4L-04 TO252-3
Q6 BCR183S SOT363
R1,R2,R3,R4,R5,R6,R7,R8,R9,R71,R73,R173 10K R0402
,R174,R177,R186,R195,R471,R473,R474,R4
75,R476
R74,R75,R76,R77,R78,R79,R80,R88,R92,R9 1K R0402
5,R98,R100,R134,R135,R161,R162,R163,R1
64,R165,R166,R167,R168,R180,R187,R197,
R234,R238,R240,R456
R90,R93,R96,R99 15K R0402
R101,R128,R169 10K R0603
R102,R104,R106,R108,R478,R479,R482,R49 0R R0603
7
R113 SMK-R000 / Isabellenhuette R1206
R131,R132 60R R0603
R133 5K1 R0402
R149,R154 Opt R0402
R150,R151,R153 4K7 R0402
R155,R156,R158,R160 2K4/0.1% R0603
R157 390/0.1% R0603
R159 3K3/0.1% R0603
R170,R224,R498 0R_opt R0603
R171 4K7 R0603
R172 220R R0603
R175,R184,R191,R198,R205 68K R0402
R178,R179,R188,R189,R196,R199 51K R0402
R182,R193,R200 91K R0402
R183,R190,R201,R237,R239,R241 2K R0402

R214,R217,R223,R228,R230,R235 6K8 R0402
R215,R218,R472 3K3 R0402
R229 0R R0402
R429,R430,R431,R447 100R R0603
R483,R484,R485 5K_pot_0,25W_20%_Bourn Bourns_3314J
s_3314J_opt
R486 0R / 0.1% R0402
R487 270K R0603
R488,R489,R490,R494,R495,R496 1K R0603
R491,R492,R493 2K7 R0603
R499,R500,R501,R502,R503,R504,R505,R50 100k R0402
6
SW1 Tyco_1-1571983-1 Tyco_1-1571983-1
SW2 SW DIP-4/SM SO8
TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9 Testpad_SMD_Ettinger Ettinger_12_18_815_testpad
U1 HCM49 8.192MABJ-UT Citizen_HCM49

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HybridPACK™

Hybrid Kit for HybridPACK™1

Evaluation Kit for Applications with

Hybrid Kit for HybridPACK™1

Revision History: 2010-04, V2.0

Trademarks of Infineon Technologies AG

Application Note 3 V2.0, 2010-04

Application Note 4 V2.0, 2010-04

4.6 Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Application Note 5 V2.0, 2010-04

Figure 1 The Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Application Note 6 V2.0, 2010-04

Figure 49 Picture of Possible Physical Implementation of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 49

Application Note 7 V2.0, 2010-04

Table 1 Key Data of DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application Note 8 V2.0, 2010-04

1.1 How to Order Hybrid Kit for HybridPACK™1

Figure 1 The Hybrid Kit for HybridPACK™1

Application Note 9 V2.0, 2010-04

1.2 Support for Hybrid Kit for HybridPACK™1

Figure 2 Serial number in the suitcase

Application Note 10 V2.0, 2010-04

Debug Logic Board

IGBT driver IGBT driver IGBT driver

Current U CAN RS232 A/D IO Supply

Figure 3 Block Diagram of Hybrid Kit for HybridPACK™1

2.1 Main Features

Application Note 11 V2.0, 2010-04

Application Note 12 V2.0, 2010-04

2.3 Key Components

2.3.1 Driver Board (6ED100HP1-FA)

2.3.2 Logic Board

Figure 6 HybridPACK™1 IGBT Six-Pack Module

Application Note 13 V2.0, 2010-04

2.3.4 DC-Link Capacitor

Figure 7 DC-Link Capacitor for HybridPACK™1

Table 1 Key Data of DC-Link Capacitor

Climatic Category Design Data Mean Life Expentancy

Application Note 14 V2.0, 2010-04

Figure 8 Technical drawing of the DC-Link Capacitor

Application Note 15 V2.0, 2010-04

2.3.5 Cooling Element

Figure 9 Example of Water Cooling Element for HybridPACK™1

Figure 10 Water Cooling System Technical Drawings

Application Note 16 V2.0, 2010-04

Evaluation Driver Board for the HybridPACK™1

3 Evaluation Driver Board for the HybridPACK™1

Figure 11 Driver Board Mounted on the Top of the HybridPACK™1 Module

3.1 Main Features

Application Note 17 V2.0, 2010-04

Evaluation Driver Board for the HybridPACK™1

3.2 Key Data

Table 2 Key Data and Characteristic Values (Typical Values)

3.3 External Connector Pin Assignment

Application Note 18 V2.0, 2010-04

Evaluation Driver Board for the HybridPACK™1

Figure 12 External Connector on the Driver Board

3.4 Mechanical Dimensions of the Driver Board

Figure 13 Dimensions of the Driver Board (in mm)

Application Note 19 V2.0, 2010-04

Evaluation Driver Board for the HybridPACK™1

Figure 14 PCB Mounting Stand-offs of HybridPACK™1

3.5 Operation of the Driver Board