A Digital PFC Controller without

Input Voltage Sensing

Barry Mather, Bhaskar Ramachandran and Dragan Maksimovic
Colorado Power Electronics Center, ECE Department, University of Colorado, Boulder, CO 80309-0425
B arry.Mather, B haskar.Ramachandran, Dragan.Maksimovic I @ colorado.edu

L i(t)
Abstract- This paper introduces a novel digital PFC (DPFC)
control approach that requires no input voltage sensing or
current loop compensation, yet results in low-harmonic operation
over a universal input voltage range and loads ranging from
high-power operation in continuous conduction mode down to
near-zero load. The controller is based on low-resolution DPWM
and A/D converters, requires no microcontroller or DSP
programming, and is well suited for a simple, low-cost
integrated-circuit realization, or as an HDL core suitable for
integration with other power control functions. Experimental
verification results are shown for a 500 W boost PFC rectifier.

LINTRODUCTION
Power factor correction (PFC) boost rectifiers are used in a
wide range of applications that are required to meet the
EN61000-3-2 standard. At low-to-medium power levels, the
transition-mode control (i.e. critical conduction mode, or
operation at the boundary of continuous conduction mode
(CCM) and discontinuous conduction mode (DCM)), which
offers simplicity and performance advantages, is widely used
and supported by a range of commercially available low-cost
controllers. At higher power levels (above several hundred
Watts), CCM operation is often preferred because of lower
conduction losses and reduced EMI filtering requirements.
Averaged current mode control in combination with a slow
voltage control loop and a multiplier, which is a well-known
control approach for CCM PFC, requires a more complex
implementation compared to the transition-mode control. With
the motivation of simplicity comparable to transition-mode or
DCM operation, together with low-harmonic, low conduction
loss, and low EMI performance in CCM, the nonlinear-carrier
(NLC) control technique was introduced in [1, 2]. This
technique eliminated the needs for input voltage sensing,
current loop compensation, and a precision analog multiplier.
Variations in the implementation of the analog NLC control
approach have been reported in [3-6], and are now used in
commercially available controllers [7, 8].
Digital PFC controllers, offering improved system interface,
power management features, support for multi-module
operation, and improved voltage-loop dynamic responses,
have recently received increased attention. Most of the digital
PFC control techniques reported so far have been based on
DSP or microcontroller implementations (e.g. [9-19]), or have
relied on multiple current samples per switching period
Fig. 1: DPFC controlled boost rectifier
The purpose of this paper is to introduce a novel digital PFC
(DPFC) control approach based on a simple current control
law that allows operation in CCM without input voltage
sensing. Further objectives are to show how low-harmonic
operation over a universal input voltage range and a wide
range in power can be achieved using low-resolution A/D
converters, a low-resolution digital pulse-width modulator
(DPWM) and minimal digital hardware. Figure 1 shows a
block diagram of the boost converter with the proposed DPFC
controller.
The paper is organized as follows: Section II introduces the
DPFC current control law. Section III describes the voltage
regulation loop and addresses mitigation of limit-cycling
oscillations related to quantization of power. Section IV
discusses system implementation, quantization issues and
experimental results for a 500 W boost DPFC rectifier.
Conclusions are given in Section V.
II. DIGITAL PFC CURRENT CONTROL LAW
With reference to Fig. 1, in a PFC rectifier the current
control objective can be written as: ig= VgIRe, where vg is the
rectified line voltage, ig is the low-frequency (average)
component of the inductor current, and Re is the emulated
resistance, Re = Vg,rmIs2P (P is the input power) [22]. Using the
quasi-static relationship for the CCM boost converter,
VOU(P-d) = vg, where d is the switch duty ratio, the current
control objective can be expressed as
9 (I d) Voutp
(I ) -(1-d)
=
(1)
Re V.,2 rms
u

[20, 21]. where

1-4244-0714-1/07/$20.00 C 2007 IEEE. 198

 =
VoutP
2
grms =-

d[n] = 1- uig [n] = 1- ui[n]

R
VOut
e

takes the role of a power control signal. In analog NLC

approaches [1, 2], (1) is solved using a voltage comparator by
constructing a carrier waveform based on d -X t/T,. A different
approach, better suited for digital realization follows by
solving (1) for the duty cycle command d[n] directly as a
function of the current sample i[n]=ig[n], where i[n] represents
a sample of the inductor current ideally in the middle of the
switch on time or in the middle of switch off time, and u is the
power control signal:

Equation (3) is the basic version of the proposed DPFC

current control law. Note that (3) requires no input voltage
sensing or compensation in the current control loop. Figure 2
shows experimental waveforms illustrating operation of a
DPFC controller based on (3). The current A/D conversion
start (CONVST) and end of conversion (EOC) signals show
(2)

(3)
3-.

4-.

T(z=Gd
Ch3
..
...............OOV ..Ch2

.10VUo
SW- CH2
5.00 v w Ch4

(z) Gi,(z)=
5.006 V
.CONVh

Bw M 2. 00p's Ch3
5.00 V w

L2K1critz

where Kcrit = ReTJI2L is a parameter that determines the

operating mode (CCM or DCM) of the boost converter in the
fijI
Fig. 2: Experimental waveforms illustrating operation of the
boost PFC based on the DPFC current control law (3)
RT 1

PFC rectifier [22]. Based on (7), stability of the current control

loop can be examined using root locus with Kcrit as a gain
1
T-

2.2 v

I
I

(7)

how the inductor current is sampled in the middle of the parameter, as shown in Fig. 3(a). The root locus shows that the
switch off time (as in [18, 23]) and the duty cycle command current loop is stable (i.e. has a pole inside the unit circle) as
d[n] is then updated based on the current sample. A triangle- long as Kcrit < 1, which is the same condition that characterizes
wave DPWM facilitates current sampling in the middle of the the PFC boost operating in CCM over the entire line cycle
switch off time (or in the middle of the switch on time). [22]. In conclusion, the current loop based on (3) is small-
A. Stability of the current control loop signal stable at high power levels when the converter always
operates in CCM. At lower power levels, the boost converter
In this section, examine small-signal stability of the
we operates in DCM around the zero crossings of the ac line, and
current control law (3) starting from a discrete-time model in CCM around the peak of the ac line. Instability of the
based on the quasi-static approximation, i.e., assuming that the current loop in such CCM operation typically manifests itself
input voltage Vg and the output voltage Vou, can be considered as current period-doubling, which may be tolerated. It is
constant on the time scale of several switching periods T, nevertheless of interest to investigate modifications of the
From the large-signal relationship [23], current control law to achieve stable operation in CCM at
lighter loads, i.e. for larger values of Kcrit. In particular, we
i[n + 1] = i[n] + g
T - out (1 - d[n])T(4) considered a control law based on a weighted sum of two
current samples,
a small-signal discrete-time relation yields the control-to- d[n] 1-uig[n] =1 -u( i[n]+(1-a)i[n-1]) (8)
current transfer function:
The maximum stable Kcrit value is attained when cx = 0.75.
Gid (Z) -V L0 Ts (5) The corresponding root locus shown in Fig. 3(b) indicates
z-1
d() current loop stability for Kcrit < 2. This effectively extends the
range of stable operation from Kcrit < 1 to Kcrit < 2, or down to
Linearization of (3) gives the effective current-loop half of the power level at which the converter starts operating
compensator transfer function:

Gic(z)= d(z) -u (6)

i (z)

Combining (2), (5) and (6), we obtain the effective discrete-

time current control loop gain,

Fig. 3a. Fig 3b.

199 Fig. 3: Root-locus of T(z) for (3a) the current control law given in (3),
and (3b) the current control law in (8) for cx = 0.75
 in DCM for a portion of the line period than previously. At
even lighter loads, the converter is in DCM most of the time.
B. Operation at light loads
At very light loads the converter will operate in DCM during
the entire input voltage line cycle. To maintain voltage
regulation in light load conditions a further modification is
added to the current control law,
d[n] = dmax -u (a i[n] + (1 - a)i[n -1]) (9)
At light loads, the power control command u saturates at Umax
which is set based on stability criteria. Beyond this point,
further reductions in power are accomplished by reducing the
maximum duty cycle, dmax. At higher power, when u < umax,
dmax is equal to 1, thus reducing the control law (9) back to (8)
(or (3)). This modification makes voltage regulation possible
down to essentially zero load even for high input voltage
levels, at the expense of somewhat increased current distortion
at such light loads.
III. VOLTAGE REGULATION AND POWER CONTROL
A block diagram of the boost rectifier with the complete
DPFC controller is shown in Fig. 4. Based on the sampled
output voltage error, the voltage loop controller G, computes
the power control signal u[n]. As described in the previous
section, as the power is reduced, the command u saturates at
Umax = 0.5 for (3). Control through dmax then enables power
control down to zero load.
Figure 5 shows a small-signal model of the power stage
obtained by averaging over half line cycle [22], for the DPFC
current control law described in Section II. This model is used
to design a standard slow voltage loop control where G, can
be a simple linear PI compensator. To remove the need for
synchronization to the ac line, and to facilitate extensions of
d dithering through XA modulation removes undesirable
l l fii[n] ~~~~~~~~~~~~~Voltage-loopl
.
. ~~~~~~~~compensator
d- DPFC Umx
S ~~~~CDurrFent T9 7 \), CC
n
Control Law Umin|
I 1 Digital PFC Controller
Fig. 4: Complete DPFC controller. Experimental prototype parameters: universal
input voltage range, V0 = 380V, L = lmH, C = 230uF, transistor: FCP2ON60,
diode: 15ETX06, switching frequency: lOOkHz, maximum power: 500W
the proposed DPFC controller to fast voltage control (as in [18]
or [ 19]), we sample the output voltage at the switching
frequencyf, which is much higher than the line frequencyfine.
The large oversampling ratio fJfi,, is also very beneficial in
resolving an issue related to power quantization. Average
power delivered to the load is determined by the value of the
power command u. In the interest of minimizing the hardware
requirements, it is beneficial to reduce the word size for the
power command. However, at high power levels the power
differential between a 1 LSB step in u may become
considerably large; meaning that the resolution of power
levels drops significantly compared to lower power levels.
The quantization of u, however, means that the power
delivered to the load may not match exactly the power
consumed by the load. As a result, the voltage loop enters a
low-frequency limit-cycling mode (subharmonic with respect
to the line frequency) leading to highly undesirable operation
for a PFC. As an example, Fig. 6(a) reveals low frequency
oscillation near the apex of the current waveform.
Next, let us consider how the power quantization problem
can be completely resolved in the DPFC controller. First,
notice that the small-signal model in Fig. 5 includes an output
resistance equal to one half of the small-signal load resistance.
As a result, even in the case of an ideal power sink load (an
ideal downstream DC-DC regulator), there is a finite small-
signal resistance loading the output, which helps stabilize the
output voltage at zero average error even with finite power
resolution of the controller. Second, given the large
oversampling ratio fJfjine, XA modulation can be very effective
in improving effective resolution of the power command u,
with minimal hardware overhead. This is even more so in
digital PFC controllers than in digital controllers for DC-DC
converters where effective XA techniques were previously
described [24].
In the DPFC realization, we implemented a simple, first-
order XA modulator (XAu in Fig. 4) in the "error-feedback"
configuration [25], as shown in Fig. 7. The command with
word length of ni, bits is effectively reduced to a dithered
command with word length of n0u, < ni, bits. In the
experimental prototype, for u dithering, we have ni, = 16,
nout= 8. The result of u dithering can be observed in Fig. 6(b)
for the same operating conditions as in Fig. 6(a). In the
experimental results of Section IV we further show how u
subharmonic limit-cycling under all operating conditions.
.
en
g2vg,rmsf j2U4 r2 C R \
P2 V2
V
J2-v g2,rms ;r2 2P
Fig. 5: Averaged small signal model of the DPFC controlled
boost for slow voltage loop design
200
 Current ADC Resolution Vg = 120 Vrms Vg = 220 Vrms
(bits) mA/bit THD (%) THD (%)

:: ~~~Vg 8 33 4.3 2.3

7 65 4.4 2.4
6 130 4.7 2.7
..a
5 260 5.3 3.5
4 521 6.1 5.4
3 1042 8.1 9.1
Table 1: THD measurements for various current ADC resolutions, 4-bit DPWM,
*k
P= 500W

resolutions of the DPWM and the current sensing ADC were

investigated to this aim.
Chi 100 v. .
M2.OOms Ch2f
5.00 Mg 6OOmV
Fig. 6a.: no SA dithering implemented i. DPWM resolution

The resolution of the DPWM was variable from 1-bit to 9-

bits. During experimentation it was determined that the 1-bit
..
Vg and 2-bit settings were simply not feasible and represented
. .. .. .. extreme quantization effects. Implementing a first-order LA
............. .......................... ........ modulator (YA d in Fig. 4) to dither the duty-cycle comand d
allowed the DPWM resolution to be lowered to as low as 3-
.. .. .. .. ..
bits while maintaining harmonic limit standards at a 500 W
g.
.. .. .. .. .. ..
power level. A DPWM setting of 4-bits, with YA modulation
implemented, was found to be a suitable setting for the
operation of the boost PFC over the entire range of input
voltages and output power levels.
ii. Current sensing ADC resolution
Chi 100V S.OOVV M2.00ms
Fig. 6b: YA dithering only
. ,.
..... .Ch2f .. 6.lmV. .
The current sensing ADC had a variable resolution of 3-bits
to 8-bits. Table 1 shows how changing the current sense
... .. .... ... ....
resolution effects the total harmonic distortion (THD) of the
line current. The current sensing resolution in mA/bit is also
....
... Vg .. presented in Table 1. For this experiment the DPWM
resolution was set to 4-bits of resolution and YA modulation
... ... was enabled for both the u and d signals. The current LSB
quantization step is as high as 1 A in the case of a 3-bit current
........................... ......................
sense A/D, however, at 500W the harmonic current limits are
.. .. .
not exceeded.

iii. Combined quantization effects

Figure 9 shows three line current waveforms for different

Cnh uuv 5.0uuV v2i.0uums
Fig. 6c: u and d SA dithering
Fig. 6: Converter waveforms for various SA dithering settings, P
500W, Vg rws = 120 Vrms, 4-bit DPWM, 8-bit current sensing ADC
IV. SYSTEM IMPLEMENTATION
The experimental prototype consists of a boost rectifier
power stage and a digital controller implemented using a
Xilinx FPGA development platform. The digital controller
allows experimentation with the resolutions of current sensing
(up to 8-bit, 33 mA current LSB resolution), voltage sensing
(up to 8-bit, 3 V LSB output voltage resolution), and the
YA modulation implementations. Real-time inspection of the
Ouumv current waveform shown in Fig. 8a reveals low frequency
oscillation near the apex of the current waveform. Circles
have been added to show the locations of the oscillations that
lead to the aforementioned undesirable sub-harmonics.
Figure 8b shows the current waveform when IA, is
implemented, the sub-harmonic steps are no longer present but
a stair-step appearance still is present in the current waveform.
With YAd and YA, implemented, Fig. 8c produces a clean
waveform that easily meets harmonic current specifications.
Figure 9 is a plot of the harmonic currents for the same
conditions as shown in Fig. 8. Harmonic current values are
shown for both the YAd and YA, enabled and IA, only settings.
201
 Fig. 7: Error-feedback configuration of a first-order YA
modulator for dithering

The Class A harmonic current limits for the odd harmonics are
also shown. Without YAd active the 3-bit DPWM is not
capable of passing the harmonic current limits, with YA d
enabled the 3-bit DPWMV easily passes the harmonic current
limits. A total of six internal dithering bits (LSBs) were
utilized for the 3-bit DPWMV setting. Fig. 8a.: no YA dithering implemented

B. Experimental waveforms
Vg
i. Operation at high and moderate power

Table 2 shows the experimental line current (ia3, the I1-+I

rectified line voltage (vg) and the output voltage ripple (vrippie)
waveforms for different line voltages (220 Vrms and 120 Vrms)
and loads (500 W and 100 W) with a 4-bit DPWM and a 4-bit lac
current sensing ADC. The Class A harmonic current limits
are mieet fur all operating conditions.

ii. Operation at very low power

Figure 10 shows the converter waveforms at a line voltage Chi: 10''' .... S.OOVQ2 M2.OOms Ch2\-c 2.3 V
of 220 Vrms and a load of 20 W. The converter output is still
Fig. 8b: YA, dithering only
regulated and the line current meets harmonic current
standards although the THD is compromnised.
V. CONCLUSIONS Vg

This paper introduced a novel digital PFC (DPFC) control

approach that requires no input voltage sensing or current loop 14-+
compensation, yet results in stable, low-harmonic operation
over a universal input voltage range and load ranging from
lac
high-load operation in continuous conduction mode down to
near-zero load. The controller architecture, together with
simple, first-order IA modulation blocks for control signal
dithering, enable DPFC controller realization with a low-
resolution DPWM, low resolution A/D converters, and a low
clock rate. The DPFC controller is suitable for stand-alone
low-cost custom-IC implementation, or as a Verilog HDL .Chi' bOYv 5.00 VQ M2.00ms 'Chf2\-V 2.3 V

(hardware description language) module well suited for Fig. 8c: u and d YA dithering

integration with other power control functions. Experimental Fig. 8: Converter waveforms for various YA dithering settings, P=

verification results are shown for a 500 W boost DPFC 500W, Vgrn<, 120 Vrm,s, 4-bit DPWM, 8-bit current sensing ADC

rectifier.

202
 0.6- u dithering only

0.5- ~u and d dithering

r

1. odd harmonic limits

E

3 7 11 15 19 23 27 1 35 39
Fig. 10: Converter waveforms for very light load
Hamoi Number
operation, P =20W, Vg, =220 Vrm,s, 4-bit DPWM

Fig. 9: Harmonic currents with and without XA d dithering implemented, P and current sensing ADC

500W, Vg, 120 Vrm,s, 3-bit DPWM, 4-bit current sensing ADC

Vg,rms =l12OVrms Vg,rms = 220 Vrms

t --.

1 -+
P = IOOW
I
'ac
KE

Vripple Vripple
3-+

.V .m.. ,. F. . -.' kuu0V

k ... .FS. OWL. -. 'k k L. -; Lf2
F. A-.
Lfl I IUU
V ~~~~~~f .UU ivtu m Lfl CflI ME 2.00UVS I I-
iM2.uums
. . I 11 11 I
52umV
I I 11 II

Ch3 2.SO 0V%l Ch3 2.SO 0V"%

I

Vg

.a
1 -+
P = 500W

.r

,pp le

3-'
RE

1.1-
Chll . .'.k
100 V
1. " ..- - - --
5.UU VS
11- ..-
M2.OUms
',..-A '-'
1h12 'L
I- -
uumv chii bO v M 2.OOYSI M42.OOms Ch2X- SSOm Y,
am 10.0V%\ Ch3 IO.O0V"%
Table 2: Experimental waveforms for 100W and 500W for input voltages of 12OVm, and 220Vm,

203
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