Assignment: - 4

Computer Organization and Architecture

Submitted by:-
PANKAJ RAMPAL
A29
E3004
Group 1

Submitted to:-
Lect. Richa Malhotra
 PART A
Q1: Design a four bit combinational circuit Incrementer and Decrementer using full
adders.

A 4-bit combinational circuit using full adder: As increment means adding 1 bit to the

least significant bit of the input.. For getting its increment we have to add one carry to each
of the full hadder. Full adder increment=A+1

4-bit combinational circuit decrementer: A circuit that subtracts one to a four bit binary number.

Figure:

4 bit combinational circuit decremented: We have to perm the operation A-1

A-1=A+2’s complement of 1(i.e.1111) .
Q2: Register A holds the 8 bit binary 11011001. Determine the B
operand and the logic micro-operations to be performed in order to
change the value in A to (a) 01101101 (b) 11111101

Ans2:

Soln: At first we have to given ‘A’=11011001( 8 bit binary number)

And output =01101101, 11111101

Using this values we are evaluate the B’s operand

a) A=11011001
B=10110100

O=01101101

In this we have perform XOR operation and get the operand of B.

b) A=11011001
B=00100100

O=11111101

In this we perform OR operation and get the operand of B

Q3: Starting from initial value of R=11011101, determine the sequence of binary values
in R after a logic shift left followed by circular shift right, followed by a logical shift
right and a circular shift.

Ans:

(i) Initial value of R= 11011101

(ii) Logical Shift left= 10111010
(iii) Circular shift right= 01011101
(iv)Logical shift right= 00101110
(v) Circular right shift= 01011100
 PART - B

Q4: Give practical implementation example of MESI Protocol.

Ans:-
The MESI protocol is a method of insuring cache coherence in a multiprocessor machine.
With shared memory and more than one processor, it is vital to ensure that data in a
processor's cache is an accurate reflection of main memory.
M - Modified

The data in the cache line is modified and is guaranteed to only reside in this cache.
The copy in main memory is not up to date, so when the cache line leaves the
modified state the data must be written back to main memory.

E - Exclusive

The data in the cache line is unmodified, but is guaranteed to only reside in this
cache.

S - Shared

The data in the cache line is unmodified, and there may also be copies of it in other
caches.

I - Invalid

The cache line does not contain valid data.

Illustration of the MESI protocol

Read/Modify from
.----------. other cpu .-----------.
| INVALID |<----------------| SHARED |
'----+----+' +---------'-----------'
| | | Modify ^
Read/| | | |Read from
Modify| +--------+-----------+ |other cpu
V | Read | |
.----------.<------+ .-V---+-----.
| MODIFIED |<----------------| EXCLUSIVE |
'----------' Modify '-----------'

MESI Implementation: MESI implementation requires a message to be sent to the

directory on elimination of an exclusive line from the L2 cache.
Q5: Why is micro programmed control better than hardwired? Identify some situations
when hardwired is preferred.

Ans:-

Since the hardwired control has been historically faster, both of these two types of machine
are implemented by using the hardwired control in the microcomputer design educational
environment
Micro programmed is very flexible. After making the control unit of micro programmed, we
can change the computer instruction set simply by altering the micro program stored in
control memory. But in Hardwired Once the control unit is designed and built, it is very
difficult and we can say that impossible to alter its architecture and instruction set.

Fig. a Block diagram of the Basic Computer's Hard-wired Control unit

 • . If we want any modification or change then we can do easily by updating the
micro programmed in control memory. But in case of hard wired we have to
construct all the circuit again which is very difficult.

For example:

Taking our basic computer as an example, we notice that its four-bit op-code permits up
to 16 instructions. Therefore, we could add seven more instructions to the instruction set
by simply expanding its micro program. To do this with the hard- wired version of our
computer would require a complete redesign of the controller circuit hardware.

• . Another advantage to using micro-programmed control is the fact that the task of
designing the computer in the first place is simplified. The process of specifying
the architecture and instruction set is now one of software (micro-programming)
as opposed to hardware design.

1.In case of speed: If speed is a consideration, hard- wiring may be

required since it is faster to have the hardware issue the required
control signals than to have a "program" do it.

Q6: Parallel processing is a useful concept. But are there any constraints in the
implementation of parallel processing environment? How one can overcome such
constraints?

Ans:- Parallel Processing: parallel processing is the concurrent or simultaneous execution

of two or more parts of a single computer program, at speeds far exceeding those of a
conventional computer. Parallel processing requires two or more interconnected processors,
each of which execute a portion of task; some supercomputer parallel processing system have
hundreds of thousands of microprocessors. The processors access data through shared
memory. The efficiency of parallel processing is dependent upon the development of
programming languages that optimize the division of the tasks among the processors.

Parallel Processing: parallel processing is the concurrent or simultaneous

execution of two or more parts of a single computer program, at speeds far
exceeding those of a conventional computer. Parallel processing requires two or
more interconnected processors, each of which execute a portion of task; some
supercomputer parallel processing system have hundered of thousands of
microprocessors. The processors access data through shared memory. The
efficiency of parallel processing is dependent upon the development of
programming languages that optimize the division of the tasks among the
processors.

SIMD:

SIMD , is a class of parallel computers in Flynn's taxonomy. It describes

computers with multiple processing elements that perform the same operation
on multiple data simultaneously. Thus, such machines exploit data level
parallelism.

MIMD:

MIMD (Multiple Instruction stream, Multiple Data stream) is a technique

employed to achieve parallelism. Machines using MIMD have a number of
processors that function asynchronously and independently. At any time,
different processors may be executing different instructions on different pieces
of data.

SISD(single instruction, single data stream):

MISD(multiple instruction, single data stream):

o MISD is not implemented practically.