Selected Answers for Electronics, 2nd edition

by Allan R. Hambley

1.6 ∆ = 152.6 µV

1.12 4 × 106 transistors/chip

1.15 Av = 50, Avs = 33.3, Ai = 1.25 × 106, G = AvAi = 6.25 × 107

1.18 Ro = 1.11 kΩ

1.21 When the amplifiers are cascaded in the order A-B, we have: Ri = RiA = 3 kΩ, Ro =
RoB = 20 Ω, Avo = 4.998 × 104.

1.27 Pdissipated = 17.5 W, η = 41.67%

1.33 Gdb = 50 dB, RL = 1 kΩ

1.39 Ro = 200 Ω

1.45 We have a nearly ideal transresistance amplifier with Rmoc = 10 Ω.

1.55 Av = 100 ∠ − 105 $ ; AvdB = 40 dB.

1.56 vo(t) = 2 + 4cos(200πt - 18$ ) - 2cos(2000πt).

1.63 CMRR = 60 dB

1.65 CMRR = 108 dB

2.4 We can have four op amps in a 14-pin package, allowing two pins for power-supply
connections common to all four op amps.

2.10 (a) -2 V; (b) -1 V; (c) 3 V; (d) 0 V; (e) 3 V.

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2.12 (b) Zin ≅ 0.1 Ω; (c) Zin = -10 kΩ; (d) Zin = . Thus, the input impedance is
jω( 101C)
that of a 101-pF capacitance.

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2.15 The tolerance of the closed-loop gain is approximately ± 2%.

2.18 A1 = -4/3; A2 = -8/3.

2.27 Avmin = 1.905; Avmax = 2.105; the tolerances of the gain magnitude are -4.75% and
+5.25%.

2.32 100 Ω/square

2.42 (a) Avs = 0.99999; (b) Zin = 1011 Ω;

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(c) Zo = = 2.5 × 10-4 Ω
1 1 + AOL
+
R in Ro

2.46
Frequency AOL Phase
100 9988 -87.14°
1 kHz 1000 -89.71°
1 MHz 1 -90.00°

2.50 (a) fFP = 159 kHz; (b) Vom = 10 V; (c) Vom = 2 V; (d) Vom = 1.59 V.

2.52 SR = 8 V/µs

2.58 Vo ranges from -26.5 mV to +66.5 mV.

2.60 (a) Voff = ± 9.09 mV; (b) IB = ± 1 µA; (c) RB = 9.09 kΩ; (d) Ioff = ± 1 µA.

2.76

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3.4 vD = 0.3 V

3.7 Tfinal = 125 °C

3.9 (a) IA ≅ 2.13 I mA, VA ≅ 0.8 V; (b) IB ≅ 1.65 mA, VB ≅ 0.66 V; (c) IC ≅ 1.15 mA, VC
≅ 0.29 V.

3.15 (a) V = 0 and I = 3.70 mA; (b) I = 0 and V = 10 volts; (c) V = 0 and I = 0; (d) V = 5
volts and I = 5 mA.

3.16 (a) V = 10 volts and I = 0; (b) V = 6 volts and I = 6 mA; (c) V = 30 volts and I = 33.6
mA.

3.22 R = 900 Ω.

3.29 (a) For a source frequency of 400 Hz, C > 2500 µF; (b) For a source frequency of 60
Hz, C > 16700 µF.

3.43 We can cascade only two OR gates if we require the output in the high state to be
at least 3.5 V.

3.45 PD = 0.48 W (worst case).

3.46 R = 333 Ω.

3.50 rd = 0.

3.51 (a) For n = 1: Is = 95.0 × 10-15 A; (b) For n = 2: Is = 9.75 × 10-9 A.

3.55 (a) ∆vload = 23.9 mV; Source regulation = 1.2%; (b) Load regulation = 0.108%.

3.59 For IDQ = -1 mA, VDQ = -4.5 V and rd = 167 Ω. For IDQ = -10 mA, VDQ = -4.77 V and
rd = 7.48 Ω.

3.71 p ≅ 1016 cm-3; n = 2.10 × 104 cm-3.

3.77 For n = 1, vD1 = 582 mV. For n = 2, vD1 = 564 mV.

3.86 L = W = 292 µm.

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3.87
m VDQ = -1 V VDQ = -10 V
1/2 70.7 pF 30.2 pF
1/3 79.4 pF 45.0 pF

3.90 (a) Rs = 25 Ω; (b) Cj0 = 26.3 pF; (c) τT = 1.75 µs.

4.8 β = 30; α = 0.9677; iE = 9.3 mA.

4.11 IC2 = 0.9804 mA; VBE = 0.6583 V.

4.15 For IE = 1 mA, VBE = 0.640 V. For IE = 0.1 mA, VBE = 0.580 V.

4.20
vin = +0.2 V vin = 0 vin = -0.2 V
iB (µA) 10 5.5 1.25
iC (mA) 4 2.2 0.5
vCE (V) 12 15.6 18.9

Av = -17.25

4.25 VBE = 0.283 V

4.29 (a) Cutoff; (b) Saturation; (c) Active.

4.35 RB = 31.5 kΩ and RE = 753 Ω.

4.42
ICQ rπ gm
1 µA 2.6 MΩ 38.5 µS
0.1 mA 26 kΩ 3.85 mS
1 mA 2.6 kΩ 38.5 mS

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4.46

High-impedance Low-impedance
amplifier amplifier
(Problem 4.45)
ICQ 39.3 µA 3.93 mA
rπ 66.2 kΩ 662 Ω
Av -75.5 -75.5
Avo -151 -151
Zin 54.8 kΩ 548 Ω
Ai -41.4 -41.4
G 3124 3124
Zo 100 kΩ 1 kΩ

βRL ′ ′
4.53 Av = where RL = RC RL
rπ + ( β + 1)RE
Zin = RB [rπ + (β + 1)RE]

4.57 Av = 0.9798; Zin = 370 kΩ.

r π + R 1 (1 + r π / R 2 )
4.60 VCEQ = 7.25 V; Ro = = 126 Ω.
1 + β + r π / R2

4.66 For the circuit to remain in saturation, we must have β > 22.3.

5.3 (a) Saturation, iD = 2.25 mA; (b) Triode, iD = 2 mA; (c) Cutoff, iD = 0.

5.10 Vto = 1 V, K = 0.5 mA/V2.

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5.15

5.20 VDC = 10.5 V, V2m = 0.5 V and V1m = -6 V. The percentage second-harmonic
distortion is V2m /V1m × 100% = 8.33%.

5.26 VGSQ = 2.5 V, IDQ = 0.5625 mA, VDSQ = 4.375 V.

5.30 rd = ∞ .

5.35
gm

IDQ

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5.40 gm = 6 mS, Rin = 3.3 MΩ, Av = -gmRD = -7.2, Ro = 1.2 kΩ.

5.44 (a) The FET in this circuit is operating in the triode region. VDSQ = 2.44 V, IDQ =
13.56 mA; (b) gm = 4.88 mS, rd = 321 Ω; (c) Ri = 100 kΩ, RL’ = RD RL rd = 195 Ω, Av =
-0.954, Ro = 243 Ω.

5.56 vGS = -1 V.

5.60 IDSS = 13 mA and Vto = -3 V.

5.65 (a) I1 = 8 mA; (b) I2 = 8 mA; (c) I3 = 8 mA, V2 = 0, V1 = 7 V; (d) I5 = 8 mA, I4 = 4

mA, V4 = 7 V, V5 = 0.586 V.

5.70 IDSSe = 2IDSS, Vtoe = Vto, gme = 2gm.

6.6 (a) F = (A + B )C ; (b) F = A + B + BC ; (c) F = D + AB + BC .

6.11 (a) F = AB + ( C + A) D = ( A + B )( AC + D)
(b) F = A( B + C) + D = ( A + B C ) D
(c) F = ABC + A(B + C) = ( A + B + C )( A + B C )

6.16 Pdynamic = 0.36 mW. (This is for an inverter operating at 400 MHz.)

6.20 NMH = 1.5 V, NML = 0.5 V.

6.25 Pdynamic = 6.25 mW.

6.30 (a) increase RD; (b) reduce W; (c) increase L; (d) reduce VDD.

6.36 NMH = 2.96 V, NML = 0.96 V.

C ln( 2)
6.40 tPHL =
1/ R D + 1/ R on

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6.48 For vI = VDD/2:
VDD (V) IDD (µA)
3 18.75
5 168.8
10 1200

For vI = 0, we have IDD = 0 for all values of VDD.

6.50 For vI high and vO = 0.5 V, iO = 0.281 mA (We are referencing the current iO into
the output terminal of the inverter.) We have iO = -0.281 mA for vI = 0 and vO = 4.5 V.

2(1 + λV DD / 2)
6.55 dv O = −
dv I λ( V DD / 2 − V to )

6.60 IDDavg = 0.25 mA, PDDavg = 1.25 mW.

6.65 The PMOS transistors must have W = 8 µm and L = 1 µm. The NMOS transistors
have W = 2µm and L = 1 µm.

6.71
φ M1 M2 M3 M4 M5 M6 M7 F IDD
1 off off on off off off on 0 0
0 off off on off off on off 1 0

6.75 Each transistor must have W/L = 2 × 6.25 = 12.5.

7.4 VBE1 - VBE2 = -1.27 mV

β2 + 2 β V − 1.2
7.15 IC3 = IC4 = 2
× CC ≅ Iref/2
2( β + 2 β + 2) R ref

7.20 Thus the percentage increase in IC2 is 0.995%.

7.25 IC2 = IC1 = IC3 = IC4 = IC5 = 0.5 mA, VO = 5 V.

7.31 (a) iD3 = 1.5 mA, iD2 = 1 ma; (b) iD5 = 0.5 mA, iD6 = 2 mA.

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  g g r d1 + g m3 + 1/ r d3 
7.35 ro = rd3  1 + m3 m1 

 g m2 + 1/ r d2 

7.40 The transfer characteristic of the BJT differential amplifier is shown in Figure
7.26 on page 439 in the book. It is approximately linear for -VT ≤ vid ≤ VT.

7.45
Percentage vid
90% 57.1 mV
99% 119 mV

7.50 Avds = 65.6, Ri = 30.5 kΩ.

v o1 = − gm RD
7.58 Avcm = .
v icm 1 + 2 g m R SB

7.62 The gate of M3 is the inverting input, and the gate of M4 is the noninverting input.

7.70 Q1 and Q2 form a differential amplifier with single-ended output. Q3 is an emitter

follower. Q4 is a common-emitter amplifier and Q5 is an emitter follower.

7.75 A1/A2 = 0.926 or A1/A2 = 1.080, depending on the polarity of the offset voltage.

8.6 number of decades = log10(2200/50) = 1.643

log10 (44)
number of octaves = log2(2200/50) = = 5.46
log10 (2)
8.9 (a)
1 − RCs
A(s) = V o =
V in 1 + RCs
(b) We have a pole at s = -1/(RC) and a zero at s = 1/(RC).
(c) The magnitude plot is constant versus frequency. The phase starts at zero at
very low frequency and approaches -180° as frequency increases.

8.12 Amid = -2.07, fz = 1 GHz, fp1 = 15.1 MHz, fp2 = 2.03 GHz. Because fp1 is much lower
than the other two break frequencies, the upper half-power frequency is approximately
equal to fp1.

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8.16 Amid = -153, RL’ = 30.6 kΩ, RL = 44.1 kΩ.

8.20 (a) Zin = 909 Ω; (b) Zin = 99.0 Ω; (c) Zin = ∞; (d) Zin = -10 kΩ.

8.25 We have a nearly ideal transresistance amplifier, and the transresistance gain is
Rm ≅ -10 kΩ.

8.30
ICQ (mA) ro hoe
0.1 1 MΩ 1 µS
1 100 kΩ 10 µS
10 10 kΩ 100 µS

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8.35 hie = rx + = 604 Ω.
1/ r π + 1/ r μ
8.40 (a) RB = 1.43 MΩ, RC = 7 kΩ; (b) fH = 6.48 MHz, Avs = -31.0.

8.46 The common-base amplifier tends to have the lowest input resistance. The
common-emitter and cascode amplifiers are inverting. To minimize feedback capacitance,
we usually want to apply the input to the first transistor and take the output from the
second transistor in an emitter-coupled pair, in which case this amplifier is noninverting.
The common-base amplifier and emitter follower are noninverting. The frequency
response of the common-emitter amplifier is limited to the greatest degree by the Miller
effect.

8.56 Av ≅ Avs ≅ 0.87, fH = 56.5 MHz.

8.61 The break frequency for each capacitor is fbreak = 1/(2πRC) where R is the total
equivalent resistance in series with the capacitor.

8.64 fB1 = 1/[2πC1(Rs + Rin)] = 264 Hz

fB2 = 1/[2πC2(Ro + RL)] = 160 Hz
fE = 1/(2πCE RE ’) = 567 Hz
fL = f1 + f2 + fE = 991 Hz.
(The simulation yields fL = 848 Hz.)

9.5 For A = 1000, we have Af = A/(1 + Aβ) = 9.9.

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 xo(t) = Afxs = 9.9cos(ωt)
xf(t) = βxo = 0.99cos(ωt)
xi(t) = xs - βxo ≅ 0.01cos(ωt)

9.9 A ≥ 990. Assuming that A = 990, we need β = 0.098989 to achieve Af = 10.

9.18 Vsignal = 17.9 V rms, Vnoise = 566 µV rms.

9.26 Negative series feedback increases input impedance. Negative parallel feedback
reduces input impedance.

9.30 Avf = 9.9990, Rif = 10 MΩ, Rof = 0.1 Ω.

9.35 Aisc = 105. (We neglect loading effects, in which case Ai = Aisc.) Aif = 9.9990, Rif = 0.1
Ω, Rof = 10 MΩ.

9.40 Here is a suitable circuit configuration:

One set of resistances that meets the objective is R1 = 909 Ω, R2 = 100 Ω, R3 = 909 Ω,
and R4 = 113 Ω.

9.45 In current feedback, the input of the feedback network is in series with the
amplifier output terminals. If the feedback resistors are large, significant voltage is
dropped across the input resistance of the feedback network. In effect, this reduces
the open-loop gain of the amplifier. Since we want Aβ to be very large in magnitude, we
choose small resistances for a current feedback network.

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9.50 (a) We need to use negative series voltage feedback with β = 1.8 × 10-3.
(b) A suitable circuit configuration is:

Neglecting loading, we determine that a suitable choice of 1%-tolerance resistors is R2 =

1 kΩ and R1 = 549 kΩ. (c) Using PSpice, we find that the input resistance achieved is
approximately 860 kΩ. The impedance is lower than desired because of loading effects
(mainly due to RL). However, if we reduce R1 to 453 kΩ, we achieve Rif ≅ 1 MΩ.

9.58

(a) (b)

(c) (d)

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9.63 For A0f = 10, the bandwidth is fbf = 105 Hz, and the time constant is τ = 1.59 µs.
For A0f = 1, the bandwidth is fbf = 106 Hz, and the time constant is 0.159 µs.

9.67 ωn = 7078, δ = 0.0777, Q = 6.43.

9.72 We set up a macromodel for the amplifier and use SPICE to obtain plots of the
open-loop gain and phase. When we run the simulation and plot the gain and phase, we
determine that for a phase of 120° (corresponding to a phase margin of 60°) we have fPM
≅ 77 Hz and a gain magnitude of 54.2 dB. Thus, the largest value allowed for β is -54.2
dB which corresponds to β = 1.95 × 10-3. Using the plots we find that the phase never
crosses through -180°. Thus the gain margin is infinite.

9.78 There is a misprint in the problem statement in the first printing of the book. The
problem should refer to the amplifier of Problem 9.76. f1 ’ = 195 Hz. The gain margin
turns out to be 17.8 dB (for β = 1).

9.85 K = 3 (or greater) and ω = 1/RC. (Assume that the op amp is ideal.)

9.88 (a) Rm = R and ω = 1/ LC . (b) Rm = 4R and ω = 1/ (RC 2 ) .

9.92 The minimum allowed value is R2 = 23.2 kΩ. To ensure that the actual value of R2
always exceeds the required value, we must choose the nominal value of R2 to be 27 kΩ.

10.6 θJC = 3.75°C/W.

10.10 The third sentence of the problem should read: "The case-to-sink thermal
resistance is θCS = 0.5°C/W." Then the answer is θSA = 10.75°C/W.

10.18 PDmax = 33.3 W, ICmax = 1.33 A.

10.23 PQ1 = 10 W, IC1avg = 1.58, and VCEavg = 12.65. Thus IC1avgVCEavg = 20 W which is not
equal to PQ1.

10.25 (a) PQ1 = 0, PCC = 225 mW, PEE = 225 mW, Po = 225 mW, η = 50%, Pbias = 225 mW (b)
PCC = 225 mW, PEE = 225 mW, Po = 112.5 mW, Pbias = 225 mW, PQ1 = 112.5 mW, η = 25%.

10.35 (a) VCC = 28.3 V. (b) The peak current rating of the transistors should be larger
than 3.54 A. (c) The peak VCE ratings of the transistors should exceed 56.6 V. (d) The
thermal design should accommodate at least 10.1 W without exceeding the maximum

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junction temperatures of the devices.

10.45 R1 = 20 kΩ.

10.57 Vth = 27.6 V, Rth = 1.8 Ω.

11.3 Here is one solution:

11.10 For a bandpass filter having f0/B ≅ 1, we would cascade a low-pass filter with a
high-pass filter. For f0/B >> 1, we use the Delyiannis-Friend circuit shown in Figure 11.12a
on page 740 in the book.

11.15 f0 = 1.592 MHz, Q = 50, B = 31.8 kHz, fL ≅ 1576 kHz, fH ≅ 1608 kHz.

11.20 Q = 120, L = 95.49 µH, and C = 2.65 pF. It is questionable whether these values
are practical. See Figure 11.35 on page 760 in the book.

11.24 f0 = 1.125 MHz, Q = 14.1, B = 79.5 kHz, fH ≅ 1.165 MHz, fL ≅ 1.085 MHz.

11.30 For f = 100 kHz: Qs = 12.6, Lp = Ls = 1 mH, Rp = 7.9 kΩ.

For f = 200 kHz: Qs = 25.1, Lp = Ls = 1 mH, Rp = 31.6 kΩ.

11.35 The functions of the matching network in a class-D amplifier are to filter out

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 undesired harmonics (or the dc component) and to step the amplitude of the
desired term either up or down as needed to achieve the desired output power.

11.40 Here is one answer. Other correct answers exist.

11.45 (a) Rs1 = Rs2 = 7.79 kΩ. Thus we choose the standard value Rs1 = Rs2 = 8.2 kΩ. (b)
C1 = 1269 pF, C2 = 316.4 pF. (c) C3 = 316.43 pF and C4 = 1269 nF. (d) Av = 1.78.

11.55 ± 0.0116 ppm. (Most crystal oscillators are not capable of this degree of accuracy
over several days.)

11.58 Ls = 31.8310 mH, Cs = 0.0318310 pF, fp = 5.0066 MHz.

12.5 Figures 12.13, 12.14 and 12.15 on pages 808 and 809 in the book show examples of
transfer characteristics with hysteresis.

12.10 Follow the procedure of Example 12.1. We arbitrarily chose R3 = 100 kΩ and
analyzed the circuit to determine that R1 = 25.68 kΩ and R2 = 10.30 kΩ. Finally, we chose
the closest 1%- tolerance values: R1 = 25.5 kΩ and R2 = 10.2 kΩ.

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12.25 One solution is shown below.

12.35 The sampling rate is 1.5 × 2 × fH = 300 Hz. n = 9 or greater. The data rate is
(300 samples/s) × (9 bits/sample) = 2700 bits per second.

12.40 io = 19.92 mA, vo = -9.96 V.

12.45 A flash ADC is best if high speed is the primary consideration. Usually a
dual-slope ADC is best if accuracy is the primary consideration.

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