EC402 Digital Electronic Circuits

Dr. Sushanta Kumar Mandal

Homework -2
Assigned on: 07-04-2011 Due on: 15-04-2011 (in class)

P1. What do you understand by asynchronous input of a flip-flop? Why asynchronous inputs are
required?

P1. Design a 4-bit positive edge-triggered binary ripple counter. Now modify the design to make it
modulo-11 counter. Draw the timing diagram.

P2. Design a 4-bit parallel-in-serial-out shift register using JK flip-flops.

P3. Design a 4-bit up-down synchronous counter.

P4. Compare between Mealy and Moore machines.

P6. Design a 2-bit up/down saturating counter using the finite state machine method discussed in class,
i.e. derive the state diagram, state table and draw the logic circuits. The counter consists of 2 inputs (one
for controlling direction, the other one is the clock) and 2 outputs that represent the current count value.
The functionality of this counter is described in the pseudo code on the right. Assume the initial counter
state is C1C0=01.

(i) Draw the state diagram using Moore machine.

(ii) Derive the State Table and derive the needed equations with K-map.
(iii) Draw the sequential logic of this counter of your design. You do not need to draw the internals of
the D Flip/Flop, simply draw D Flip/Flop as a block.

P7. Design an arithmetic circuit with one selection variable S and two 2-bit inputs A and B using full
adders, inverter and 4x1 multiplexers. The circuit will perform the following operation in conjunction
with the input carry Cin.
S Cin = 0 Cin =1
0 A+B A+1
1 A-1 A-B
P8. Design a 3-bit counter to count 0-2-3-6-5-1. After 1 it is to go back to 0. If three JK flip-flops be
used for such a counter, obtain the excitation table for the inputs of the three flip-flops and draw the
logic circuit. For the Present states of 100 and 111, assume the Next states to be 111 and 100
respectively.
P9. 4 memory modules of 512MX8 are to be connected together to get a memory of 1GX8.
Show the connection of the memory modules along with the decoder required for the memory
system.

P10. Design a 4-bit self-correcting ring counter using D-FF whose main loop is as follows:
1 1 0 0 → 0 1 1 0→ 0 0 1 1→1 0 0 1→1 1 0 0→0 1 1 0 …
Draw the state diagram including unused states to show that if the circuits ever goes to one of
the unused states after some clock pulse the circuit goes back to one of the valid states and
continues to count correctly.

P11. A sequential circuit has one input X(t), and one output Z(t). Whenever the input sequence
consists of a stream of 010 or 0001 (three 0’s in a row then 1), the output will become 1 during
the clock cycle when the last symbol is received. Otherwise, the output equals to 0. Derive a
Mealy model state diagram of this synchronous sequential circuit.

P12. Design a counter that can count both modulo-5 and modulo-8.

P13. Design a modulo-12 up counter using a 4-bit Up/Down counter.

P14. Derive the reduced state table.

P15. Implement the CMOS logic circuit of the following Boolean function.