APPROACH TO NANOELECTRONICS

BY: DHEERA SAXENA

THAKRAL COLLEGE OF TECHNOLOGY

1. INTRODUCTION TO NANOELECTRONICS

1.1 Nanoscale

Dimensions between approximately 1 and100 nanometers are known as the nanoscale. A nano meters is a
unit of length in the metric system, equal to one billionth of a metre.
1 nanometre =1×10−9 m

Unusual physical, chemical, and biological properties can emerge in materials at the nanoscale. It can be
seen that atoms, DNA, proteins, viruses and transistors all are in the realm of what can be broadly
classified as nanoscale objects.

1.2 Nanotechnology

The definition from the U.S. National Nanotechnology Initiative encompasses key aspects included in
other definitions from around the world.

“Nanotechnology is the understanding and control of matter at dimensions between approximately 1

and 100 nanometers, where unique phenomena enable novel applications. Encompassing nanoscale
science, engineering, and technology, nanotechnology involves imaging, measuring, modeling, and
manipulating matter at this length scale. "

The size scale involved in nanotechnology also corresponds to some point in Electromagnetic spectrum,
where it can be appreciated that wavelengths between the Ultraviolet (UV) and X-rays are on the general
scale of nanometer.

1.3 Nanoelectronics

Nanoelectronics is nanotechnology applied in the context of electronic circuits and systems. The aim of
Nanoelectronics is to process, transmit and store information by taking advantage of properties of matter
that are distinctly different from macroscopic properties. The relevant length scale depends on the
phenomena investigated: it is a few nm for molecules that act like transistors or memory devices can be
999 nm for quantum dot where the spin of the electron is being used to process information.
Microelectronics, even if the gate size of the transistor is 50 nm, is not an implementation of
nanoelectronics, as no new qualitative physical property related to reduction in size are being exploited.
Semiconductor electronics have seen a sustained exponential decrease in size and cost and a similar
increase in performance and level of integration over the last thirty years Nanoelectronics thus needs to be
understood as a general field of research aimed at developing an understanding of the phenomena
characteristic of nanometer sized objects with the aim of exploiting them for information processing
purposes. Specifically, by electronics we mean the handling of complicated electrical wave forms for
communicating information (as in cellular phones), probing (as in radar) and data processing (as in
computers).

There are several perspectives to the concept of nanoelectronics:

 One is the fact that the nanoscale dimensions of nanoelectronic components allow for systems of
giga-scale complexity measured in terms of component on a chip or in a package. This scaling
feature and the road to giga-scale systems can be described as the ‘More Moore’ domain of
development.
 Another is that nanotechnology is very diverse and allows the integration of purely electronic
devices with mechanical devices, bio-devices, chemical devices, etc. Also, digital systems can be
combined with analog/RF circuits. This technology fusion can be described as the ‘More than
Moore’ domain of development.
 A third is that traditional scaling limits in standard CMOS technology are reached during the next
decade, calling for fundamentally new nanoscale electronic devices. This development of
nanoelectronic components can be denoted the ‘Beyond CMOS’ domain of development
Hence nanoelectronics is a wide open field with vast potential for breakthroughs coming from
fundamental research.

2. APPROACHES TO NANOELECTRONICS

2.1 MOORE’S LAW

In 1965, Gordon Moore (cofounder of Intel Corporation) observed that the number of transistors per
square inch on an IC chip roughly doubled in every 12 months. This general rule is known as Moore’s
Law has approximately held through the present time. Although Moore's law was initially made in the
form of an observation and forecast, the more widely it became accepted, the more it served as a goal for
an entire industry. This drove both marketing and engineering departments of semiconductor
manufacturers to focus enormous energy aiming for the specified increase in processing power that it was
presumed one or more of their competitors would soon actually attain. In this regard, it can be viewed as a
self-fulfilling prophecy.
Though now the number of transistor per square inch on an IC chip gets doubled in every 18-24 months.
The beginning of nanoelectronics have made electronic industry to like this process of minimization and
scientists have predicted the end of Moore’s Law by 2015 to 2018, when manufacturing of transistors
with 16 nm feature size will be possible.

2.2 SEMICONDUCTOR ROAD MAP

The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the

semiconductor industry's technology requirements. The objective of the ITRS is to ensure advancements
in the performance of integrated circuits and remove roadblocks to the continuation of Moore's Law. This
assessment, called road mapping, is a cooperative effort of global industry manufacturers and suppliers,
government organizations, consortia, and universities.

2.3 THE “TOP-DOWN" APPROACH

A Top-Down approach (or Step-Wise design) is essentially the breaking down of a system to gain insight
into its compositional sub-systems. In a top-down approach an overview of the system is first formulated,
specifying but not detailing any first-level subsystems. Each subsystem is then refined in yet greater
detail, sometimes in many additional subsystem levels, until the entire specification is reduced to base
elements.
The microelectronic industry was born out of the invention of the transistor in 1947 to 1948 by William
Shockley, Walter Brattain, and John Bardeen of Bell Laboratories. The invention of integrated circuit in
1958 by Jack Kilby and Robert Noyce. The first transistor was a bipolar device consisting of two sharp
metal wires. By 1960, the minimum size of a transistor had shrunk to approximately 100µm. In 1980, it
was close to 1µm, and in 2001, feature size was on the order of 130nm.This was followed by 90nm
manufacturing in 2003, and in 2005, 65 nm were produced. Also, 45nm technologies were produced in
the 2007 and 32nm technologies being planned for the near future.
Because of the diminishing feature size of transistor and other components, one could say that the
electronics industry is already “doing” nanotechnology.

2.4 THE “BOTTOM-UP” APPROACH

A bottom-up approach is the piecing together of systems to give rise to grander systems, thus making the
original systems sub-systems of the emergent system. In a bottom-up approach the individual base
elements of the system are first specified in great detail. These elements are then linked together to form
larger subsystems, which then in turn are linked, sometimes in many levels, until a complete top-level
system is formed.
In contrast to the “top-down” approach, this nanoscale building is called the “bottom-up” approach, and
represents a much more radical technology shift, which is currently being explored in research
laboratories. Though this approach is time-consuming process but it also generates a possible future for
nanoelectronics.
Instruments are developed recently that have allowed scientists to see and manipulate nano- and atomic-
sized objects. These instruments include scanning electron microscope (SEM) and the scanning tunneling
microscope (STM).

3. NANOLITHOGRAPHY

Nanolithography refers to the fabrication of nanometer-scale structures, meaning patterns with at least
one lateral dimension between the size of an individual atom and approximately 100 nm.
Nanolithography is used during the fabrication of leading-edge semiconductor integrated circuits
(nanocircuitry) or nanoelectromechanical systems (NEMS).
Nanolithography is that branch of nanotechnology, which deals with the study and application of
fabrication of nanoscale structures like semiconductor circuits.
There are many types of nanolithography

 Optical Lithography
 X-ray Lithography
 Magneto Lithography
 Extreme Ultraviolet Lithography
 Immersion Lithography

3.1 OPTICAL LITHOGRAPHY (PHOTOLITHOGRAPHY)

Optical lithography is the most commonly used nanolithography.

Photolithography (or "optical lithography") is a process used in nanofabrication to selectively remove
parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photo
mask to a light-sensitive chemical photo resist, or simply "resist," on the substrate. A series of chemical
treatments then engraves the exposure pattern into the material underneath the photo resist. In complex
integrated circuits, for example a modern CMOS will go through the photolithographic cycle up to 50
times.

Optical lithography will require the use of liquid immersion and a host of resolution enhancement
technologies (phase-shift masks (PSM), optical proximity correction (OPC)) at the 32 nm node. Optical
lithography has driven many of the advances in nano-scale manufacturing, with its ability to print ever
smaller features as the technology matures. Lens-based optical systems are typically used, with improved
resolution usually being achieved by lowering the wavelength-current systems use 193nm illumination
from ArF excimer lasers. By applying some additional tricks, these sophisticated projectors can be pushed
to print dense lines narrower that 45nm, which is less that 1/4 of that wavelength. Most experts feel that
traditional optical lithography techniques will not be cost effective below 22 nm.

4. INNOVATIVE NANOELECTRONIC DEVICES

There are numerous developments in the field of nanoelectronics, just to list few:

4.1 CARBON NANOTUBE DEVICES (CNT Devices)

4.1.1 STRUCTURE AND TECHNOLOGY

Carbon nanotubes are made out of a network with the basic unit being six carbon atoms in ring
configuration and arranged in form of cylinders. The geometry of the interconnections between carbon
rings results in either metallic or semiconducting material.
The growth of the cylinders with diameters in nanoscale range is generally induced by the use of catalytic
elements such as iron, molybdenum and cobalt. Depending on the growth parameters, the deposition
processes results in the formation of multiwall nanotubes or single wall nanotubes.

4.1.2 APPICATOINS OF CNT

The first applications of CNT’s are wiring of microelectronic circuits and the use as field emitters for high
resolution flat panel displays. The other application of CNT’s is in Carbon NanotubeTransistors.

4.2 NANOWIRES

Semiconductor nanowires are increasingly used in electronic devices including field-effect

transistors, sensors, detectors and light-emitting diodes.

Semiconductor nanowires are one-dimensional structures, with unique electrical and optical
properties, that are used as building blocks in nanoscale devices. Their low dimensionality means
that they exhibit quantum confinement effects. For example, narrowing the wire’s diameter
increases its band gap, compared to the bulk material.
Researchers have examined various ways of growing semiconductor nanowires, including laser
ablation, chemical vapour deposition (CVD) and template-assisted growth. While laser ablation
and template-assisted approaches provide bulk quantities of semiconductor nanowires, they do
not provide much control over the composition, size or crystallographic direction of the
nanowire. Also to grow core-shell and core-multishell nanowire heterostructures using a CVD
method that provides increased control over the structure’s composition. Using this technique,
the nanowires are grown by gradually building up thin, uniform shells around a nanometre-sized
cluster of gold atoms. The nanowires had boron-doped silicon shells surrounding intrinsic
silicon, as well as silicon wrapped around a silicon oxide core. They also investigated the growth
of crystalline germanium-silicon and silicon-germanium core-shell heterostructures.

5. ADVANTAGES OF NANOELECTRONICS

The most important advantage of nanoelectronics is the reduction of feature size in manufacturing
process, at a greater expense. It has fulfilled the wish of consumers and manufactures for smaller, faster,
cheaper and yet better electronic products. Thus the reduction in product size is due to shrinking the size
of individual electronic devices. This reduction also leads to improved functionality. There are direct
economical advantages of small device size, since the cost of integrated circuits chips depends upon the
number of chips that can be per silicon wafer. Therefore, higher device density leads to more hips that can
be produced per silicon wafer, resulting cost reduction. Thus the smart nanoelectronic devices boost the
system performance and incorporate new services such as :

 Compact( devices components of nanoscale)

 Less energy consumption
 More efficient and sustained generation of energy
 Wireless sensors technologies for monitoring
 Enhanced devices
 Better security, and many more.

6. APPLICATIONS OF NANOELETRONICS

 Analytical equipment and techniques for measurement of electro technical properties

 Fabrication tools for integrated circuits
 Nano-structured sensors
 Optoelectronics
 Nano-enabled solar cells
 Bioelectronic applications
 Energy storage devices
 Fuel cells
 Electro technical properties of nanotubes/nanowires

7. PROBLEMS IN NANOELECTRONICS
In addition to the benefits of smaller transistors, there are significant problems in shrinking convention
devices to the nanoscale.
DEVICE FABRICATION: There is difficulty to extend optical lithography into the realm of low tens of
nanometer and other fabrication methods for high-throughput, commercial-level production are yet
matured.
DEVICE OPERATION: As device dimensions are reduced, voltage levels also need to be reduced
accordingly. This lowers the threshold voltage of MOSFET devices, and makes it difficult to completely
turn the device off wasting power.
HEAT DISSIPATION: As device density increases, the dissipation of heat becomes a major problem,
reducing circuit reliability and leading to shorter device lifetime.
Given the proceeding problems, it can be seen that at some point in time, the electronics industry needs to
look beyond shrinking the size of conventional electronic devices. New devices and system architectures
will need to be developed, probably based on physical effects only encountered on the nanoscale. For a
new electronics technology to supersede the current silicon-based complementary metal oxide
semiconductor (CMOS) technology, it would need to be more attractive from an economic and technical
stand point

Last, it should be mentioned that many prototype nanoelectronic devices have been developed and in
some cases their device characteristics are fairly well understood. The sector of nanoelectronics opens
new ways for education, personal entertainment, more efficient administration and allows increased
efficiency and sustainability of the production of goods and services.
Achievement in the area of a key enabling technology as nanoelectronics will result in improvements
everywhere in economy and society. With smaller, more performing and smarter chip many products and
services can get better, cheaper, easier to handle, safer and more secure.