Prashanth Kandaswamy V

745 Camino Del Sur Apt #35 +1 805-886-5467

Goleta CA 93117 prashanthkandasw@umail.ucsb.edu

EDUCATION
Masters, Electrical and Computer Engineering GPA 3.88 Expected graduation
University of California, Santa Barbara December 2011
Specialization: VLSI testing / Digital design and Computer Architecture
Bachelors, Electronics & Communication Engineering GPA 3.6 May 2010
SSN College of Engineering, Anna University Chennai, India
COURSES
 VLSI testing techniques  Advanced computer architecture
 CMOS VLSI for Computer engineering  VLSI design validation
 Embedded system design  Software development for smart phones
 Advanced Architecture Distributed systems  VLSI project design

PROJECTS:
Implementation of DFT on RISC processor:
Implemented DFT for 8-bit RISC processor using Mentor Graphics’ DFT and test generation tools. The DFT
Advisor tool was used to implement full scan and partial scan design. FastScan and FlexTest was used to
generate test patterns for full and partial scan design respectively. High quality, non-overlapping test vectors
were generated for achieving desired coverage metrics.
Multilevel Cache hierarchy Design:
A behavioral Verilog simulation of three levels of memory hierarchy was designed. Four processors each
having its own L1 cache forms the first level. Two L2 communicating with four L1 cache forms the second
level and a main memory forms the level three.
Super Scalar Instruction Dispatch - Tomasulo’s Design:
Currently working on a Super Scalar Instruction Dispatch Processor capable of issuing two instructions per
clock cycle based on Tomasulo’s Algorithm using Verilog in ModelSim. The processor has various sub-blocks
such as Adder, Multiplier and its Reservation stations.
VLSI design validation
Written RTPG and directed test patterns to verify select modules in RISC OR1200 processor using Modelsim.
Aim was to hit maximum coverage with minimum test patterns.
Voice application on Spartan 3E
Implemented voice application on Xilinx Spartan 3E that can identify speech utterances. On identification it
communicates with a PC and opens a webpage based on uttered phrase. Done using STFT(Short Time
Fourier Transform) for meeting memory and time constraints.
3D Face Reconstruction on Android
Currently working on an application that can upload images of a human face, taken from Android mobile, to
a server (through wi-fi) which will process and return a 3D model of the face. A viewer for the received
image is developed using OpenGL ES on Android mobile.

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EXPERIENCE:
Internship, R&D lab CEERI: Central Electronic Engineering and Research Institute, Chennai [May-October 2009]
“Online Image Acquisition and Processing for steel grade classification” under the guidance of Mr. A. Sada
Siva Sarma(Scientist EII). Implemented on TI’s digital media board DM642 fed by a NIR camera.
UNDERGRADUATE PROJECTS
 A novel face and speaker recognition system was built and concocted into a rigid multimodal biometric
authentication system Dec ‘09-May’10.
 ‘Employee ID Verification system’ using Microchip PIC 18F8720 Microcontroller. Dec ‘08-Feb ‘09.
TECHNICAL TRAINING:
 Work stint at Indian Institute of Technology, Madras on the applications of Digital Signal Processing in the
Analog Devices lab unit. Hands on work in still image compression, echo cancellation and speech coding
using ADI-BF533.

SKILL SET:
Design tools: Mentor Graphics DFTAdvisor, Mentor Graphics FastScan, Mentor Graphics
Flextest, PODEM, Cadence Virtuoso
Simulation tool: MATLAB
Hardware Description Languages: Verilog
Graphics language OpenGL ES
Languages Known: C, Java, Assembly Language Programming - 8085/8086
Workbenches: Texas Instruments Code Composer Studio, Analog Devices Visual DSP.