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for organic TFTs

a,*

M. Estrada , A. Cerdeira a, J. Puigdollers b, L. Reséndiz a, J. Pallares c,

L.F. Marsal c, C. Voz b, B. Iñiguez c

a

Sección de Electrónica del Estado Sólido (SEES), Departamento de Ingenierı́a Eléctrica, CINVESTAV, Av. IPN No. 2508,

Apto. Postal 14-740, 07300 DF, Mexico

b

Departament dÉnginyeria Electronica, Universitat Politecnica de Catalunya, C/Jordi Girona, Modul C4, Barcelona 08034, Spain

c

Departament dÉnginyeria Electronica Eléctrica i Automatica, Universitat Rovira i Virgili, Avda. Paisos Catalans 26, 43007 Tarragona, Spain

Received 18 November 2004; received in revised form 14 February 2005; accepted 15 February 2005

Available online 31 March 2005

Abstract

In this paper we demonstrate the applicability of the uniﬁed model and parameter extraction method (UMEM), previously devel-

oped by us, to organic thin ﬁlm transistors, OTFTs.

The UMEM, which has been previously used with a-Si:H, polysilicon and nanocrystalline TFTs, provides a much rigorous and

accurate determination of main electrical parameters of organic TFTs than previous methods. Device parameters are extracted in a

simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model

parameter or using optimization methods. The method can be applied to both experimental and simulated characteristics of organic

TFTs, having diﬀerent geometries and mobility. It provides a very good agreement between transfer, transconductance and output

characteristics calculated using parameter values obtained with our extraction procedure and experimental curves. Diﬀerences in

mobility behavior, as well as other device features that can be analyzed using UMEM are discussed.

2005 Elsevier Ltd. All rights reserved.

eral diﬀerences with respect to crystalline (MOSFETs),

Simulation of devices requires both, an accurate amorphous, (a-Si:H TFTs) or polycrystalline Si (polySi

model to represent the behavior of the device and an TFTs) devices. According to measured transfer and out-

extraction method strictly related to this model to deter- put characteristics of organic TFTs, it has been observed

mine with precision the device parameters required by it that mobility usually increases with gate voltage. It has

and thus by simulation. Modeling of organic TFTs also been reported that mobility increases with VDS

(OTFTs) has been made, up to now, analytically or for a given value of VGS, in a more pronounced way

numerically, mostly using the same expressions as for than the mobility of a-Si:H devices with similar geome-

try, [1–3]. This increase of mobility with VDS has been

*

Corresponding author. Tel.: +52 55 50613786; fax: +52 55

related to hopping [4]; to a Frenkel–Poole type eﬀect

50613978. associated to traps in the material, [5] as well as; to

E-mail address: mestrada@cinvestav.mx (M. Estrada). the lowering of the emission barrier in traps located at

0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved.

doi:10.1016/j.sse.2005.02.004

1010 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016

the boundaries between crystals, since most materials Finally we present a complement to the UMEM in

used to fabricate OTFTs are polycrystalline, [6,7]. order to consider, if necessary, the non-ohmic contact

OTFTs can present deformation at the origin of the at drain and source, sometimes present in OTFTs. For

output characteristics, due to non-ohmic contacts at this last treatment, analytical expressions are also pro-

drain and source [8–10]. They can also have leakage cur- vided for modeling this eﬀect and for the extraction of

rent across the gate dielectric [11] and/or polarization ef- the required parameters.

fects [8], which can be signiﬁcant and have to be taken

into account.

In numerical simulations, the longitudinal ﬁeld 2. Main features of uniﬁed model and parameter

dependence of the mobility has been introduced by extraction method (UMEM)

external models, [5], evaluated by Monte Carlo [1], or

simply not considered, [12]. 2.1. Summary of steps to extract model parameters

Some authors have used simulation in SPICE using

the MOSFET model, to which some features as series The mobility dependence with gate voltage is de-

and non-linear resistance at drain and source are some- scribed as [15]:

times added, [8,2]. The use of the model 15 for a-Si:H c

ðV GS V T Þ a

devices in AIMSpice was reported in [13], with an addi- lFET ¼ l0 ¼ lFET0 ðV GS V T Þca ð1Þ

tional treatment of the series and non-linear OTFTs V aa

resistance. The non-linear OTFT resistance was also where lFET0 is the a value of mobility for low perpendi-

treated in [14]. Although this last approach has some cular and longitudinal electric ﬁeld, VT the threshold

advantages regarding previous, the method used voltage and ca and Vaa are ﬁtting parameters. l0 is usu-

for parameter extraction is numerical and among its ally taken as the band mobility for the material of the

disadvantages are a relatively big number of ﬁtting para- TFT under analysis. Since this parameter is usually esti-

meters, which can be determined by optimization mated, the ﬁtting parameter Vaa is used to adjust lFET0

methods when using AIMSpice, or through graphical to the experimental value of the low ﬁeld mobility for

or derivative methods which are troublesome and impre- the device being modeled. Parameter ca is related to

cise due to experimental errors. For example, with AIM- the conduction mechanism and can describe both an in-

Spice extractor, it is diﬃcult to obtain the same group of crease or decrease in mobility with VGS. In the ﬁrst case,

ﬁtting parameters for all modeled transistor curves, ca > 0 and in the second ca < 0. The ﬁrst behavior is typ-

which also lack physical meaning. In addition, some of ical of amorphous and nanocrystalline devices and is re-

the extraction procedures, require to previously assume lated to trap conduction mechanism, while a decrease in

values to some parameters in order to extract the rest of mobility with gate voltage appears in polycrystalline

them, that is, some parameters cannot be extracted inde- TFTs when surface scattering starts to be important.

pendently one from another [15]. In organic TFTs, as will be shown later, both behaviors

In the last years, we have been applying our uniﬁed were observed. In this way, extracted ﬁtting parameters

model and parameter extraction method (UMEM) ﬁrst can be used nevertheless, to analyze physical mecha-

to a-Si:H, [15,16], to polycrystalline, [17] and recently nisms that take place in the devices.

to nanocrystalline silicon transistors [18]. Among the Drain current in the linear and saturation regions is

advantages of this method are that all above threshold modeled as:

parameters are extracted from two transfer characteris-

W lFET ðV GS V T Þ

tics, one in the linear and the other in the saturation re- I DS ¼ C diel

gion and from the output characteristic of the device L 1 þ R WL C diel lFET ðV GS V T Þ

under study, using a single mathematical processing V DS ð1 þ k V DS Þ

h h im i1=m þ I 0 ð2Þ

involving and integral method that additionally reduces

experimental noise. The method can be used to compare 1 þ VVDSsat

DS

devices with diﬀerent geometries and fabrication condi- where W is the channel width, L is the channel length,

tions under the same parameter extraction conditions. Cdiel is the gate capacitance, R is source plus drain resis-

This method uses analytical expressions for both model- tance, I0 is the leakage current and m and k are ﬁtting

ing and parameter extraction, so calculations can be parameters related to the sharpness of the knee region

made using any program for mathematical calculations. and to the channel length modulation respectively.

In addition it was also implemented in AIMSpice [19]. Parameter k describes the variation of conductance with

In this paper we show that UMEM provides an excel- VDS in the saturation region.

lent tool for modeling OTFTs with diﬀerent geometries, The saturation voltage is deﬁned through the satura-

dielectric materials and fabrication processes. We apply tion modulation parameter aS:

it to analyze and compare the mobility behavior of four

diﬀerent types of pentacene TFTs. V DSsat ¼ aS ðV GS V T Þ ð3Þ

M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1011

For the extraction procedure in the above threshold the maximum gate voltage value you want to model.

regime, we will use the same integral function H(VGS) Select a value of VDS in the saturation region, not too

deﬁned in [15]: far from the knee of the output selected curve for which

R V GS the drain current IDS1 is known from measurements. This

I DS ðxÞdx

H ðV GS Þ ¼ 0 ð4Þ drain voltage value will be referred as VDS1 and should be

I DS ðV GS Þ equal to:

After substituting (1) in (2) and calculating H(VGS) from V DS1 ¼ aS ðV GS1 V T Þ ð9Þ

(4), the following expression is obtained for above

threshold regime: This value of IDS1 corresponds to IDSsat(VDSsat) in

1 expression (8).

H a ðV GS Þ ¼ ðV GS V T Þ ð5Þ Step no. 5: Parameter k is then extracted from:

2 þ ca

8 h h im i1=m 9

>

< ðI DS2 Þ2 ½1 þ R K lFET ðV GS1 Þ ðV GS1 V T Þ 1 þ asðVV DS2V Þ >

=

ðV DS2 Þ GS1 T 1

k¼ ; ð10Þ

>

: K lFET ðV GS1 Þ ðV GS1 V T Þ >

; V DS2

The generalized parameter extraction procedure for dif- where VDS2 is selected not too far from the maximum

ferent devices and operation regimes can be found in drain voltage measured in the characteristic to be mod-

[15–18]. The steps for the determination of the model eled. IDS2 is the measured drain current for the selected

parameters VT, ca, aS Vaa, m and k are summarized drain voltage VDS2.

below.

If the slope of the IDS–VGS curve in the linear region

Step no. 1: VT is obtained from the intercept, and ca is observed to decrease due to the presence of a series

from the slope in expression (5). resistance, the value of this resistance can be determined

Step no. 2: From 1 the experimental data, calculate as indicated in [15].

ðI DS Þ1þca vs. (VGS VT) and its slope Sl. OTFT can show a non-linear contact at drain and

The value of Vaa is extracted as: source. To model also this region, the following simple

1=ca and precise procedure can be used.

KV DS

V aa ¼ ; ð6Þ

Sl1þca 2.2. Modeling of OTFTs output characteristics when

non-ohmic contacts are present

where K ¼ WL l0 C diel . In this form, the three parame-

ters that determine the eﬀective change of the ﬁeld eﬀect If a non-ohmic contact is present at drain and source,

mobility in the above threshold regime are extracted. which is frequently observed in OTFTs, the external bias

Step no. 3: Using the saturation current characteristic applied, Vext, will fall part on the non-ohmic contact,

for VDS P VGS VT, calculate the slope (diode), Vdiode and part on the transistor, VDS, including

1=ð2þcaÞ

Ss in the linear region of I DSsat vs. its series resistance, that is:

(VGS VT). Parameter aS is extracted as:

pﬃﬃﬃ V DSext ¼ V DS þ V diode

Ss2þca V caaa 2

aS ¼ ð7Þ I DS kT I DS

K ¼ þn log

GðV GS ; V DS Þ q I do

Step no. 4: Parameter m, is calculated evaluating (2) at

VDSsat for a value of gate voltage near the I DS kT I DS

¼ þn log ; ð11Þ

maximum measured, neglecting R and k: GðV GS ; V DSext Þ n q I do

where

K lFET ðV GS Þ

m ¼ log 2= log

½1 þ K lFET ðV GS Þ ðV GS V T Þ

GðV GS ; V DSext Þ

aS ðV GS1 V T Þ

ð8Þ KlFET ðV GS Þ ðV GS V T Þ ð1 þ k V DSext Þ

I DSsat ðV DSsat Þ ¼ h m i1=m

ð1 þ R lFET ðV GS Þ ðV GS V T ÞÞ 1 þ VV DSext

DSsat

To determine IDSsat(VDSsat) select a measured output

characteristic for VGS = VGS1, where VGS1 is a value near ð12Þ

1012 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016

and n is a ﬁtting parameter to account for the real volt- The eﬀect of n is to provide the necessary displace-

age across the transistor when the diode resistance is ment and adjustment of the slope of the modeled curve

signiﬁcant. to the measured one, in the region of deformation.

To model output characteristics presenting this eﬀect, After determining n, calculate k from (11) and (12),

after following steps 1–4 previously described, the diode solving for a value of drain voltage VDSext = VDS2 (and

parameters must be determined. It must be indicated its corresponding IDS = IDS2) not too far from the maxi-

that for steps 1–4, the transfer curve selected must cor- mum drain voltage measured in the selected output

respond to a VDSext in the linear region, that at the same curve for VGS2.

time lies outside of the region aﬀected by the deforma- Finally, IDS vs. VDS is modeled substituting the

tion of the non-linear contact. extracted parameters in (11).

After parameters VT, ca, aS, Vaa and m are deter- 3. Experimental part and results

mined, select an output characteristic with VGS = VGS2

where the non-ohmic contact eﬀect is clearly seen. Plot Four diﬀerent pentacene TFTs, T1, T2, T3 and T4

the curve log(IDS) vs. VDSext and determine the slope, were studied. All of them are bottom gate pentacene

B, and the intercept, A, of this curve near the origin. TFTs on glass substrate. Transistor T1 uses polymethyl

Using the normal procedure for a diode: methacrylate (PMMA) as gate dielectric and were pre-

pared as indicated in [20]. The PMMA dielectric thick-

log e

n¼ ð13Þ ness is 700 nm thick with a dielectric constant of 3.9.

B kT

q Pentacene thickness was 160 nm. These devices have

L = 120 and W = 600 lm.

and T2 type transistors were fabricated by a process sim-

I do ¼ 10A : ð14Þ ilar as indicated in [21]. The gate dielectric is a 100 nm

polyvinylphenol (PVP) layer. Pentacene layer thickness

was of 30 nm, W = 500 lm and L = 50 lm.

2.2.2. Extraction of ﬁtting parameter n Transistors T3 type correspond to devices previously

The eﬀect of the presence of this diode is to reduce the reported in [21], with 120 nm polyvinylphenol (PVP)

drain current at small values of bias, when the diode layer as gate dielectric, 30 nm of pentacene layer,

resistance is high. As the external bias is increased be- W = 500 lm and L = 50 lm.

yond the knee of the I–V characteristic of the diode, Transistor T4 corresponds to devices previously re-

the drain current increases and starts to be determined ported in [22]. The gate dielectric was a 400 nm SiO2

mainly by the transistor. This means that in the output layer. The thickness of the pentacene layer was 50 nm,

characteristic, near or after the maximum slope in this W = 220 lm and L = 20 lm. Since we did not have mea-

region of deformation, most of the applied voltage starts sured characteristics of T4 type devices, we used simu-

to fall across the transistor. For this reason, parameter n lated characteristics in ATLAS1 to compare with

is determined as: output characteristics modeled using UMEM. Parame-

ters used for simulation were taken from [5], where it

I DS ðV GS2 ; V ext2 Þ I DS ðV GS2 ; V ext1 Þ

was shown that they provide an excellent agreement

G1ðV GS2 Þ G1ðV GS2 Þ with measured curves for these devices.

n¼ ð15Þ

½V DS2 V DS1 Trap distribution was taken as:

where IDS(VGS2, Vext2) and IDS(VGS2, Vext1) are the mea- ðEc EÞ

gatail ðEÞ ¼ gatail0 exp ð17Þ

sured current for the selected output characteristic at Eatail

two external bias Vext2 and Vext1 limiting an approxi-

mately linear region of the curve IDS vs. VDSext,, where ðE EV Þ

gdtail ðEÞ ¼ gdtail0 exp ð18Þ

the maximum slope of this curve is included. VDS2, Edtail

(VDS1) are determined substituting Vext2, (Vext1) and its

where gatail0 is the concentration of acceptor tail states at

corresponding IDS in (8).

conduction band Ec equal to1 2.5 · 1018 cm3; gdtail0 in

G1(VGS2) is the conductance in the linear region eval-

the concentration of donor tail states at valence band

uated for VGS = VGS2:

EV, equal to 1 · 1018 cm3 and Eatail = 0.129 eV and

KlFET ðV GS2 Þ ðV GS2 V T Þ Edtail = 0.5 eV are the activation energy for acceptor

G1ðV GS2 Þ ¼ : ð16Þ and donor tail states respectively.

ð1 þ R lFET ðV GS2 Þ ðV GS2 V T ÞÞ

parameters, respectively. 1

ATLAS is property of Silvaco International.

M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1013

Table 1

Technological parameters of pentacene transistors

Transistor Pentacene layer [nm] Dielectric gate W [lm] L [lm] Reference

Type [nm]

T1 160 PMMA 700 600 120 [20]

T2 30 PVP 100 500 50

T3 30 PVP 120 500 50 [21]

T4 50 SiO2 400 220 20 [5,22]

of ei = 3. The extended states concentration at valence

and conduction bands was taken as 2.88 · 1021 cm3.

Pentacene is considered to be p-type with hole concen-

tration of 5.75 · 1017 cm3.

According to [5], externally it was pﬃﬃﬃadded

ﬃ a ﬁeld

dependence in the form of a exp½b F , where F is

the longitudinal electric ﬁeld, a = 0.5 and b = 3 · 103

(V/cm)1/2, to account for the presence of a Frenkel–

Poole eﬀect.

Table 1 shows the summary of the fabrication param-

eters for the four types of transistors.

Fig. 2. Measured and modeled output characteristics of T2 type

Figs. 1–4 show measured and modeled output charac- transistor.

teristics of the four types of transistors described. As can

be seen, all devices characteristics analyzed in this work

can be very well modeled using UMEM, without the

need of any additional term to consider Frenkel–Poole

eﬀect.

In some OTFTs, the dependence of the drain current

with drain voltage in the saturation region of the output

characteristic is more pronounced that the observed in

a-Si:H devices, however it can be still well modeled

through parameter k. This is also in agreement with

reported by [13].

transistor.

for one transistor of each type of devices.

As we mentioned, one of the advantages of using

UMEM is the possibility of monitoring the behavior

of mobility, as well as to obtain distinguishing features

of each device. For example, from the extracted para-

meters indicated in Table 2, we can see that transistors

T1, T2 and T3 type are normally oﬀ, while T4 is nor-

Fig. 1. Measured and modeled output characteristics of T1 type mally on. Series resistance reduces from T1 to T4. In this

transistor. later case it is so small that cannot be determined.

1014 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016

transistor.

transistor in the linear and in the saturation regions.

Parameter as, which is related to the behavior of the out-

put characteristic at the onset of saturation, is higher for

transistors T2 and T3 type, which is also observed in the transfer curve, trying to cover the widest possible region

output characteristics in Figs. 2 and 3, where the linear where function H(VGS) is linear with VGS.

region is larger relative to the measured range of VDS. Another feature worth to remark is the comparison

Also parameter m, related to the knee of the curve at on- of the VT values obtained by our method and by the

set of saturation is approximately half the observed for standard

p ﬃﬃﬃﬃﬃﬃﬃ method for crystalline devices pﬃﬃﬃﬃﬃﬃﬃ basedð1þc

in the

Þ

transistors T2, T3 and T4 type. I DS vs. VGS. In Fig. 6 we plotted I DS and I DS a vs.

Fig. 5 shows agreement between modeled transfer VGS curves for one T1 type transistor. If VT is obtained

pﬃﬃﬃﬃﬃﬃﬃ

curves for T1 type transistor for two values of VDS, for this device using a I DS vs. VGS curve, as is fre-

one in the linear region (VDS = 1 V) and the other in quently done by authors, the value obtained is around

saturation, (VDS = 40 V). As can be seen, the agree- 18 V. This will not correspond to what is observed

ment is excellent, using the same group of ﬁtting param- from measured output characteristics, where transistor

eters for both curves. This is really diﬃcult to obtain is clearly oﬀ for VGS around 4 V. The cause of this is

with other extraction procedures, while using UMEM understood

pﬃﬃﬃﬃﬃﬃﬃ from Fig. 6, where it is clear that the curve

is easy, provided you correctly select the voltage range I DS vs. VGS does not present any region where you

in the linear and saturation region where the integral can assure that there is a linear behavior. However, with

ð1þc Þ

function H is evaluated. Table 2 also indicates the volt- the representation I DS a vs. VGS, there is a wide linear

age range used for each case. In general, best results are region, in which VT can be determined accurately. Say-

obtained when the voltage range in both regions is se- ing it in other words, OTFTs do not show the square

lected near the maximum slope of the corresponding root behavior of drain current with drain voltage typical

Table 2

Extracted parameters

T1 T2 T3 T4

Linear region voltage range (35–39) (8–11) (10–20) (60–100)

Saturation region voltage range (30–39) (8–11) (15–20) (80–100)

Output characteristic VGS [V] 40 14 20 40

VT [V] 4.1 2.6 3.9 +12.3

ca 1.9 0.6 0.15 0.072

Vaa [V] 1.7 · 103 106 1.4 · 103 1.7 · 104

lFET0 [cm2/V s] 7.4 · 107 0.058 0.52 0.7

R [kX] 1.1 · 104 200 14 0

as 0.39 1.7 1.4 0.935

m 1.27 2.8 2.97 2.8

k [1/V] 3.5 · 103 1.1 · 102 9.6 · 105 2 · 104

n – 8.9 – –

I0 [A] – 1.9 · 108 – –

n – 1.37 – –

M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1015

0.30 0.08

1/(1+γ a)

I IDSI

0.25 VDS = 40 V

5

γα = 3.07 0.06 T3

[µA]

1/2

a

0.20

γ

[V]

1/(1+γa )

0.15 0.04

µFET/µFETo

I IDS I

[µA]

0.10

0.02 T2

1/2

0.05

T4

0.00 0.00

-10 0 10 20 30 40 0

0 5 10 15

-VGS [V]

(a) IVGS-VTI [V]

7x10

if the present mobility model, (1), or the crystalline-like model is used.

6x10

-4 Transistor T1 type

-4

a

5x10

γ

of crystalline devices. In fact, other amorphous devices,

[V]

as for example a-Si:H and nanocrystalline Si TFTs, do 4x10

-4

µFET/µFETo

not show this dependence either. -4

3x10

OTFTs can present signiﬁcant VT shifts at room tem-

-4

perature when a positive or negative gate voltage is ap- 2x10

1x10

the current voltage characteristics. Since UMEM re-

quires measurements of transfer curves in linear and sat- 0

0 5 10 15 20 25 30 35

uration regions as well as the output characteristic, in (b) IVGS-VTI [V]

order to extract the device parameters, measurements

must be done so that gate and drain voltage variations Fig. 7. Relative behavior of mobility normalized to lFET0 as function

start from the same initial value in the three measured of the gate overvoltage. (a) For transistors T2, T3, and T4. (b) For

transistor T1.

curves, usually in the sense of increasing its absolute

value.

UMEM can also be used to determine VT shifts as dinal ﬁeld as the one included in [5]. According to results

was done in [23]. presented, it was perfectly possible to model the OTFTs

UMEM also allows to extract subthreshold parame- behavior of all OTFTs analyzed, with the common

ters in a-Si:H, polycrystalline and Si nanocrystalline expression (2), through parameter k.

TFTs, [16–18]. In the case of OTFTs, surface and gate For the other three types of transistors, mobility in-

leakage currents can be signiﬁcant, so subthreshold re- creases with VGS, resulting in positive values of ca. This

gion is usually determined by them and not by traps. mobility dependence with VGS of transistors T2 and T3

For this reason, it has not been possible up to now to type is similar to the observed for a-Si:H TFTs. Mobility

deal with this region. for T2 type transistors depends much less with VGS than

for T3 type transistors, which can be associated to a

3.2. Mobility behavior higher value of resistance, an order more. Transistor

T1 has much higher series resistance and lower eﬀective

Regarding the mobility model, parameter ca is related mobility compared to T2 and T3. The eﬀective mobility

to the dependence of mobility with VGS, while increases more rapidly with VGS, but remains at lower

lFET0 ¼ Vlc0a ﬁts the modeled value of mobility to its mea- absolute values, see Fig. 7b. This is supposed to be ob-

aa

sured value at low gate voltages slightly higher than VT. tained because the pentacene layer in T1 was deposited

Fig. 7a shows the relative behavior of mobility normal- at lower temperature and directly on top of the dielec-

ized to lFET0 for transistors T2, T3 and T4 type. As can tric, which is expected to produce smaller grains.

be seen transistor T4 shows a mobility decreasing with With the above analysis of the four diﬀerent types of

VGS, resulting in a negative value for parameter ca. As OTFTs, we have illustrated the applicability of UMEM

already indicated, the series resistance is very small for to modeling OTFTs, as well as its advantages in inter-

T4 type devices and VT is positive and quite large, which preting and comparing diﬀerences in their behavior

is not a typical behavior for these OTFTs. However, the through the extracted parameters, which in this case

model can represent well their output characteristics are not only ﬁtting parameters. This advantage is not

without adding any other dependence with the longitu- trivial compared with other methods and is especially

1016 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016

important for modeling and analyzing OTFTs, where the tics of pentacene-based thin ﬁlm transistors. Thin Solid Films

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