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Non-Idealities in SIMULINK
A. Fornasari, P. Malcovati and F. Maloberti
Department of Electrical Engineering, University of Pavia
Via Ferrata 1, 27100 Pavia, Italy
E-mail: {andrea.fornasari, piero.malcovati, franco.maloberti}@unipv.it
Abstract—The goal of this paper is to present an extension of The square root of this value, Vn, was finally used in the
the behavioral models, implemented in the Matlab/Simulink™ model to scale the output of a Gaussian distributed random
environment, previously presented in [1, 2] and available in signal. This model allows very fast simulations and can be
[3]. This toolbox allows us to simulate at behavioral level most used without any worry, if one of the two following consid-
of the switched-capacitor (SC) sigma-delta ( ) modulator erations is satisfied:
non-idealities, such as sampling jitter, kT/C noise and opera- • the flicker noise (1/f) can be neglected in the specific field
tional amplifier limitations (finite bandwidth, finite DC gain, of application (wide band converters);
slew rate and saturation). Although very effective in simulating
• the noise spectrum is folded, due to sampling operation, a
wide-band, medium-resolution converters the lack of a number of time sufficient to be considered white.
model for flicker noise and multi-bit quantizers makes this If these two conditions are not satisfied a more accurate
toolbox less attractive for simulating narrow band high resolu-
model has to be used.
tion converters. The proposed extension not only fixes this limi-
tation, but introduces a predictive model of the effect of
capacitor mismatch in the internal multi-bit D/A converter.
SOURCE
z-1 z-1
1-z-1 1-z-1
I. INTRODUCTION Discrete Filter Discrete Filter
A/D
speed of the simulations. In this paper two additional blocks Figure 1. modulator topology porposed in [4] and used to test
are presented. The first allows us to include in the Matlab behavioral blocks.
environment data about the noise power spectral density
(PSD) of the operational amplifiers obtained by a circuit
simulator (e.g. Spectre or Eldo), including flicker noise. The III. COLORED NOISE MODEL
second one allows us to estimate the impact of the mis- The noise PSD (expressed in V2/Hz), provided by most
matches among capacitors in the feedback DAC of a multi- transistor-level simulator, can be considered as the spectrum
bit modulator on the signal-to-noise and distortion ratio of the sum of N sine-waves with arbitrary phase (Fourier
(SNDR). In order to validate the proposed models, we simu- theorem), each having a power equal to the area of a slide of
lated both at behavioral and transistor level the second-order the PSD as large as FMAX divided by N (i.e. as large as a bin)
switched-capacitor (SC) modulator architecture shown in
Fig. 1 [4], which features a 12 levels internal DAC (11 com- N
parators in the ADC). VNoise = a i sin2 F N MAX
it + i ,
(1)
i=1
II. NOISE MODEL This simple consideration is the basis for the proposed noise
In the original toolbox (SD Toolbox) all the possible model, whose flow chart is shown in Fig. 2. Basically, we
noise sources (mainly the contributions of the operational pass in the Matlab environment a detailed description of the
amplifiers and of the voltage references) were supposed to be noise PSD, elaborate it (basically folding it around the sam-
white. The parameter Vn of the noise model (i.e. the noise pling frequency Fs) and calculate the value of VNoise at the
rms voltage) had to be evaluated using a transistor-level end of each clock period (Ts). The first possibility to pass the
noise simulation in the proper clock phase and including all PSD in the Matlab environment is to sample the waveform
the load capacitors. The output referred noise PSD obtained (Fig. 3) provided by the transistor-level simulator (e.g. using
from the simulation had then to be integrated over the whole the Ocean commands in the Cadence environment) and to
frequency spectrum, thus obtaining the total noise power Vn2. reconstruct the function in Matlab. A simpler possibility is to
k 1
SN = c + 1 . (2)
f 1 + f 2 f P2
f C3 yC f C f P2 yC + 2 f P3 y P
c=
(fC f P )f P2
(3)
k1 =
(
f C f C2 yC + f P2 yC + 2 f P2 y P )
(fC f P )f P Figure 3. Noise output PSD of an operational amplifier obtained from a
circuit simulator (black) and reconstructed by Matlab (red). The PSD
as shown in Fig. 3. integral on 1 GHz bandwidth is 1.089 nV2, which means Vn=33 V.
without folding
considering folding
115
120
125
PSD [dB]
f
130
135
140
3 4 5 6
10 10 10 10
Frequency [Hz]
Figure 4. Noise output PSD in the band [0 FS] before and after having
Figure 2. Flow chart of the proposed colored noise model. considered the folding due to the sampling operation.
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has already been reported in Fig. 2. A transistor level noise TABLE I. SIMULATED PERFORMANCES
simulation (in time domain) of the modulator with
Fs=2.5 MHz
Fs=1.25 MHz and OSR=256 was made to verify the im-
provement in simulation accuracy of the proposed colored OSR=512 Bandwidth=2.4 kHz
noise block.
Model SNR [dB] Bit
−110
Colored Noise Model
Ideal 142.6 23.4
Colored Noise Model with Autozero
SD Toolbox Model SD Toolbox 109.6 17.9
−115
SD Toolbox update 99.4 16.2
SD Toolbox update w/ autozero 110.5 18.1
−120
OSR=256 Bandwidth=4.9 kHz
PSD [dB]
60
Model SNR [dB] Bit
80
SD Toolbox 111.3 18.2
100
SD Toolbox update 97.7 15.9
120
SD Toolbox update w/ autozero 108.0 17.6
OSR=256 Bandwidth=2.4 kHz
140
It is well known [5] that a mismatch among capacitors in OSR=64 Bandwidth=9.7 kHz
the internal DAC of a multi-bit modulator causes an in- Model SNR [dB] Bit
crease in the noise floor and in the harmonic distortion. Per-
formance degradation is proportional to capacitor standard Ideal 98.6 16.1
deviation (), given by: SD Toolbox 95.9 15.6
SD Toolbox update 93.5 15.2
C k
= [% / μm] (4) SD Toolbox update w/ autozero 95.3 15.5
C WL
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Sampling Jitter
Jitter
Simulink block SD Toolbox SD Toolbox update
SOURCE b g g b
kT/C kT/C
in in
g OpNoise
ADC Vout
z-1 z-1
ADC-DAC
1-
g OpNoise 1-z -1 1-z-1 OUTPUT
DAC
REAL REAL
Integrator Integrator
2
b g
kT /C Gain
in
Noise
Figure 7. Simulink model of the modulator simulated with blocks introduced in the previous version of SD Toolbox and those proposed in this paper
Therefore, is inversely proportional to the square root of DAC. This shrewdness is fundamental to avoid overrating
the capacitor size (the constant k depends on the technology mismatch effect on the output spectrum.
and is usually provided by the silicon foundry). Considering
that the sampling capacitor value impacts the constraints of CONCLUSIONS
almost all basic building blocks (e.g. operational amplifiers
and voltage references) it has to be determined at the very In this paper we presented an extension of the
beginning of the design phase. This makes approaches based SD Toolbox, which includes a more general noise model
on circuit simulator (e.g. Montecarlo simulation) ineffective with also flicker noise and a multibit quantizer model con-
(not only time consuming). sidering capacitor mismatches. Transistor level simulation
have demonstrated that, under specific conditions, the pro-
-0
bw posed noise model achieves results by far more accurate than
capacitor mismatch not considered
capacitor mismatch considered
the original one. Moreover, the multibit quantizer model
-20 allows us to accurately estimate the sampling capacitance
value required for achieving a given harmonic distortion at
-40 the very early stage of the design.
SFDR = 96 dB
-60
REFERENCES
PSD [dB]
-80
3
[1] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto,
7
F. Maloberti, “Modeling sigma-delta modulator non-idealities in
th 5th th
9th
-100 SIMULINK”, Proceedings of ISCAS '99, Vol. 2, , pp. 384-387, 1999.
[2] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, F. Cusinato, A.
-120 Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta
modulators”, IEEE Trans. on Circuits and Systems I, Vol. 50, No. 3,
-140
pp. 352-364, 2003.
[3] Category: Control Systems, File: SD Toolbox [Online]. Available:
-160 http://www.mathworks.com/matlabcentral/fileexchange
5E2 1E3 2E3 3E3
Frequency [Hz] [4] J. Silva, U. Moon, J. Steensgaard, G. Temes; “Wideband low-
distortion delta-sigma ADC topology”, Electronics Letters, Vol. 37,
Figure 8. modulator output spectrum with and without capacitor pp. 737-738, June 2001.
mismatch. The FFT is performed on a window of 217 points.
[5] C. Enz and G. Temes, “Circuit techniques for reducing the effects of
op-amp imperfections: autozeroing, correlated double sampling and
Therefore, we developed a block which models the ADC chopper stabilization”, Proc. IEEE, Vol. 84, pp. 584-614, Nov. 1996.
and DAC of a modulator, including the mismatch effects. [6] SIMULINK and MATLAB Users Guides, The MathWorks, Inc.,
This block can be used to evaluate if, given a sampling ca- Natick, MA, 1997.
pacitor size, the performance degradation due to mismatch [7] S. Norsworthy, R. Schreier, G. Temes, “Delta-sigma data converters:
can be considered negligible with respect to thermal noise, or Theory, design and simulation”, IEEE Press, Piscataway, NJ, 1997.
if some correction technique, e.g. dynamic element matching
(DEM), has to be applied (Fig. 8). The internal DAC was
supposed to have an odd symmetry (as it happens in reality
in all fully differential circuits and in all single ended circuits
carefully designed), which means that the same elements are
used to construct both positive and negative values. Under
this assumption no even distortion can be introduced by
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