CONTENTS

PAGE NO.

Chapter ABSTRACT............................................................ 7
Chapter-1 Introduction........................................................... 9
Chapter-2 Hardware
2.1 Block diagram...................................................... 12
2.2 Hardware description......................................... 13
i) MAX232.............................................................. 13
ii) LDR..................................................................... 15
iii) Analog to Digital Converters............................ 16
Chapter-3 I2C-BUS
3.1 I2C-BUS Concept................................................ 18
3.2 General characteristics....................................... 20
3.3 Start&stop condition.......................................... 21
3.4 Transfering data................................................. 22
3.5 Synchronisation.................................................. 24
3.6 Arbitration........................................................ 25

Chapter-4 ADDRESSING FORMATS OF I2C-BUS

4.1 7-bit addressing.................................................... 29
4.2 10-bit addressing.................................................. 31
4.3 Fast mode............................................................ 35
4.4 High speed mode................................................ 36
Chapter-5 Design Calculation 39
Chapter-6 I/0 EXPANDERS
6.1 Features................................................................. 43
6.2 General description.............................................. 44
6.3 Bus Expanders,Hubs,buffers& repeaters…… 45
6.4 Electrical connections of lines ……………… 46

1
Chapter-7 Memory Types
7.1 Volatile Memory…………………………………….. 50
i) RAM…………………………………………….. 50
ii) DDR SDRAM………………………………….. 51
7.2 Non-Volatile memory…………………………. 52
7.3 Flash Memory…………………………………. 52
7.4 EEPROM
i) Features …………………………………….. 53
ii) Pin diagram………………………………….. 54
iii) Device operation…………………………….. 56
iv) Device Addressing ……………………………. 57
v) Data Security………………………………… 58
vi) Read Operation…………………………………. 59
Chapter-8 RTC
8.1 Features………………………………………….. 62
8.2 Pin Description…………………………………. 64
8.3 Block Diagram………………………………….. 65
Chapter-9 Software Implementation
9.1 Keil software…………………………………. 70
9.2 Wait for read operation……………………. 72
9.3 Wait for write operation…………………….. 73
9.4 EEPROM coding…………………………….. 75
9.5 RTC coding………………………………….. 85

CONCLUSION................................................ 92
REFERENCES............................................... 93

2
ABSTRACT

3
ABSTRACT:

I2C bus for interfacing serial EEPROM and LM35 using microcontroller: The
circuit is also provided with an RS232 port for connecting with PC to send commands for
reading/writing EEPROM or setting date/time in RTC.

Communication with PC is done through Hyper Terminal. A screen shot of the

message sent to PC by microcontroller immediately after power ON is shown in the
figure at the left, where the user is asked to enter choice from the menu options related to
EEPROM and LM35. User can store data in EEPROM, or when he wants to know the
Environmental conditions. The option will be provided and data will be retrieved from
EPROM and it will be display on pc.

The measurements of temperature, atmospheric pressure and relative humidity

remotely by using the appropriate sensors are not only important in environmental or
weather monitoring but also crucial for many industrial processes. A device for weather
monitoring has been developed as described in this paper to monitor and display the
temperature, pressure and relative humidity of the atmosphere, using analogue and digital
components. The analogue outputs of the sensors are connected to a microcontroller
through an ADC for digital signal conversion and data logging. An LCD display is also
connected to the microcontroller to display the measurements. For analysis and archiving
purposes, the data can be transferred to a PC with a graphical user interface program
through a USB link.

4
 CHAPTER-1
INTRODUCTION

5
INTRODUCTION:

Communication network systems are rapidly growing in size and complexity.

These systems have many high speed integrated circuits with critical operating
parameters and must provide extremely reliable service with zero down time. To
maintain the performance of these systems, adequate environmental monitoring must be
performed, so a failure or a data trend leading to a potential failure can be rapidly
identified. Furthermore, this monitoring must be performed cheaply to keep system costs
low.
The I2C (Inter-Integrated Circuit) Bus is a two-wire, low to medium speed,
communication bus (a path for electronic signals) developed by Philips Semiconductors
in the early 1980s. I2C was created to reduce the manufacturing costs of electronic
products. It provides a low-cost, but powerful, chip-to-chip communication link within
these products. Initial applications for I2C included volume and contrast control in radios
and televisions. Over the past decade, I2C has expanded its communications role to
include a wide range of applications.
The I2C Bus is a time-proven, industry standard, communication protocol used in a
wide variety of electronic products. Its low cost and powerful features make I2C ideal for
low to medium speed chip-to-chip communications. I2C is supported by a large and
growing number of semiconductor and system manufacturers. These companies offer a
variety of electronic devices, including memories, input and output devices, sensors of
many types, real-time clocks, displays, data entry devices, and much more.I2C is an
effective technology that can lower product costs and increase product performance.
It is a simple, low band width, short distance protocol, most available i2c devices
operate at speeds up to 400kbps, with some venturing up into the low megahertz range.
I2C is easy to use to link multiple devices together since it has a built-in addressing

6
scheme. Examples of simple I2C-compatible devices found in embedded systems include
EEPROMs, thermal sensors, and real-time clocks. I2C is also used as a control interface
to signal processing devices that have separate, application-specific data interfaces.

In all, Philips, National Semiconductor, Xicor, Siemens, and other manufacturers

offer hundreds of I2C-compatible devices. Initial applications for I2C included volume
and contrast control in radios and televisions. Over the past decade, I2C has expanded its
communications role to include a wide range of applications.
The I2C (Inter-Integrated Circuit) Bus is a two-wire, low to medium speed,
communication bus (a path for electronic signals) developed by Philips Semiconductors
in the early 1980s. I2C was created to reduce the manufacturing costs of electronic
products. It provides a low-cost, but powerful, chip-to-chip communication link within
these products. Initial applications for I2C included volume and contrast control in radios
and televisions. Over the past decade, I2C has expanded its communications role to
include a wide range of applications.
Today, the I2C bus is used in many other application fields than just audio and
video equipment. The bus is generally accepted in the industry as a de-facto standard.
The I2C bus has been adopted by several leading chip manufacturers like Xicor, ST
Microelectronics, Infineon Technologies, Intel, Texas Instruments, Maxim, Atmel,
Analog Devices and others.

All I2C-bus compatible devices incorporate an on-chip interface which allows

them to communicate directly with each other via the I2C-bus. This design concept
solves the many interfacing problems encountered when designing digital control
circuits. I2C has become a de facto world standard that is now implemented in over 1000
different ICs and is licensed to more than 50 companies.

7
CHAPTER-2
HARDWARE

8
2.1 BLOCK DIAGRAM:

9
 PC

RS
232

MAX
232

Micro I2C
Controller Protocol
EEPROM

ADC

LDR

2.2 Hardware description:

i) MAX232:
The MAX232 is a dual driver/receiver that includes a capacitive voltage generator
to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts
TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical

10
threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each
driver converts TTL/CMOS input levels into TIA/EIA-232-F levels.

FEATURES:
 Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28
 Operates From a Single 5-V Power Supply With 1.0-F Charge-Pump
Capacitors
 Operates Up To 120 kbit/s,
 Two Drivers and Two Receivers,
 ±30-V Input Levels,
 Low Supply Current ...8 ma Typical,
 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A),
 Upgrade With Improved ESD (15-kV HBM) and 0.1-F Charge-Pump
Capacitors,
 Available With the MAX202.

Applications:
 TIA/EIA-232-F,
 Battery-Powered Systems,
 Terminals,
 Modems, and
 Computers.

Pin diagram:

11
 In this application note the software modules are developed in C language, with
RVDK environment. The software implemented to manage read and write operations
between the STR71x I2C interface and the M24C08 is divided in three parts:

Write: first, the program writes the contents of a predefined buffer to the memory
starting from address 0x00 of Block3.

Wait: then, it waits until the write operation is finished,

Read: finally it reads the data already written.

ii) LDR (Light dependent resistance):

12
 A photo resistor or light dependent resistor or cadmium sulfide (CdS) cell is a
resistor whose resistance decreases with increasing incident light intensity. It can also be
referenced as a photoconductor.

A photo resistor is made of a high resistance semiconductor. If light falling on the

device is of high enough frequency, photons absorbed by the semiconductor give bound
electrons enough energy to jump into the conduction band. The resulting free electron
(and its hole partner) conduct electricity, thereby lowering resistance.

A photoelectric device can be either intrinsic or extrinsic. An intrinsic

semiconductor has its own charge carriers and is not an efficient semiconductor, e.g.
silicon. In intrinsic devices the only available electrons are in the valence band, and
hence the photon must have enough energy to excite the electron across the entire band
gap. Extrinsic devices have impurities, also called dopants, and added whose ground state
energy is closer to the conduction band; since the electrons do not have as far to jump,
lower energy photons (i.e., longer wavelengths and lower frequencies) are sufficient to
trigger the device.

Applications:

Photo resistors come in many different types. Inexpensive cadmium sulfide cells
can be found in many consumer items such as camera light meters, street lights, clock
radios, alarms, and outdoor clocks.

13
 They are also used in some dynamic compressors together with a small
incandescent lamp or light emitting diode to control gain reduction.

Lead sulfide and indium antimonite LDRs are used for the mid infrared spectral
region. Ge:Cu photoconductors are among the best far-infrared detectors available, and
are used for infrared astronomy and infrared spectroscopy.

iii) Analog to digital converter:

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device

which converts continuous signals to discrete digital numbers. The reverse operation is
performed by a digital-to-analog converter (DAC).

Typically, an ADC is an electronic device that converts an input analog voltage

(or current) to a digital number. However, some non-electronic or only partially
electronic devices, such as rotary encoders, can also be considered ADCs. The digital
output may use different coding schemes, such as binary, Gray code or two's complement
binary.

APPLICATIONS:
AD converters are used virtually everywhere where an analog signal has to be
processed, stored, or transported in digital form.
Fast video ADCs are used, for example, in TV tuner cards. Slow on-chip 8, 10, 12,
or 16 bit ADCs are common in microcontrollers. Very fast ADCs are needed in digital
oscilloscopes, and are crucial for new applications like software defined radio..

14
Chapter-3
I2C BUS

15
3.1 I2C bus concept:

The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two
wires, serial data (SDA) and serial clock (SCL), carry information between the devices
connected to the bus. Each device is recognized by a unique address — whether it’s a
microcontroller, LCD driver, memory or keyboard interface — and can operate as either
a transmitter or receiver, depending on the function of the device. Obviously an LCD
driver is only a receiver, whereas a memory can both receive and transmit data. In
addition to transmitters and receivers, devices can also be considered as masters or slaves
when performing data transfers. A master is the device which initiates a data transfer on
the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.

Fig1: Example of i2c-bus configuration using two micro controller

The I2C-bus is a multi-master bus. This means that more than one device capable
of controlling the bus can be connected to it. As masters are usually micro-controllers,
let’s consider the case of a data transfer between two microcontrollers connected to the
I2C-bus .This highlights the master-slave and receiver-transmitter relationships to be

16
found on the I2C-bus. It should be noted that these relationships are not permanent, but
only depend on the direction of data transfer at that time.
The transfer of data would proceed as follows:

1. Suppose microcontroller A wants to send information to microcontroller B:

 Microcontroller A (master), addresses microcontroller B (slave)
 Microcontroller A (master-transmitter), sends data to
microcontroller B (slaver)
 Microcontroller A terminates the transfer.

2. If microcontroller A wants to receive information from microcontroller B:

 Microcontroller A (master) addresses microcontroller B (slave)
 Microcontroller A (master-receiver) receives data from microcontroller
B (slave-transmitter)
 Microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the
transfer.
The possibility of connecting more than one microcontroller to the I2C-bus means
that more than one master could try to initiate a data transfer at the same time. To avoid
the chaos that might ensue from such an event — an arbitration procedure has been
developed. This procedure relies on the wired-AND connection of all I2C interfaces to
the I2C-bus. If two or more masters try to put information onto the bus, the first to
produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration. The clock
signals during arbitration are a synchronized combination of the clocks generated by the
masters using the wired-AND connection to the SCL line. Generation of clock signals on
the I2C-bus is always the responsibility of master devices; each master generates its own
clock signals when transferring data on the bus. Bus clock signals from a master can only
be altered when they are stretched by a slow-slave device holding-down the clock line, or
by another master when arbitration occurs.

17
3.2 GENERAL CHARACTERISTICS:

Both SDA and SCL are bidirectional lines, connected to a positive supply voltage
via a pull-up resistor (see Figure 2). When the bus is free, both lines are HIGH. The
output stages of devices connected to the bus must have an open-drain or open-collector
in order to perform the wired-AND function. Data on the I2C-bus can be transferred at a
rate up to 100 kbit/s in the standard-mode, or up to 400 kbit/s in the fast-mode. The
number of interfaces connected to the bus is solely dependent on the bus capacitance
limit of 400pF.

Fig2: Connection of i2c bus devices to the i2c bus

18
BIT TRANSFER:
Due to the variety of different technology devices (CMOS, NMOS, bipolar) which
can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are
not fixed and depend on the associated level of VDD (see Section 15.0 for Electrical
Specifications). One clock pulse is generated for each data bit transferred.
Data validity:
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH or LOW state of the data line can only change when the clock signal on the SCL
line is LOW.

Fig3: bit transfer on the i2c bus

3.3 START and STOP conditions:
Within the procedure of the I2C-bus, unique situations arise which are defined as
START and STOP conditions (see Figure 3).

19
 A HIGH to LOW transition on the SDA line while SCL is HIGH is one such
unique case. This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition. START and STOP conditions are always generated by the master.
The bus is considered to be busy after the START condition. The bus is considered
to be free again a certain time after the STOP condition. Detection of START and STOP
conditions by devices connected to the bus is easy if they incorporate the necessary
interfacing hardware. However, microcontrollers with no such interface have to sample
the SDA line at least twice per clock period in order to sense the transition.

3.4 TRANSFERRING DATA:

Byte format:
Every byte put on the SDA line must be 8-bits long. The number of bytes that can
be transmitted per transfer is unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant bit (MSB) first (Figure 5)
If a receiver can’t receive another complete byte of data until it has performed some
other function, for example servicing an internal interrupt, it can hold the clock line SCL
LOW to force the transmitter into a wait state. Data transfer then continues when the
receiver is ready for another byte of data and releases clock line SCL.

20
 In some cases, it’s permitted to use a different format from the I2C-bus format (for
CBUS compatible devices for example). A message which starts with such an address
can be terminated by generation of a STOP condition, even during the transmission of a
byte.

Fig5: Data transfer on the i2c bus

Acknowledge:
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse
is generated by the master. The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge clock pulse so
that it remains stable LOW during the HIGH period of this clock pulse (Figure 6).

21
 Fig6: Acknowledge on the i2c bus

Of course, set-up and hold times must also be taken into account. Usually, a
receiver which has been addressed is obliged to generate an acknowledge after each byte
has been received, except when the message starts with a CBUS address. When a slave-
receiver doesn’t acknowledge the slave address (for example, it’s unable to receive
because it’s performing some real-time function), the data line must be left HIGH by the
slave. The master can then generate a STOP condition to abort the transfer.
If a slave-receiver does acknowledge the slave address but, some time later in the
transfer cannot receive any more data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge on the first byte to follow. The
slave leaves the data line HIGH and the master generates the STOP condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the
slave-transmitter by not generating an acknowledge on the last byte that was clocked out
of the slave. The slave-transmitter must release the data line to allow the master to
generate a STOP or repeated START condition.

3.5 Synchronization:
All masters generate their own clock on the SCL line to transfer messages on the
I2C-bus. Data is only valid during the HIGH period of the clock. A defined clock is
therefore needed for the bit-by-bit arbitration procedure to take place.

22
 Clock synchronization is performed using the wired-AND connection of I2C
interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line
will cause the devices concerned to start counting off their LOW period and, once a
device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH
state is reached (Figure 7).

Fig7:Clock synchronization during the arbitration procedure

However, the LOW to HIGH transition of this clock may not change the state of
the SCL line if another clock is still within its LOW period. The SCL line will therefore
be held LOW by the device with the longest LOW period. Devices with shorter LOW
periods enter a HIGH wait-state during this time. When all devices concerned have
counted off their LOW period, the clock line will be released and go HIGH. There will
then be no difference between the device clocks and the state of the SCL line, and all the
devices will start counting their HIGH periods. The first device to complete its HIGH
period will again pull the SCL line LOW. In this way, a synchronized SCL clock is
generated with its LOW period determined by the device with the longest clock LOW
period, and its HIGH period determined by the one with the shortest clock

23
3.6 Arbitration:
A master may start a transfer only if the bus is free. Two or more masters may
generate a START condition within the minimum hold time (tHD; STA) of the START
condition which results in a defined START condition to the bus. Arbitration takes place
on the SDA line, while the SCL line is at the HIGH level, in such a way that the master
which transmits a HIGH level, while another master is transmitting a LOW level will
switch off its DATA output stage because the level on the bus doesn’t correspond to its
own level.
Arbitration can continue for many bits. Its first stage is comparison of the address
bits (addressing information is in Sections 9.0 and 13.0). If the masters are each trying to
address the same device, arbitration continues with comparison of the data. Because
address and data information on the I2C-bus is used for arbitration, no information is lost
during this process.
A master which loses the arbitration can generate clock pulses until the end of the
byte in which it loses the arbitration. If a master also incorporates a slave function and it
loses arbitration during the addressing stage, it’s possible that the winning master is
trying to address it. The losing master must therefore switch over

The moment there is a difference between the internal data level of the master
generating DATA 1 and the actual level on the SDA line, its data output is switched off,

24
which means that a HIGH output level is then connected to the bus? This will not affect
the data transfer initiated by the winning master.
Since control of the I2C-bus is decided solely on the address and data sent by
competing masters, there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is
transmitted to the I2C-bus. If it’s possible for such a situation to occur, the masters
involved must send this repeated START condition or STOP condition at the same
position in the format frame.

In other words, arbitration isn’t allowed between:

 A repeated START condition and a data bit
 A STOP condition and a data bit
 A repeated START condition and a STOP condition.

Use of the clock synchronizing mechanism as a handshake:

In addition to being used during the arbitration procedure, the clock
synchronization mechanism can be used to enable receivers to cope with fast data
transfers, on either a byte level or a bit level.
On the byte level, a device may be able to receive bytes of data at a fast rate, but
needs more time to store a received byte or prepare another byte to be transmitted. Slaves
can then hold the SCL line LOW after reception and acknowledgement of a byte to force
the master into a wait state until the slave is ready for the next byte transfer in a type of
handshake procedure.
On the bit level, a device such as a microcontroller without, or with only a limited
hardware I2C interface on-chip can slow down the bus clock by extending each clock
LOW period. The speed of any master is thereby adapted to the internal operating rate of
this device.

25
 Chapter -4
Addressing Formats of I2C-bus

26
4.1 7-BIT ADDRESSING:

Data transfers follow the format shown in Figure 8. After the START condition
(S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is
a data direction bit (R/W) —a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates
a request for data (READ). A data transfer is always terminated by a STOP condition (P)
generated by the master. However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address another slave without first
generating a STOP condition. Various combinations of read/write formats are then
possible within such a transfer.

Fig8: complete data transfer

Possible data transfer formats are:

27
  Master-transmitter transmits to slave-receiver. The transfer direction is not
changed.

 Master reads slave immediately after first byte :

At the moment of the first acknowledge, the master-transmitter becomes a master-
receiver and the slave-receiver becomes a slave-transmitter. This acknowledge is still
generated by the slave.
The STOP condition is generated by the master

 Combined format: During a change of direction within a transfer, the

START condition and the slave address are both repeated, but with the R/W

28
 bit reversed. If a master receiver sends a repeated START condition, it has
previously sent a not acknowledge (A).

NOTES:

 Combined formats can be used, for example, to control a serial memory.

During the first data byte, the internal memory location has to be written.
After the START condition and slave address is repeated, data can be
transferred.
 All decisions on auto-increment or decrement of previously accessed memory
locations etc. are taken by the designer of the device.
 Each byte is followed by an acknowledgement bit as indicated by the A or A
blocks in the sequence.
 I2C-bus compatible devices must reset their bus logic on receipt of a START
or repeated START condition such that they all anticipate the
 Sending of a slave address.

EXTENSIONS TO THE I2C-BUS SPECIFICATION:

The I2C-bus with a data transfer rate of up to 100 kbit/s and 7-bit addressing has
now been in existence for more than ten years with an unchanged specification. The
concept is accepted world-wide as a de facto standard and hundreds of different types of
I2C-bus compatible ICs are available from Philips and other suppliers.

4.2 10-BIT ADDRESSING:

29
 The 10-bit addressing does not change the format in the I2C-bus specification.
Using 10 bits for addressing exploits the reserved combination 1111XXX for the first
seven bits of the first byte following a START (S) or repeated START (Sr) condition as
explained in Section 9.1. The 10-bit addressing does not affect the existing 7-bit
addressing. Devices with 7-bit and 10-bit addresses can be connected to the same I2C-
bus, and both 7-bit and 10-bit addressing can be used in a standard-mode system (up to
100 kbit/s) or a fast-mode system (up to 400 kbit/s).
Although there are eight possible combinations of the reserved address bits
1111XXX, only the four combinations 11110XX are used for 10-bit addressing. The
remaining four combinations 11111XX are reserved for future I2C-bus enhancements.

Definition of bits in the first two bytes

The 10-bit slave address is formed from the first two bytes following a START
condition (S) or a repeated START condition (Sr). The first seven bits of the first byte are
the combination 11110XX of which the last two bits (XX) are the two most-significant
bits (MSBs) of the 10-bit address; the eighth bit of the first byte is the R/W bit that
determines the direction of the message. A ‘zero’ in the least significant position of the
first byte means that the master will write information to a selected slave. A ‘one’ in this
position means that the master will read information from the slave.
If the R/W bit is ‘zero’, then the second byte contains the remaining 8 bits
(XXXXXXXX) of the 10-bit address. If the R/W bit is ‘one’, then the next byte contains
data transmitted from a slave to a master

Formats with 10-bit addresses

Various combinations of read/write formats are possible within a transfer that
includes 10-bit addressing.
Possible data transfer formats are:

 Master-transmitter transmits to slave-receiver with a 10-bit slave address. The

transfer direction is not changed (shown below).

30
 When a 10-bit address follows a START condition, each slave compares the first
seven bits of the first byte of the slave address (11110XX) with its own address
and tests if the
 Eighth bit (R/W direction bit) is 0. It is possible that more than one device will
find a match and generate an acknowledge (A1). All slaves that found a match
will compare the eight bits of the
 Second byte of the slave address (XXXXXXXX) with their own addresses, but
only one slave will find a match and generate an acknowledge (A2). The
matching slave will remain addressed by the master until it receives a STOP
condition (P) or a repeated START condition (Sr) followed by a different slave
address.
 Master-receiver reads slave- transmitter with a 10-bit slave address. The transfer
direction is changed after the second R/W bit (Figure 30).

 Up to and including acknowledge bit A2, the procedure is the same as that
described for a master-transmitter addressing a slave-receiver. After the repeated
START condition (Sr), a matching slave remembers that it was addressed before.

31
 This slave then checks if the first seven bits of the first byte of the slave address
following Sr are the same as they were after the
 START condition (S) and tests if the eighth (R/W) bit is 1. If there is a match, the
slave considers that it has been addressed as a transmitter and generates
acknowledge A3.
 The slave-transmitter remains addressed until it receives a STOP condition (P) or
until it receives another repeated START condition (Sr) followed by a different
slave address. After a repeated START condition (Sr), all the other slave devices
will also compare the first seven bits of the first byte of the slave address
(11110XX) with their own addresses and test the eighth (R/W) bit. However,
none of them will be addressed because R/W = 1 (for 10-bit devices), or the
11110XX slave address (for 7-bit devices) does not match).

Combined format. A master transmits data to a slave and then reads data
from the same slave. The same master occupies the bus all the time. The
transfer direction is changed after the second R/W bit.

– Combined format. A master transmits data to one slave and then

transmits data to another slave. The same master occupies the bus all the
time.

32
 Combined format. 10-bit and 7-bit addressing combined in one serial
transfer. After each START condition (S), or each repeated START condition
(Sr), a 10-bit or 7-bit slave.

 Address can be transmitted. Figure shows how a master-transmits data to a slave

with a 7-bit address and then transmits data to a second slave with a 10-bit
address. The same master occupies the bus all the time.

NOTES:
1. Combined formats can be used, for example, to control a serial memory. During the
first data byte, the internal memory location has to be written. After the START condition
and slave address is repeated, data can be transferred.
2. All decisions on auto-increment or decrement of previously accessed memory
locations etc. are taken by the designer of the device.
3. Each byte is followed by an acknowledgement bit as indicated by the A or A blocks in
the sequence.
4. I2C-bus compatible devices must reset their bus logic on receipt of a START or
repeated START condition such that they all anticipate the sending of a slave address.

33
4.3 FAST-MODE:
In the fast-mode of the I2C-bus, the protocol, format, logic levels and maximum
capacitive load for the SDA and SCL lines quoted in the previous I2C-bus specification
are unchanged.
Changes to the previous I2C-bus specification are:

 The maximum bit rate is increased to 400 kbit/s

 Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted.
There is no need for compatibility with other bus systems such as CBUS because
they cannot operate at the increased bit rate
 The inputs of fast-mode devices must incorporate spike suppression and a Schmitt
trigger at the SDA and SCL inputs
 The output buffers of fast-mode devices must incorporate slope control of the
falling edges of the SDA and SCL signals
 If the power supply to a fast-mode device is switched off, the SDA and SCL I/O
pins must be floating so that they don’t obstruct the bus lines
 The external pull-up devices connected to the bus lines must be adapted to
accommodate the shorter maximum permissible rise time for the fast-mode I2C-
bus. For bus loads up to 200pF, the pull-up device for each bus line can be a
resistor; for bus loads between 200pF and 400pF, the pull-up device can be a
current source (3mA max.) or a switched resistor circuit as shown below

34
4.4 High Speed Mode (HSM):

High-speed mode (Hs-mode) devices offer a quantum leap in I2C-bus transfer speeds.
Hs-mode devices can transfer information at bit rates of up to 3.4 Mbit/s, yet they remain
fully downward compatible with Fast- or Standard-mode (F/S-mode) devices for bi-
directional communication in a mixed-speed bus system.
Depending on the application, new devices may have a Fast or Hs-mode I2C-bus
interface, although Hs-mode devices are preferred as they can be designed-in to a greater
number of applications.

High speed transfer:

To achieve a bit transfer of up to 3.4 Mbit/s the following improvements have been made
to the regular I 2 C-bus specification:

35
  Hs-mode master devices have an open-drain output buffer for the SDAH signal
and a combination of an open-drain pull-down and current-source pull-up circuit
on the SCLH output (1) .This current-source circuit shortens the rise time of the
SCLH signal. Only the current-source of one master is enabled at any one time,
and only during Hs-mode.
 No arbitration or clock synchronization is performed during Hs-mode transfer in
multi-master systems, which speeds-up bit handling capabilities. The arbitration
procedure always finishes after a preceding master code transmission in F/S-
mode.
 Hs-mode master devices generate a serial clock signal with a HIGH to LOW ratio
of 1 to 2. This relieves the timing requirements for set-up and hold times.
 As an option, Hs-mode master devices can have a built-in bridge (1) . During Hs-
mode transfer, the high speed data (SDAH) and high-speed serial clock (SCLH)
lines of Hs-mode devices are separated by this bridge from the SDA and SCL
lines of F/S-mode devices. This reduces the capacitive load of the SDAH and
SCLH lines resulting in faster rise and fall times.
 The only difference between Hs-mode slave devices and F/S-mode slave devices
is the speed at which they operate. Hs-mode slaves have open-drain output buffers
on the SCLH and SDAH outputs. Optional pull-down transistors on the SCLH pin
can be used to stretch the LOW level of the SCLH signal, although this is only
allowed after the acknowledge bit in Hs-mode transfers.
 The inputs of Hs-mode devices incorporate spike suppression and a Schmitt
trigger at the SDAH and SCLH inputs.
 The output buffers of Hs-mode devices incorporate slope control of the falling
edges of the SDAH and SCLH signals.

The figure below shows the physical I 2 C-bus configuration in a system with only
Hs-mode devices. Pins SDA and SCL on the master devices are only used in mixed-
speed bus systems and are not connected in an Hs-mode only system. In such cases, these
pins can be used for other functions.

36
 Optional series resistors Rs protect the I/O stages of the I2C-bus devices from
high-voltage spikes on the bus lines and minimize ringing and interference. Pull-up
resistors Rp maintain the SDAH and SCLH lines at a HIGH level when the bus is free
and ensure the signals are pulled up from a LOW to a HIGH level within the required rise
time. For higher capacitive bus-line loads (>100 pF), the resistor Rp can be replaced by
external current source pull-ups to meet the rise time requirements. Unless proceeded by
an acknowledge bit, the rise time of the SCLH clock pulses in Hs-mode transfers is
shortened by the internal current-source pull-up circuit MCS of the active master.

37
 CHAPTER-5

DESIGN CALCULATION

Design Calculations for the I2C Bus:

When designing an I2C network, the number of devices on the bus, physical
characteristics of the bus wiring, and the length of the bus must be considered. These

38
variables determine the total amount of capacitive load on the bus, which the I2C
specification limits to 400pF.The value of the bus pull-up resistors are chosen based on
the bus capacitance. If the electrical characteristics of the wiring used for the I2C bus are
known, then it is easy to determine the total bus capacitance. All that is required is to
figure out the capacitance contribution of each device on the bus. If the capacitance of
each device is not known, then 10Pf per device is a good estimate.

Another way to find the total bus capacitance is to pick preliminary values for the
pull-up resistors and analyze the rise time on the bus, using a digital storage oscilloscope.
For most applications, 2000Ω would be a good starting value for the pull-up resistors.
The rise time is the time that the signal takes to go from 10% to 90% of the final value.
Then, the total bus capacitance can be determined using Equation 1.

CBUS = tR/2.2 • R………………..(1)

Next, the rise time specification for the I2C bus must be known, which is dependent on
the bus frequency. For high speed mode (400 kHz), the maximum rise time is 300nS. For
standard mode (100 kHz), the maximum rise time is 1µs. Equation 1 can be rearranged to
find the required value of the pull-up resistors as shown in Equation 2.

RPULLUP = tR/2.2 • CBUS………………….(2)

The I2C specification limits the amount of current on the bus to 3mA, which
indirectly places a limit on the value of the pull-up resistors. So for a 5V bus, the
minimum pull-up resistance that could be used is 5V/3mA, or approximately 1600Ω.
Driving Longer Distances If the bus length in the application exceeds a few feet,
selection of pull-up resistor values that satisfy the I2C specifications is a bit harder.

In this case, bus extender IC’s are available that allow you to use a longer bus in
your design. One such IC, the Philips 82B715, provides a 10x current gain. This IC
allows the total bus capacitance to increase to 4000pF and the maximum current on the
bus to 30mA. Figure 4 shows how the bus extender IC’s are connected.

39
 Fig: I2C BUS EXTENSION BLOCK DIAGRAM

It may be possible to eliminate the need for the bus extenders since PICmicro I/O pins
can sink or source greater than 3mA.

Example Design Calculations

As a design example, the characteristics of the wire that was used to test the application
firmware provided in this application note, will be used in the calculations that follow. A
24 ft. length of wire was used to connect two PIC16F873 devices with 200Ω pull-up
resistors on the SDA and SCL lines. The SCL line was observed on an oscilloscope and
the rise time was determined to be 464ns. The wiring capacitance, per foot, is calculated
in Example 1.

CWIRE = 464 ns/(2.2)(200 Ω)(24 ft)=44 pF/ft

40
 Chapter-6

I/O EXPANDERS

6.1 FEATURES:

• Operating supply voltage 2.5 to 6 V

41
 • Low standby current consumption of 10 µA maximum

• I2C-bus to parallel port expander

• Open-drain interrupts output

• 8-bit remote I/O port for the I2C-bus

• Compatible with most microcontrollers

• Latched outputs with high current drive capability for directly driving LEDs

• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with

PCF8574A)

• DIP16, or space-saving SO16 or SSOP20 packages

The I2C I/O expander as shown in this diagram allows system layout to be greatly
simplified. The two wire bus reduces PCB complexity through trace reduction and
routing simplification.

42
 Fig: System With I C I/O Expanders

Advantages:

• Easy board routing

• Board-space savings

• Processor-pin savings

• Low cost

• Industry standard

6.2 GENERAL DESCRIPTION:

The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O
expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus).

The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface.

The PCF8574 has a low current consumption and includes latched outputs with high
current drive capability for directly driving LEDs. It also possesses an interrupt line
(INT) which can be connected to the interrupt logic of the microcontroller. By sending an

43
interrupt signal on this line, the remote I/O can inform the microcontroller if there is
incoming data on its ports without having to communicate via the I2C-bus. This means
that the PCF8574 can remain a simple slave device.

6.3 Bus Expanders, Hubs, Buffers and Repeaters:

I2C bus expanders, hubs, buffers and repeaters permit bus expansion, sectional bus
isolation, address conflict resolution and voltage-level translation as shown in this
diagram.

Fig: Bus expanders, hubs, buffers and repeaters

Advantages:

• Can isolate a section on the I2C bus through enable (EN) pin.

• Permits I2C bus expansion.

• Resolves I2C address conflicts.

• Supports voltage-level translation between 2.5v, 3.3v and 5v buses, which is essential in
mixed-voltage I2C systems.

44
6.4 ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THE
BUS LINES:
I2C-bus devices with fixed input levels of 1.5 V and 3 V can each have their own
appropriate supply voltage. Pull-up resistors must be connected to a 5 V ± 10% supply.

I2C-bus devices with input levels related to VDD must have one common supply
line to which the pull-up resistor is also connected.

45
 When devices with fixed input levels are mixed with devices with input levels
related to VDD, the latter devices must be connected to one common supply line of 5V ±
10% and must have pull-up resistors connected to their SDA and SCL pins as shown in
Fig.35.

Input levels are defined in such a way that:

• The noise margin on the LOW level is 0.1VDD
• The noise margin on the HIGH level is 0.2VDD
• As shown in Fig.36, series resistors (RS) of e.g. 300 Ω can be used for protection
against high-voltage spikes on the SDA and SCL lines (resulting from the flash-
over of a TV picture tube, for example).

46
Maximum and minimum values of resistors Rp and Rs for Standard-mode I2C-bus
devices For Standard-mode I2C-bus systems, the values of resistors Rp and Rs in Fig.33
depend on the following parameters:
• Supply voltage
• Bus capacitance
• Number of connected devices (input current + leakage current).
The supply voltage limits the minimum value of resistor Rp due to the specified
minimum sink current of 3mA at VOLmax = 0.4 V for the output stages. VDD as a
function of Rp min is shown in Fig.37. The required noise margin of 0.1VDD for the
LOW level, limits the maximum value of Rs.
The bus capacitance is the total capacitance of wire, connections and pins. This
capacitance limits the maximum value of Rp due to the specified rise time. Fig.39 shows
Rp max as a function of bus capacitance.

Fig.37 . FIG.39

47
 CHAPTER-7

MEMORY TYPES

48
Memory types:

There are two types of memories

1. Volatile memory
2. Non Volatile memory

7.1 Volatile Memory:

Volatile memory, also known as volatile storage or primary storage device, is

computer memory that requires power to maintain the stored information, unlike non-
volatile memory which does not require a maintained power supply.

Most forms of modern random access memory (RAM) are volatile storage,
including dynamic random access memory (DRAM) and static random access memory
(SRAM). Content addressable memory and dual-ported RAM are usually implemented
using volatile storage. Early volatile storage technologies include delay line memory and
Williams’s tube.

The volatile memory type devices are DRAM, SRAM

1) Random-access memory (RAM):

RAM is a form of computer data storage. Today it takes the form of integrated
circuits that allow the stored data to be accessed in any order (i.e., at random). The word
random thus refers to the fact that any piece of data can be returned in a constant time,
regardless of its physical location and whether or not it is related to the previous piece of
data.

This contrasts with storage mechanisms such as tapes, magnetic discs and optical
discs, which rely on the physical movement of the recording medium or a reading head.

49
In these devices, the movement takes longer than the data transfer, and the retrieval time
varies depending on the physical location of the next item.

The word RAM is mostly associated with volatile types of memory (such as
DRAM memory modules), where the information is lost after the power is switched off.
However, many other types of memory are RAM as well (i.e., Random Access Memory),
including most types of ROM and a kind of flash memory called NOR-Flash.

To store the information we are also using a external memory devices like ROM,
EPROM, EEPROM.

2) DDR SDRAM :

DRAM is a class of memory integrated circuits used in computers. It achieves

nearly twice the bandwidth of the preceding "single data rate" SDRAM by double
pumping (transferring data on the rising and falling edges of the clock signal) without
increasing the clock frequency.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of
(memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number
of bits/byte). Thus with a bus frequency of 100 MHz, DDR SDRAM gives a maximum
transfer rate of 1600 MB/s.

DDR SDRAM operates at a voltage of 2.5v. This can significantly reduce power
consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal
voltage of 2.6 Volt.

Memory manufacturers have stated that it is impractical to mass-produce DDR1

memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1
leaves off, and is available at clock rates of 400 MHz and higher.

50
7.2 Non-Volatile memory;

Non-Volatile is a type of memory used in computers and other electronic devices

to store small amounts of data that must be saved when power is removed, e.g.,
calibration tables or device configuration.

Non-volatile memories are PROM, EPROM, EEPROM, and Flash Memories.

PROM: Program Read Only Memory is abbreviated as PROM. This is a type of Memory
.This will be use only one time .

EPROM: This is a type of memory .In the EPROM to erase the programme we are using
UV-Radiation. This cost is high.

To erase the programme we require 15-20 min. So to avoid this we are using a
EEPROM.

7.3 FLASH MEMORY:

Flash memory (sometimes called "flash RAM") is a type of constantly-powered

nonvolatile memory that can be erased and reprogrammed in units of memory called
blocks. It is a variation of electrically erasable programmable read-only memory
(EEPROM) which, unlike flash memory, is erased and rewritten at the byte level, which
is slower than flash memory updating. Flash memory is often used to hold control code
such as the basic input/output system (BIOS) in a personal computer. When BIOS needs
to be changed (rewritten), the flash memory can be written to in block (rather than byte)
sizes, making it easy to update. On the other hand, flash memory is not useful as random
access memory (RAM) because RAM needs to be addressable at the byte (not the block)
level.

51
7.4 EEPROM:

i) Features:

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 3.6V)

• Internally Organized 65,536 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

• Automotive Devices Available

• Die Sales: Wafer Form, Waffle Pack and Bumped Die.

52
 ii) PIN DIAGRAM:

The AT24C512 provides 524,288 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each.
The device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Fig: Pin diagram

53
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
Open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that
are hardwired or left not connected for hardware compatibility with other AT24Cxx
devices.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing
section. If the pins are left floating, the A1 and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows
normal write operations. When WP is connected high to VCC, all write operations to the
memory is inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a
write operation creates a software write protect function.

Memory Organization:
AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512
pages of 128-bytes each. Random word addressing requires a 16-bit data word address.

54
 iii) Device Operation :
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an
external device. Data on the SDA pin may change only during SCL low time periods.
Data changes during SCL high periods will indicate a start or stop condition as defined
below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start

condition which must precede any other command.

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop

condition. After a read sequence, the stop command will place the EEPROM in a standby
power mode.
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to

55
acknowledge that it has received each word.
STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled:
a) Upon power-up and
b) After the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two wire part can be reset by following these steps:
(a) Clock up to 9 cycles,
(b) Look for SDA high in each cycle while SCL is high and then
(c) Create a start condition as SDA is high.

iv) Device Addressing:

The 512K EEPROM requires an 8-bit device address word following a start
condition to enable the chip for a read or write operation .The device address word
consists of a mandatory “1”, “0” sequence for the first five most significant bits as
shown. This is common to all two-wire EEPROM devices.

Fig: Device Address

The 512K uses the two device address bits A1, A0 to allow as many as four
devices on the same bus. These bits must compare to their corresponding hardwired input
pins. The A1 and A0 pins use an internal proprietary circuit that biases them to a logic
low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read
operation is initiated if this bit is high and a write operation is initiated if this bit is low.

56
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
v) DATA SECURITY:
The AT24C512 has a hardware data protection scheme that allows the user to
Write Protect the whole memory when the WP pin is at VCC. Write Operations

BYTE WRITE:
A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a “0” and then clock in the first 8-bit data word. Following receipt of
the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (Figure 8 ).

Fig: Byte Write

PAGE WRITE:
The 512K EEPROM is capable of 128-byte page writes. A page write is initiated
the same way as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the
first data word, the microcontroller can transmit up to 127 more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller
must terminate the page write sequence with a stop condition.

57
 The data word address lower 7 bits are internally incremented following the receipt
of each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from
the last byte of the current page to the first byte of the same page.

ACKNOWLEDGE POLLING:
Once the internally-timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition
followed by the device address word. The Read/Write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a “0”, allowing the read or write sequence to continue.

vi) Read Operations:

Read operations are initiated the same way as write operations with the exception
that the Read/Write select bit in the device address word is set to “1”.
There are three read operations: Current address read,
Random address read
Sequential read.

CURRENT ADDRESS READ:

The internal data word address counter maintains the last address accessed during
the last read or write operation, incremented by “1”. This address stays valid between
operations as long as the chip power is maintained. The address roll over during read is
from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.

58
The microcontroller does not respond with an input “0” but does generate a following
stop condition.

RANDOM READ:
A random read requires a “dummy” byte write sequence to load in the data word
address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with
a “0” but does generate a following stop condition (see Figure 11 on page 11).

59
Chapter-8
RTC

60
RTC:

The DS1307 serial real-time clock (RTC) is a low-power, full binary-coded

decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are
transferred serially through an I2C, bidirectional bus. The clock/calendar provides
seconds, minutes, hours, day, date, month, and year information. The end of the month
date is automatically adjusted for months with fewer than 31 days, including corrections
for leap year. The clock operates in either the 24 hour or 12-hour format with AM/PM
indicator. The DS1307 has a built-in power-sense circuit that detects power failures and
automatically switches to the battery supply.

8.1 FEATURES:

 Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month,
Month, Day of the week, and Year with Leap-Year Compensation Valid Up to
2100
 56-Byte, Battery-Backed, Nonvolatile (NV) RAM for Data Storage
 I2C Serial Interface
 Programmable Square-Wave Output Signal
 Automatic Power-Fail Detect and Switch Circuitry
 Consumes Less than 500nA in Battery Backup Mode with Oscillator Running
 Optional Industrial Temperature Range: -40°C to +85°C
 Available in 8-Pin DIP or SO
 Underwriters Laboratory (UL) Recognized

61
 Fig: pin diagram

ABSOLUTE MAXIMUM RATINGS:

Voltage range on any pin relative to ground…………………………..-0.5V to +7.0V

Operating Temperature Range (non condensing)…………0°C to +70°C (Commercial),

-40°C to +85°C (Industrial)

Storage temperature range…………………………………..-55°C to +125°C.

Soldering temperature……………………………………. +260°C for 10 seconds.

62
8.2 Pin description:

X1 X2: Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load capacitance (CL)
of 12.5pF.
X1 is the input to the oscillator and can optionally be connected to an external 32.768
kHz oscillator. The output of the internal oscillator, X2 is floated if an external oscillator
is connected to X1.
Note: For more information on crystal selection and crystal layout considerations,
refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

VBAT:
Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source.
Battery voltage must be held between the minimum and maximum limits for proper
operation. Diodes in series between the battery and the VBAT pin may prevent proper
operation. If a backup supply is not required, VBAT may be grounded. The nominal
power-fail trip point (VPF) voltage at which access to the RTC and user RAM is denied
is set by the internal circuitry as 1.25 x VBAT nominal. A lithium battery with 48mAhr
or greater will back up the DS1307 for more than 10 years in the absence of power at
+25°C. UL recognized to ensure against reverse charging current when used with a
lithium battery.

GND: Ground

SDA: Serial Data Input/Output. SDA is the data input/output for the I2C serial interface.
The SDA pin is open drain and requires an external pull-up resistor.
SCL: Serial Clock Input. SCL is the clock input for the I2C interface and is used to
synchronize data movement on the serial interface.
SWQ/OUT: Square Wave/Output Driver. When enabled, the SQWE bit set to 1, the
SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz).

63
The SQW/OUT pin is open drain and requires an external pull-up resistor. SQW/OUT
operates with either VCC or VBAT applied.

VCC: Primary Power Supply. When voltage is applied within normal limits, the device is
fully accessible and data can be written and read. When a backup supply is connected to
the device and VCC is below VTP, read and writes are inhibited. However, the
timekeeping function continues unaffected by the lower input voltage.

8.3 Block diagram:

64
Oscillator:

The DS1307 uses an external 32.768 kHz crystal. The oscillator circuit does not
require any external resistors or capacitors to operate. Table 1 specifies several crystal
parameters for the external crystal. Figure 3 shows a functional schematic of the
oscillator circuit. If using a crystal with the specified characteristics, the startup time is
usually less than one second.

Fig: oscillator ckt showing internal biasing network

CLOCK ACCURACY:
The accuracy of the clock is dependent upon the accuracy of the crystal and the
accuracy of the match between the capacitive load of the oscillator circuit and the
capacitive load for which the crystal was trimmed. Additional error will be added by
crystal frequency drift caused by temperature shifts. External circuit noise coupled into
the oscillator circuit may result in the clock running fast.

65
RTC AND RAM ADDRESS MAP:
The RTC registers are located in address locations 00h to 07h. The RAM registers are
located in address locations 08h to 3Fh. During a multibyte access, when the address
pointer reaches 3Fh, the end of RAM space, it wraps around to location 00h, the
beginning of the clock space.

CLOCK AND CALENDAR:

The time and calendar information is obtained by reading the appropriate register
bytes. Table 2 shows the RTC registers. The time and calendar are set or initialized by
writing the appropriate register bytes.
The contents of the time and calendar registers are in the BCD format. The day-of-
week registers increments at midnight. Values that correspond to the day of week are
user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and
so on.) Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is
the clock halt (CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared
to 0, the oscillator is enabled.
Please note that the initial power-on state of all registers is not defined. Therefore,
it is important to enable the oscillator (CH bit = 0) during initial configuration.
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM.
In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). The hours value
must be re-entered whenever the 12/24-hour mode bit is changed.

66
 Fig: Timekeeper Registers
The DS1307 control register is used to control the operation of the SQW/OUT pin.

Bit 7: Output Control (OUT). This bit controls the output level of the SQW/OUT pin
when the square wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT
pin is 1 if OUT = 1 and is 0 if OUT = 0.

Bit 4: Square-Wave Enable (SQWE). This bit, when set to logic 1, enables the oscillator
output. The frequency of the square-wave output depends upon the value of the RS0 and
RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling
edge of the square wave.

Bits 1, 0: Rate Select (RS1, RS0). These bits control the frequency of the square-wave
output when the square-wave output has been enabled. The following table lists the
square-wave frequencies that can be selected with the RS bits.
.

67
 CHAPTER-9
SOFTWARE IMPLEMENTATION

68
9.1 KEIL SOFTWARE:
Keil development tools for the 8051 Microcontroller Architecture support every
level of software developer from the professional applications engineer to the student just
learning about embedded software development.
The industry-standard Keil C Compilers, Macro Assemblers, Debuggers, Real-time
Kernels, Single-board Computers, and Emulators support all 8051 derivatives and help
you get your projects completed on schedule.
 When starting a new project, simply select the microcontroller you use from the
Device Database and the µVision IDE sets all compiler, assembler, linker, and
memory options for you.
 Numerous example programs are included to help you get started with the most
popular embedded 8051 devices.
 The Keil µVision Debugger accurately simulates on-chip peripherals (I²C, CAN,
UART, SPI, Interrupts, I/O Ports, A/D Converter, D/A Converter, and PWM
Modules) of your 8051 device. Simulation helps you understand hardware
configurations and avoids time wasted on setup problems. Additionally, with
simulation, you can write and test applications before target hardware is available.

69
 The Keil Cx51 ANSI C Compiler supports all classic and extended 8051 device
variants. Compiler extensions provide full access to all CPU resources and support up to
16MB memory. Keil Cx51 generates code with the efficiency and speed of hand-
optimized assembly. New compiler and linker optimizations shrink programs into the
smallest single-chip devices.
The Keil µVision® IDE fully integrates Cx51 Version 8 and provides control of
the Compiler, Assembler, Real-Time OS, Project Manager, and Debugger in a single,
intelligent environment. With support for all 8051 devices and full compatibility with
emulators and third party tools, Keil Cx51 is clearly the best choice for your 8051
project.

Cx51 Compiler Highlights:

1. Support for all 8051 derivatives and variants

2. Fast 32-bit IEEE floating-point math
3. Efficient interrupt code and direct register bank control
4. Bit-addressable objects
5. Sophisticated syntax checking and detailed warnings
6. Use of AJMP and ACALL instructions
7. Memory banking for code and variables beyond 64KB
8. Register parameters and dynamic register variables
9. Global program wide register optimization
10. Common code block subroutine optimization
11. Use of multiple data pointers
12. Use of on-chip arithmetic units
13. Generic and memory-specific pointers
14. Reentrant functions and register bank independent code
15. Extensive debug and source browse information
9.2 WAIT FOR READ OPERATION:

70
Example:
This example shows a write of data values 0x05 and 0xE0 to address 0x00 and
0x01 of M24C08 Block3 respectively.

9.3 Wait for Write Operation:

71
 Before starting any new operation with the EEPROM, we wait until the write
operation is finished. The EEPROM will send the ACK bit if busy with the write
operation, so the processor has to send the EEPROM address continuously until the
EEPROM sends the ACK bit.
To initiate the communication, the STR71x I2C has to generate a START
condition and then send the M24C08 Address (with R/W bit cleared). After checking the
correct status of the previous transmission, the Master writes, in the Data Register (DR),
the address of the first byte. We want to read from the M24C08. The previous byte
transmission check is done by looping on the BTF flag in the Status Register 1 (SR1).
Then the STR71x I2C has to regenerate the START condition and then write the
slave address in the Data Register (DR). This address must be the same as the address
sent after the first START condition except that the least significant bit (R/W) must be
set. Then a previous byte transmission check is done by looping on the ENDAD flag in
Status Register 2 (SR2).
After this, the STR71x I2C becomes a receiver for all bytes sent from the M24C08.
To receive a new data byte, the previous byte reception has to be completed correctly.
The byte reception check is done by looping on the BTF flag in Status Register 1 (SR1).
This flag is cleared by reading the Data Register (DR).
To close the communication, before reading the last byte from the DR register, set
the STOP bit to generate the Stop condition. The interface goes automatically back to
slave mode (M/SL bit cleared). In order to generate the non-acknowledge pulse after the
last received data byte, the ACK bit must be cleared just before reading the second last
data byte.

72
73
EEPROM Programme:

#include<reg51.h>
#include<stdio.h>
#include<intrins.h>
#include<absacc.h>

call();
rec();
void convert(unsigned char);
void Initserial(void);
void start(void); Begin
void display(unsigned char[]);
void stop(void); Generate START Condition
void WriteI2c(unsigned char Data);
Send Slave Address((R/W)bit=0)
unsigned char ReadI2c(bit ACK_Bit);
void DelayMs(unsigned int count);
Send the EEPROM’s
unsigned char ReadBYTE(unsigned int Addr); address to read from
void WriteBYTE(unsigned int Addr, unsigned char Data);
Re-Generate START
void space();
void next();
void enter(); Send Slave Address((R/W)bit=1)

void convert(unsigned char);

void comp(unsigned char); Wait until the byte is received
void send(unsigned char);
NO
2nd last byte
#define ACK 1 to receive
#define NO_ACK 0

Disable ACK
unsigned char i;

NO
Last byte
to receive
74

Enable STOP condition generation

 Receive next byte

NO
sbit SDA=P0^2; End of
reception
sbit SCL=P0^3;

void main(void) End

{
unsigned char val[]="enter the values:/";
unsigned char res[]="Address 0x00:/";
unsigned char x,y,z,loc,Data;
unsigned char EData;
Initserial();

while(val[x]!='/')
{
SBUF=val[x];
while(TI==0);
TI=0;
x++;
}

for(x=0;x<5;x++)
{
z=call();
DBYTE[0x20+y]=z;
y++;
space();
}

next();
enter();
y=0;
loc+=0x0000;

75
for(x=0;x<5;x++)
{
loc+=0x0000;
Data=DBYTE[0x20+y];
WriteBYTE(loc,Data);
DelayMs(10);
loc++;
y++;
}

y=0;
x=0;
while(res[x]!='/')
{
SBUF=res[x];
while(TI==0);
TI=0;
x++;
}
//TI=1;
//printf("ADDRESS 0x00:\t");
//TI=0;
for(x=0;x<5;x++)
{
EData=ReadBYTE(0x0000+y);
//TI=1 ;
DelayMs(10);
convert(EData);
space();

//printf("%02bX\t",EData);

76
y++;
//TI=0;
}
next();
enter();
while(1);
}

/*start I2c*/

void start(void)
{
SDA=1;
SCL=1;
if(SDA==1)
{
if(SCL==1)
{
_nop_();
SDA=0;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
SCL=0;
CY=0;
}
}
else
CY=1;

77
}

/*stop I2c*/

void stop(void)
{

SDA=0;
_nop_();
_nop_();
SCL=1;
_nop_();
_nop_();
_nop_();
_nop_();
SDA=1;
}

/* write I2C */

void WriteI2c(unsigned char Data)

{
for(i=0;i<8;i++)
{
SDA=(Data&0x80)? 1:0;
SCL=1;
SCL=0;
Data<<=1;
}
SCL=1;
_nop_();

78
 _nop_();
SCL=0;
}

/*Read I2c */

unsigned char ReadI2c(bit ACK_Bit)

{
unsigned char Data=0;
SDA=1;
for(i=0;i<8;i++)
{

SCL=1;
Data<<=1;
Data=(Data|SDA);
SCL=0;
_nop_();
}
if(ACK_Bit==1)
SDA=0;
else
SDA=1;
_nop_(); _nop_();
SCL=1;
_nop_(); _nop_();
_nop_(); _nop_();
SCL=0;
return Data;
}

79
/*read 1 byte data from I2c*/
unsigned char ReadBYTE(unsigned int Addr)
{
unsigned char Data;
start();
WriteI2c(0xA0);
WriteI2c((unsigned char)(Addr>>8)&0xFF);
WriteI2c((unsigned char)Addr&0xFF);
start();
WriteI2c(0xA1);
Data=ReadI2c(NO_ACK);
stop();
return(Data);
}

/*write 1byte to I@c*/

void WriteBYTE(unsigned int Addr,unsigned char Data)
{
start();
WriteI2c(0XA0);
WriteI2c((unsigned char) (Addr>>8)&0XFF);
WriteI2c((unsigned char) Addr & 0XFF);
WriteI2c(Data);
stop();
}

/*data function*/
void DelayMs(unsigned int count)
{

80
unsigned int i;
while(count)
{
i=115;
while(i>0)
i--;
count--;
}
}

/*initialize serial port */

void Initserial(void)
{
SCON=0X50;
TMOD=0X20;
TH1=0XFD;
TR1=1;
}
/*call*/
call()
{
unsigned char y,z,a;
rec();
y=SBUF;
rec();
z=SBUF;
y=y^0X30;
y=y<<4;
z=z^0X30;

81
 a=y|z;
return(a);
}

rec()
{
unsigned char a;
while(RI==0);
a=SBUF;
SBUF=a;
while(TI==0);
TI=0;
RI=0;
}
void space()
{
SBUF=0X20;
while(TI==0);
TI=0;
}
void next()
{
SBUF=0X0A;
while(TI==0);
TI=0;
}
void enter()
{
SBUF=0X0D;
while(TI==0);
TI=0;

82
 }
void convert(unsigned char x)
{
unsigned char y;
y=x;
x=x&0xf0;
x=x>>4;
comp(x);
x=y;
x=x&0x0f;
comp(x);
}
void comp(unsigned char x)
{
if(x<=9)
{
x=x|0x30;
send(x);
}
else
{
x=x+0x37;
send(x);
}
}
void send(unsigned char y)
{
SBUF=y;
while(TI==0);
TI=0;}

83
RTC Programme:

/**/#include<reg51.h>
#include<stdio.h>
#include<intrins.h>
#include<absacc.h>

void DelayMs(unsigned int count);

void InitSerial(void);
void ReadRTC(unsigned char * buff);
void WriteRTC(unsigned char * buff);
char * Int2Day(unsigned char day);
char * Int2Month(unsigned char month);

#define ACK 1
#define NO_ACK 0

unsigned char i;

const unsigned char * DayStr[7] = {{"Sun"},

{"Mon"},
{"Tue"},
{"Wen"},
{"Thu"},
{"Fri"},
{"Sat"}};

84
const unsigned char * MonthStr[12] ={{"Jan"},
{"Feb"},
{"Mar"},
{"Apr"},
{"May"},
{"Jun"},
{"Jul"},
{"Aug"},
{"Sep"},
{"Oct"},
{"Nov"},
{"Dec"}};

sbit SDA = P0^1; // connect to SDA pin (Data)

sbit SCL = P0^0; // connect to SCL pin (Clock)

unsigned char RTC_ARR[7]; // Buffer for second, minute,.....,year

void main()
{
InitSerial();

ReadRTC(&RTC_ARR[0]);
RTC_ARR[0] = RTC_ARR[0] & 0x7F; // enable oscillator (bit 7=0)

85
 WriteRTC(&RTC_ARR[0]); // Set RTC
while(1)
{

ReadRTC(&RTC_ARR[0]);
TI=1;
put char(0x0C); // clear Hyper terminal
DelayMs(100);
printf("Day : %s\r\n",Int2Day(RTC_ARR[3]));
printf("Time%02bX:%02bX:%02bX\r\n",RTC_ARR[2],RTC_ARR[1],RTC_ARR[0]);
printf("Data : %02bX-%02bX-%02bX\r\n",RTC_ARR[4],RTC_ARR[5],RTC_ARR[6]);
printf("month: %s\r\n",Int2Month(RTC_ARR[5]));
DelayMs(1000);
TI=0;
}
}

unsigned char BCD2HEX(unsigned int bcd)

{
unsigned char temp;
temp=((bcd>>8)*100)|((bcd>>4)*10)|(bcd&0x0f);
return temp;

void Start(void)
{
SDA = 1;
SCL = 1;
_nop_();_nop_();
SDA = 0;

86
 _nop_();_nop_();
SCL = 0;
_nop_();_nop_();
}

void Stop(void)
{
SDA = 0;
_nop_();_nop_();
SCL = 1;
_nop_();_nop_();
SDA = 1;
}

void WriteI2C(unsigned char Data)

{

for (i=0;i<8;i++)
{
SDA = (Data & 0x80) ? 1:0;
SCL=1;SCL=0;
Data<<=1;
}

SCL = 1;
_nop_();_nop_();
SCL = 0;

87
unsigned char ReadI2C(bit ACK_Bit)
{

unsigned char Data=0;

SDA = 1;
for (i=0;i<8;i++)
{
SCL = 1;
Data<<= 1;
Data = (Data | SDA);
SCL = 0;
_nop_();
}

if (ACK_Bit == 1)
SDA = 0; // Send ACK
else
SDA = 1; // Send NO ACK

_nop_();_nop_();
SCL = 1;
_nop_();_nop_();
SCL = 0;

return Data;
}

void ReadRTC(unsigned char * buff)

88
{

Start();
WriteI2C(0xD0);
WriteI2C(0x00);

Start();
WriteI2C(0xD1);
*(buff+0)=ReadI2C(ACK); // Second
*(buff+1)=ReadI2C(ACK); // Minute
*(buff+2)=ReadI2C(ACK); // hour
*(buff+3)=ReadI2C(ACK); // Day
*(buff+4)=ReadI2C(ACK); // date
*(buff+5)=ReadI2C(ACK); // month
*(buff+6)=ReadI2C(NO_ACK); // year
Stop();
}

void WriteRTC(unsigned char *buff)

{

Start();
WriteI2C(0xD0);
WriteI2C(0x00);
WriteI2C(*(buff+0));
WriteI2C(*(buff+1));
WriteI2C(*(buff+2));
WriteI2C(*(buff+3));
WriteI2C(*(buff+4));

89
 WriteI2C(*(buff+5));
WriteI2C(*(buff+6));
Stop();
}

char * Int2Day(unsigned char day)

{
return DayStr[day-1];
}

char * Int2Month(unsigned char month)

{
return MonthStr[BCD2HEX(month)-1];
}
void DelayMs(unsigned int count)
{
unsigned int i;
while(count)
{
i = 115;
while(i>0) i--;
count--;
}
}
void InitSerial(void)
{
SCON = 0x50; // setup serial port control
TMOD = 0x20; // hardware (9600 BAUD @11.05592MHZ)
TH1 = 0xFD; // TH1
TR1 = 1; // Timer 1 on

90
}

Conclusion:

A framework has been presented that incorporates the uses of sensors in

developing a low-cost, high-accuracy weather monitoring system, using analogue and
digital components. The proposed system has been tested through extensive experiments
and the results have proven the accuracy and reliability of the proposed system. Besides,
a comparison on the features of different types of monitoring systems has been carried
out and it shows that the proposed system is of better choice in terms of cost, portability,
memory capacity and logging interval-setting capability.

91
REFERENCES
Bu, J. U., T. Y. Kim, Y. S. Jun, Y. C. Shim, and S. T. Kim. 1995. Silicon-
based thermal comfort sensing device. p.104–107. In Proceedings of Transducers 95
(2). Eurosensors IX,Stockholm, Sweden.
Buff, W., F. Plath, O. Schmeckebier, M. Rusko, T. Vandahl, H. Luck, and F.
Muller. 1994.
Remote sensor system using passive SAW sensors. p.585-588. In Proceedings of
IEEE Ultrasonics Symposium. Cannes. November 1994.

92