Multiplexers, Transmission Gates & Dynamic Logic

COMP20212 Digital Design Techniques School of Computer Science
Lecture 4:
Multiplexers, Transmission Gates &
Dynamic Logic
Aims
The aim of this lecture is to investigate larger scale implementation
of digital logic, we will be looking at:
• the operation of the multiplexer

• the transmission gate multiplexer
• synthesis of logic functions using multiplexers
• multiplexer trees
• dynamic logic
COMP20212: Lecture 4 1
Syllabus
Introduction [1] - PWN
CMOS circuit design [3] – EWH/PWN
Layout [2] – EWH
CMOS fabrication [2] – EWH
Scaling [2] – EWH
Power, speed and space compromises [2] – EWH
Circuit simulation [1] – EWH
Sequential system design using ASM charts [4] – PWN
Implementation choices & digital design with
programmable logic devices [2] – PWN
System design for arithmetic operations [3] – PWN
1
CMOS Logic Synthesis

In the last two lectures you have looked at …
• implementing logic functions using CMOS transistors

• complex gate implementations
We can also synthesise CMOS designs using …
• multiplexers (as Universal Logic Modules – ULMs)

• dynamic logic
• programmable logic (later lectures)
What You Need to Know …
You need to recall a few things from the first year …
• Standard logic design (i.e. AND, OR gates)
• Logic optimisation techniques
• DeMorgans theorem
• Karnaugh Maps
• etc etc
2
The Multiplexer (MUX)
A multiplexer is a digital logic

device that has 2n data input lines
and a single output, the logic
input to n inputs select one of 2n
data inputs to be connected to the
output.
Thus, the MUX is a switching circuit or data selector, i.e. it can

be used to select data to be processed or stored.
2:1 MUX
Symbol: Circuit:
Functional form: f = s0 d0 + s0 d1
3
4:1 MUX
Symbol: Circuit:
Functional form: f = s0 s1d0 + s0 s1d1 + s0 s1d2 + s0 s1d 3
2n:1 MUX
If we have n select inputs …
2 n !1
f = "m d k k
k=0
where mk is a minterm of the n select inputs and

dk is the corresponding data input
What can we use the MUX for? (apart from a data selector/switch)
4
The Transmission Gate

s
A logic controlled switch
can be constructed using
a complementary input output
arrangement of pmos and
nmos transistors:
s
s switch
0 transistors off, high impedance ‘off’
1 transistors on, low impedance ‘on’
The Transmission Gate MUX

Due to their short delays and simplicity transmission gates are
often used to implement devices such as MUXs and flip-flops.
2:1 MUX
Inverter
5
0 0 0
The Transmission 0 0 1
Gate MUX
0 1 0
8:1 MUX 1 1
0
1 0 0
1 0 1
1 1 0
1 1 1
Can you see any problems
implementing larger MUXs?
The MUX and Combinatorial Logic

In addition, a MUX may be used to synthesise combinatorial logic by applying
data signals to both the inputs of the MUX and the control lines ...
… output can be any function of a number of input variables,

hence, they can be thought of as a form of universal logic module (ULM).
The implementation of combinatorial logic using MUXs is attractive because:
• useful in hardware prototyping – reconfigurable

• design has direct correspondence with the ASM chart
in sequential designs
• are available in standard cell libraries for implementation
in semi-custom designs
6
Combinatorial Logic using the MUX

A 2n:1 MUX can implement any function of n variables
(variables as select only) ...
… for example, a 4:1 MUX can implement a function of 2 variables:
A B f
0 0 0
0 1 1
1 0 0
1 1 1 Multiplexer
Logic
Combinatorial Logic using the MUX
We are not only restricted to applying variables to the MUX

select lines, but also as data inputs to the MUX.
Example
f ( A,B,C ) = AC+A
Process
• expand so each minterm includes select inputs
• choose variables to control select lines, and variable to be
connected to the data lines
7
Select and Data Assignment

Extract from the Karnaugh map, i.e.
if x1 is the select and x2 forms the inputs
2:1 MUX
x1x2
00 01 11 10
- - - -
d0 d1
if x2 is the select and x1 forms the inputs
x1x2
00 01 11 10
- - - -
Can implement a function of
2 variables – f(x2,x1) d0 d1
4:1 MUX if x1 and x2 are the select and x3 forms the inputs
x1x2
x3 00 01 11 10
0 - - - -
1 - - - -
d0 d1 d3 d2
x1x2
00 01 11 10
f(x3) f(x3) f(x3) f(x3)
Can implement a function of
three variables – f(x3,x2,x1)
8
It is possible to synthesise more than a function of k+1 variables using a 2k:1

MUX by gating the inputs to the multiplexer.
For example, use a 4:1 MUX to implement the function of four variables:
i.e. select – x1x2, data – x3x4 Example:
x1 x2 x1 x2
x3 x4 00 01 11 10 x3 x4 00 01 11 10
00 - - - - 00 0 1 0 0
01 - - - - 01 0 0 0 0
11 - - - - 11 1 0 0 1
10 - - - - 10 0 0 0 1
d0 d1 d3 d2
Example: 2-bit Comparator
N1(A1B1) E
2-bit
comp L
N2(A2B2)
H
E=1 when N1=N2, E=0 otherwise

L=1 when N1<N2, L=0 otherwise
H=1 when N1>N2, H=0 otherwise
9
Example: 2-bit Comparator

N1 N2
A1 B1 A2 B2 E L H
E=1 0 0 0 0 1 0 0
0 0 0 1 0 1 0
L=1 0 0 1 0 0 1 0
0 0 1 1 0 1 0
H=1 0 1 0 0 0 0 1
0 1 0 1 1 0 0
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
No don’t cares 1 1 1 0 0 0 1
1 1 1 1 1 0 0
Example: NAND Gate Implementation

Warning:
as designs get more complex
then so do simple gate designs
Problems:
Irregular
Complex - simplification?
Multilevel gating required?
Glitches, timing errors?
10
Example: 8:1 MUX Implementation
Multiplexer Trees
You can implement larger MUX (ULM) circuits by cascading smaller MUXs.
i.e. consider the 8:1 MUX
2:1 2:1
2:1
4:1
2:1 2:1
2:1 4:1 2:1 8:1
2:1 2:1
4:1
2:1
2:1 2:1
11
Dynamic Logic
A dynamic CMOS gate

consists of an nmos
transistor logic structure
whose output is pre-charged
to VDD by a pmos transistor
and conditionally discharged
by an nMOS transistor
Dynamic Logic
1
CLK 0
precharge evaluate
• When CLK=0, the output, Z, is charged to VDD by the switch

on of the pmos transistor, the route to VSS is closed by nmos
transistor
• When CLK=1, the function implemented by the nmos logic
block is evaluated to determine whether the output is pulled
down to VSS or held at VDD (depending upon capacitive
loading)
12
Dynamic Logic Example
NOR gate:
Precharge:
• Z = VDD, i.e. ‘1’
Evaluate:
• If X=Y=0, a and b will be off and Z
remains at ‘1’
• If X=0,Y=1, then a will be on and Z
will be pulled down to VSS, i.e. ‘0’
• If X=1, Y=0, then b will be on and Z
will be pulled down to VSS, i.e. ‘0’
• If X=Y=1, then both a and b will be
on and Z will be pulled down to VSS,
i.e. ‘0’
Dynamic Logic
Advantages
• reduced number of transistors, hence areal size
Disadvantages
• slower due to the two stage process

• data at the output is generally not valid until the falling
edge of the clock
• any capacitive loading on the output will pull the signal
low
13
Summary
We have discussed
• the operation of the multiplexer

• the transmission gate implementation of the multiplexer
• that the multiplexer can also be used to synthesise logic functions
• that the multiplexer can be used as a general reconfigurable universal
logic module
• the process of control and data assignments using the Karnaugh map
• implementing finite state machines using multiplexers
• the number of MUXs in the next state function equals the number
of state variables
• the number of MUXs in the output logic equals the number of outputs
• the width of each MUX is equal to the number of states
• the use of dynamic logic
References
• Roth, Fundamentals of Logic Design, 4th Edition, PWS,

ISBN 053495472-3
• Green, Modern Logic Design, Addison Wesley,

ISBN 0-201-14541-
• Wakerley, ‘Digital Design, Principles & Practices,

ISBN 0-13-089896-1
14

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COMP20212 Digital Design Techniques School of Computer Science

• the operation of the multiplexer

COMP20212 Digital Design Techniques School of Computer Science

CMOS Logic Synthesis

• implementing logic functions using CMOS transistors

We can also synthesise CMOS designs using …

• multiplexers (as Universal Logic Modules – ULMs)

COMP20212 Digital Design Techniques School of Computer Science

What You Need to Know …

You need to recall a few things from the first year …

• Standard logic design (i.e. AND, OR gates)

• Logic optimisation techniques

The Multiplexer (MUX)

A multiplexer is a digital logic

Thus, the MUX is a switching circuit or data selector, i.e. it can

COMP20212 Digital Design Techniques School of Computer Science

Functional form: f = s0 s1d0 + s0 s1d1 + s0 s1d2 + s0 s1d 3

COMP20212 Digital Design Techniques School of Computer Science

If we have n select inputs …

where mk is a minterm of the n select inputs and

The Transmission Gate

COMP20212 Digital Design Techniques School of Computer Science

The Transmission Gate MUX

COMP20212 Digital Design Techniques School of Computer Science

The MUX and Combinatorial Logic

… output can be any function of a number of input variables,

The implementation of combinatorial logic using MUXs is attractive because:

• useful in hardware prototyping – reconfigurable

Combinatorial Logic using the MUX

COMP20212 Digital Design Techniques School of Computer Science

Combinatorial Logic using the MUX

We are not only restricted to applying variables to the MUX

Select and Data Assignment

if x2 is the select and x1 forms the inputs

COMP20212 Digital Design Techniques School of Computer Science

Select and Data Assignment

Select and Data Assignment

It is possible to synthesise more than a function of k+1 variables using a 2k:1

COMP20212 Digital Design Techniques School of Computer Science

Example: 2-bit Comparator

E=1 when N1=N2, E=0 otherwise

Example: 2-bit Comparator

COMP20212 Digital Design Techniques School of Computer Science

Example: NAND Gate Implementation

Example: 8:1 MUX Implementation

COMP20212 Digital Design Techniques School of Computer Science

2:1 4:1 2:1 8:1

A dynamic CMOS gate

COMP20212 Digital Design Techniques School of Computer Science

• When CLK=0, the output, Z, is charged to VDD by the switch

Dynamic Logic Example

COMP20212 Digital Design Techniques School of Computer Science

• reduced number of transistors, hence areal size

• slower due to the two stage process

• the operation of the multiplexer

COMP20212 Digital Design Techniques School of Computer Science

• Roth, Fundamentals of Logic Design, 4th Edition, PWS,

• Green, Modern Logic Design, Addison Wesley,

• Wakerley, ‘Digital Design, Principles & Practices,

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