ACKNOWLEDGEMENT

The magnitude of this seminar demanded the co-operation, guidance and

assistance from a number of people and I have been fortunate to have this, and I take this
opportunity to thank all those who have helped me in this seminar.
I express a deep sense of gratitude to Prof. Saleem Hebbal and Prof. Damodar
Hotkar for their constant timely advice, valuable suggestions and help given from time to
time.
I also express a deep sense of gratitude to Prof. Poornima Raikar for her
valuable suggestions and help given.
I take this opportunity to thank Prof. A.V. Kolaki HOD of Computer Science
and Engineering Dept, VDRIT Haliyal providing the inspiration for taking this seminar.
I will be failing in my duty if I don’t thank our principal Dr. G.R. Udupi for
providing healthy environment in the college that helped in concentrating on the task.
Then I would also thank all teaching and non teaching staff of the department who
directly or indirectly contributed in accomplishing this task.
Last but not the least I express my sincere thanks to all persons who have directly
or indirectly assisted my endeavour.

Sayyan N Shaikh

I
 CONTENTS

List of Figures III

Abstract IV

CHAPTER 1
INTRODUCTION 01

CHAPTER 2
INSTRUCTION SETS 03
2.1 SSE4.1 and SSE4.2 03
2.2 AVX (Advanced Vector Extensions) 03
2.3 AES (Advanced Encryption Standard) 04
2.4 LWP (Light Weight Profiling) 04

CHAPTER 3
THE CPU BUILDING BLOCKS 05

CHAPTER 4
THE FETCH AND DECODE UNITS 07

CHAPTER 5
THE EXECUTION UNITS 09

CHAPTER 6
THE MEMORY UNITS 12

CHAPTER 7
POWER MANAGEMENT 14

CONCLUSION 15

REFERENCES 16

II
 LIST OF FIGURES

FIGURE NO. DESCRIPTION PAGE NO.

3.1 Bulldozer building block 5

Eight-core CPU based on the

3.2 Bulldozer architecture 6

4.1 The Fetch and Decode units 7

5.1 The Execution units 9

5.2 The floating point unit 10

6.1 The L2 memory cache 13

7.1 Power management 14

III
 ABSTRACT

Bulldozer is the codename AMD has given to one of the next-generation CPU cores
after the K10 microarchitecture for the company's M-SPACE design methodology, with the
core specifically aimed at 10 watt to 125 watt TDP computing products.

Basically, it is a monolithic dual core building block that supports two threads of
execution and is intended for deployment in everything from mainstream clients (including
desktops and notebooks) to servers.

The bulldozer architecture has two dedicated integer cores. Each of these consist of
2 Arithmetic Logic Unit 2 AGU which together can execute 4 independent arithmetic or
memory operations per clock cycle per core. Core module of AMD bulldozer shares
portions of a traditional core—including the instruction fetch, decode, and floating-point
units and L2 cache—between two otherwise-complete processor cores. The integer core has
duplicating integer schedulers. The execution pipeline offers dedicated hardware
significantly increasing performance in multi-threaded integer applications.

IV