EEE 352: Lecture 18

* Complementary MOS Inverters

* Dynamic Random Access Memory

* Static Memory

* Growth of the VLSI Density

* Moore s Law

* Scaling the MOSFET

Portion of Pentium chip.

 n-Channel Inverter

VDS
When INPUT goes HIGH VDS

0 t
VDS
N

0 t

The OUTPUT goes LOW

A HIGH input voltage turns the transistor ON, which decreases

its resistance to a value much less than the RESISTOR, pulling
the output voltage to GROUND level.
 p-Channel Inverter

VDS
When INPUT goes LOW VDS

P 0 t
VDS

0 t

The OUTPUT goes HIGH

A LOW input voltage turns the transistor ON, which decreases its
resistance to a value much less than the RESISTOR, pulling the
output voltage to VDS level.
 The Complementary MOS Inverter
The RESISTORS dissipate too much power. We eliminate them by combining the two
circuits into one as a PUSH-PULL.

VDS VDS VDS

P
P
+ =
N N
 The Complementary MOS Inverter

VDS

When INPUT goes LOW, VDS

P
The OUTPUT goes HIGH
0 t

N VDS

When INPUT goes HIGH,

0 t
The OUTPUT goes LOW

A LOW input voltage turns the p-device ON, pulling the output
voltage to VDS level. A HIGH input voltage turns the n-device ON,
pulling the output to GROUND level.

The OFF transistor dissipates little power, so the CMOS circuit

dissipates almost ZERO power in the standby state—dissipation
only occurs during the SWITCH process when both transistors
are ON.
 The Complementary MOS Inverter

INTEL: S. Tyagi et al., IEDM 2000

 The Complementary MOS Inverter

Poly-silicon (or silicide)

Metal interconnects gates and interconnect
Oxides lines.

Field Field Field

oxide oxide oxide
P+ P+ N+ N+

pseudo n-well
p-well

n-type substrate
 Transistor for the 0.13 µm “Node”

INTEL: S. Tyagi et al., IEDM 2000

INTEL: S. Tyagi et al., IEDM 2000
 Dynamic Random Access Memory
VDS

row select
VDS
During WRITE operation, BOTH ROW and
COLUMN lines are at VDS, so that the
TRANSISTOR is ON and charge flows
ONTO the capacitor.

column select

row select
VDS
During READ operation, ONLY the ROW
and lines is at VDS. But the TRANSISTOR
VC is ON and charge flows OFF the
capacitor. The COLUMN line is used to
DETECT this charge with an AMPLIFIER.

column select
 Dynamic Random Access Memory

Metal interconnects Poly-silicon (or silicide)

Oxides gates and interconnect
lines.

Field Field
oxide oxide
N+ N+

p-well

n-type substrate

N+
trench capacitor
 Static Random Access Memory

row select

VDS

P P

N N

column select column select

complement
INTEL: S. Tyagi et al., IEDM 2000
INTEL: S. Tyagi et al., IEDM 2000
Pentium III
Progress in ULSI Integration on Single Chip—Moore s Law!

DRAM TODAY
Pentium IV
Pentium III

Pentium II

Logic!
 Moore s Law
(after Gordon Moore, of Intel, from an IEDM talk in mid-80s.
This has proven to be correct for the past 40 years.)

  The density of a chip increases a factor of 4 every three

years!
  This density increase arises from 3 factors:

1.  The critical length (gate length L) is reduced

by a factor of 1/21/2=0.7X each generation.
2.  There is an additional 1.5X compaction each
generation due to circuit cleverness.
3.  The DIE (chip) size increases in area by 1.33X
each generation. (In fact, this has not
occurred for the past decade.)
 Basic Structure of the MOSFET
tox
BIASED GATE
SOURCE DRAIN

+++++ +++++

INSULATING OXIDE LAYER

n+ n+
CHANNEL

P-TYPE

LG

1.  The critical length (gate length L) is reduced by a factor of

1/21/2=0.7X each generation.
 Devices will get smaller! SIA Projections:

1000
These projections are
being hit right on
schedule.
Dimension (nm)

100 DRAM
MPU Isolated Line

We have gate lengths

in the 30-50 nm
regime today. Lithography problem
Intel expects to be
10 here by the end of the
decade.
1995 2000 2005 2010 2015

Year
Devices will get smaller! Intel Projections:
 Scaling the MOSFET
CONTROL GATE
SOURCE DRAIN
oxide thickness t

INSULATING OXIDE LAYER

n n
L

p-TYPE LAYER

1.  We reduce the gate length by 0.7X

2.  We reduce the oxide thickness by 0.7X
3.  The area of the transistor is reduced by 0.5X
4.  In order to keep the field Eoxide constant, the operating
voltage must be reduced by 0.7X
5.  In order to reduce the depletion width of the p-n junctions
by 0.7X, we must increase the doping by 1.4X.

⎡ eW 2 N D N A ⎤
Vbi = ⎢ ⎥
⎣⎢ 2ε ( N D + N )
A ⎦⎥
 Scaling the MOSFET
CONTROL GATE
SOURCE DRAIN
oxide thickness t

INSULATING OXIDE LAYER

n n
L

p-TYPE LAYER

6.  The current decreases as 0.7X

Zeµ eCox ⎡ VDS ⎤

I= V
⎢ GS − − VT ⎥VDS
L ⎣ 2 ⎦

7.  The power decreases as (0.7)2=0.5X

 Scaling the MOSFET
CONTROL GATE
SOURCE DRAIN
oxide thickness t

INSULATING OXIDE LAYER

n n
L

p-TYPE LAYER

8.  The switching speed increases as 1/0.7=1.4X

1 V 1
f ~ , R = ⇒ 1 , C ~ ACox ~ 0.5 *
RC I 0.7
Devices will get faster! Intel Projections:

Today s hold on frequency increases

4 GHz
 Moore s Law
(after Gordon Moore, of Intel, from an IEDM talk in mid-80s.
This has proven to be correct for the past 40 years.)

  The density of a chip increases a factor of 4 every three years!

  This density increase arises from 3 factors:

1.  The critical length (gate length L) is reduced by a

factor of 1/21/2=0.7X each generation.
2.  There is an additional 1.5X compaction each
generation due to circuit cleverness.
3.  The DIE (chip) size increases in area by 1.33X
each generation.

The overscaling of the area, due to circuit cleverness, can increase the power
per unit area of the chip, so this cleverness must include new approaches to
lower the power dissipation in the circuit—low power designs.
 Scaling reduces dimensions by 0.7X,
but area by 0.33X due to overscaling

Chip area increases by 1.5X

ALMOST 5X INCREASE IN CHIP AREA!

Because of the increased power density (overscaling area), not all of
the speed increase can be used unless good low power design is
achieved.
New functions added to make the
new generation perform more
processing.

New, longer interconnects are

required to mold the new
functions into the overall
system architecture.

This requires new levels of

metal to cross the old,
optimized metallization.

WHY?
The number of functions on
chip increases faster than the
chip area, since the size per
function decreases due to
scaling
f ~ A1.4
time, chip area
The finished Si chip costs on
the order of $10-30 per square
centimer. Hence, the cost for
manufacturing, packaging,
and test of the chip increases
with time
$C ~ A
As a result, the cost per
function DECREASES as the
area increases
C
~ A− 0.4
F
The reduced cost per function
is the driving force for Moore s
Law and continuing scaling in
nanoelectronics.
In fact, Moore s Law has already been broken, as die size has not
been increasing as expected (or as predicted).

107 mm2 for dual core, > 4X108

transistors
215 mm2 for quad core, 8.2X108
transistors
As for what the future
really holds; there are
many theories:

But, there are very few

proofs (as we can see
from the appropriate
box)

Nevertheless, Moore s
law, and the
dominance of (Si) real
estate cost, can give
some guidance.
Cyrix 6x86