Class Notes Digital Lec13

`~ivjvcbx t Telephone :
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980
dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: APECE@univdhaka.edu
Ref. No............................ July 20, 2010

Dated, the………………………….
Dynamic RAM:
Dynamic RAMs are fabricated using MOS technology and are noted for their high capacity, low power requirement,
and moderate operating speed. DRAMs store 1s and 0s as charges on a small MOS capacitor. Because of the
tendency for these charges to leak off after a period of time, DRAMs require periodic recharging of the memory cells,
this is called refreshing. Each memory cell must be refreshed typically every 2, 4 or 8ms, or its data will be lost.
The need for refreshing is a drawback of dynamic RAM as compared to static RAM. Designing with and using DRAM
in a system is more complex than with SRAM. But because of their simple cell structure, DRAMs typically have four
times the density of SRAMs. Hence, DRAMs are the memory of choice in systems where the most important design
considerations are keeping down size, cost and power.
For applications where speed and reduced complexity are more critical than cost, space and power considerations,
static RAMs are still the best. They are generally faster than dynamic RAMs and require no refresh operation.
SW4
SW1 SW2 SW3

Data in
Data out
Sense
C amplifier
VREF
Fig.: Symbolic representation of a dynamic memory cell.

Figure shows a symbolic representation of a dynamic memory cell and its associated circuitry. The switches SW1
through SW4 are actually MOSFETs that are controlled by various address decoder outputs and the R/ W signal.
The capacitor is the actual storage cell.
To write data to the cell, signals from the address decoding and read/write logic close switches SW1 and SW2, while
keeping SW3 and SW4 open. This connects the input data to C. A logic 1 at the data input charges C, and a logic 0
discharges it. Then the switches are open so that C is disconnected from the rest of the circuit.
To read data from the cell, switches SW2, SW3 and SW4 are closed, and SW1 is kept open. This connects the
stored capacitor voltage to the sense amplifier. The sense amplifier compares the voltage with some reference value
to determine if it is a logic 0 or 1, and it produces a solid 0V or 5V for the data output. This data output is also
connected to C and refreshes the capacitor voltage by recharging or discharging.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]
Row and column address lines are usually multiplexed in a DRAM. This is done to reduce the number of pins on the
package. Row address select (RAS) and column address select (CAS) inputs are used to indicate whether a row or a
column is to be addressed.
As shown in the figure a DRAM consists of –
(I) An array of single-bit memory cells. Each cell occupies a unique row and column position within the array.
(II) Address decoders – row decoder and column decoder.
(III) Refresh control and
(IV) Address latches – row address latch and column address latch.
Seven address lines are time multiplexed at the beginning of the memory cycle by the RAS and CAS lines. Firstly,
the seven lower-order address bits A0 to A6 is latched into the row address latch, and then the seven higher-order
address bits A7 to A13 is latched into the column address latch. They are then decoded to select the particular
memory location.
Lec-13, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
Refresh Refresh control

circuitry and timing signals
---
A0 1
A1 2
- Memory array
A6 Data Row
128 rows x
selector decoder -
A0 Row - 128 column
Multiplexed A1 address -
address bus 127
A6 latch - 128
1 2 127 128
- - -
1
2
A7 Column Column - I/O buffer Data out
- A8 address - decoder - and sense
Data in
- A13 latch - - amplifier
127
128
CAS
RAS
R / W CS
Fig.: Architecture of a 16Kx1 dynamic RAM.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]
Read Cycle –
MUX
RAS
CAS
Address ROW COLUMN
Hi-Z Data
DATA OUT
valid
t1 t2 t3 t4 t5
t0
Fig.: Signal activity for a read operation on a dynamic RAM.
Assuming R/ W is in its HIGH state throughout the operation, the step-by-step description of read operation is –
t0: MUX is driven LOW to apply the row address bits (A0 to A6) to the DRAM address inputs.
t1: RAS is driven LOW to load the row address into the DRAM.
t2: MUX goes HIGH to place the column address (A7 to A13) at the DRAM address inputs.
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
t3: CAS goes LOW to load the column address into the DRAM.
t4: The DRAM responds by placing valid data from the selected memory cell onto the DATA OUT line.
t5: MUX, RAS , CAS and DATA OUT return to their initial states.
Write Cycle –
MUX
RAS
CAS
Address ROW COLUMN
R /W
Hi-Z Data
DATA OUT
valid
t0 t1 t2 t3 t4 t5 t6 t7
Fig.: Signal activity for a write operation on a dynamic RAM.

The sequence of events during write operation is –
t0: The LOW at MUX places the row address at the DRAM inputs.
t1: The NGT at RAS loads the row address into the DRAM.
t2: MUX goes HIGH to place the column address at the DRAM inputs.
t3: The NGT at CAS loads the column address into the DRAM.
t4: Data to be written are placed on the DATA IN line.
t5: R/ W is pulsed LOW to write the data into the selected cell.
t6: Input data are removed from DATA IN.
t7: MUX, RAS , CAS and R/ W are returned to their initial states.
Expanding Word Size:

When a given application requires a RAM or ROM with a capacity that is larger than what is available on a single
chip, more than one such chip can be used to achieve that objective. The required enhancement in capacity could be
either in terms of –
(I) increasing the word size, or
(II) increasing the number of memory locations.
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
AB3
AB2 Address
AB1 bus
AB0
R /W
CS
A3 A2 A1 A0 A3 A2 A1 A0
R /W RAM-0 R /W RAM-1
16x4 16x4
CS CS
I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0
DB7
DB6
DB5
DB4 Data
bus
DB3
DB2
DB1
DB0
Fig.: Combining two 16x4 RAMs for a 16x8 module.
Figure shows the configuration how two 16x4 memory chips with common I/O lines can be combined to produce a
memory that can store 16 eight-bit words.
RAM-0 stores the four higher-order bits of each of the 16 words, and RAM-1 stores the four lower-order bits of each
of the 16 words. A full eight-bit word is available at the RAM outputs connected to the data bus.
Any one of the 16 words is selected by applying the appropriate address code to the four-line address bus (AB3, AB2,
AB1, AB0). Since the address inputs are common, the same location in each chip is accessed at the same time.
To read, first the address is selected and then R/ W must be high and CS must be low. This causes RAM I/O lines
to act as outputs. RAM-0 places its selected four-bit word on the upper four data bus lines and RAM-1 places its
selected four-bit word on the lower four data bus lines. The data bus then contains the full selected eight-bit word,
which can now be transmitted to some other device.
Expanding Memory Location:

Figure shows how to produce a memory that can store 32 four-bit words by combining two 16x4 memory chips. Each
RAM is used to store 16 four-bit words. The four data I/O pins of each RAM are connected to a common four-line
data bus. Only one of the RAM chips can be selected at one time so that there will be no bus-contention problems.
Since the total capacity of this memory module is 32x4, there must be five address input lines. The MSB address bit
AB4 feeds the CS input of one chip directly and the CS input of other chip after inversion. This is used to select
one RAM or the other as the one that will be read from or written into. Four of the five address inputs AB0 to AB3,
other than the MSB address bit, are common to both 16x4 chips. They are used to select the one memory location
out of 16 from the selected RAM chip.
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
AB4
AB3
Address
AB2
bus
AB1
AB0
R /W
A3 A2 A1 A0 A3 A2 A1 A0
R /W RAM-0 R /W RAM-1
16x4 16x4
CS CS
I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0
DB3
DB2 Data
DB1 bus
DB0
Fig.: Combining two 16x4 chips for a 32x4 memory.
When AB4=0, the CS of RAM-0 enables this chip for read or write. Then any address location in RAM-0 can be
accessed by AB3 through AB0. Thus the range of addresses representing locations in RAM-0 is –
AB4AB3AB2AB1AB0 = 00000 to 01111.
The CS of RAM-1 is high, so that its I/O lines are disabled and cannot communicate with the data bus.
When AB4=1, it enables RAM-1 for read or write and disables RAM-0. Then any address location in RAM-1 can be
accessed by AB3 through AB0. Thus the range of addresses representing locations in RAM-1 is –
AB4AB3AB2AB1AB0 = 10000 to 11111.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]
Fixed Logic Versus Programmable Logic:

Three important classes of devices used to build digital electronics systems are –
(I) Memory devices – used to store information such as the software instructions of a program or the contents of
a database.
(II) Microprocessors – execute software instructions to perform a variety of functions.
(III) Logic devices – implement device-to-device interfacing, data timing, control and display operations etc.
There are two broad categories of logic devices –
(1) Fixed logic devices and
(2) Programmable logic devices.
(1) Fixed Logic Devices:
A fixed logic device performs a given logic function that is known at the time of device manufacture.
The circuits or building blocks and their interconnections in a fixed logic device are permanent and cannot be altered
after the device is manufactured.
Logic gates, multiplexers, demultiplexers, arithmetic circuits, flip-flops, counters, registers etc. are some examples of
fixed logic devices.
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
A
B
C
A
B
C
Y
A
B
C
A
B
C
Fig.: Fixed logic circuit.
Figure shows a simple logic circuit comprising four three-input AND gates and a four-input OR gate.
This circuit produces an output that is the sum output of a full adder. Here, A and B are the two bits to be added and
C is the carry-in bit.
It is a fixed logic device as the circuit is unalterable from outside owing to fixed interconnections between the various
building blocks.
(2) Programmable Logic Devices:
+V
A
B
C
+V
Y
+V
+V
Fig.: Simple programmable logic circuit.
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

UNIVERSITY OF DHAKA
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
Ref. No............................ July 20, 2010

Dated, the………………………….
The function to be performed by a programmable logic device is undefined at the time of its manufacture.
These devices can be configured by the user to perform a large variety of logic functions.
It offers to the user a wide range of logic capacity which can be configured by the user to perform the intended
function or set of functions. This configuration can be modified or altered any number of times by the user by
reprogramming the device.
Figure shows the logic diagram of a simple programmable device.
The device has an array of four six-input AND gates at the input and a four-input OR gate at the output. Each AND
gate can handle three variables A, B and C. The three variables or their complements can be programmed to appear
at the inputs of any of the four AND gates through antifuses. Thus each AND gate can produce the desired three-
variable product term.
Thus the circuit could be programmed to produce the sum output resulting from the addition of three bits or to
produce difference outputs resulting from subtraction of two bits with a borrow-in.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Class Notes Digital Lec13

Caricato da

Informazioni sul documento

Descrizione originale:

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Class Notes Digital Lec13

Caricato da

Copyright:

Formati disponibili

`~ivjvcbx t Telephone :

wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

SW1 SW2 SW3

Fig.: Symbolic representation of a dynamic memory cell.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

Refresh Refresh control

Address ROW COLUMN

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

Address ROW COLUMN

Fig.: Signal activity for a write operation on a dynamic RAM.

Expanding Word Size:

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0

Expanding Memory Location:

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0

Fixed Logic Versus Programmable Logic:

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

Fig.: Simple programmable logic circuit.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ July 20, 2010

Potrebbero piacerti anche