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Ref. No............................ July 18, 2010

Dated, the………………………….

Static RAM:
In SRAM, the memory cell is essentially a latch and can store data indefinitely as long as the DC power is supplied. It
does not need to be periodically refreshed.
SRAMs are available in bipolar, MOS (NMOS or CMOS) and BiCMOS technologies. While bipolar SRAM offers a
relatively higher speed of operation, MOS technology offers a higher capacity and reduced power consumption.
+VCC +VDD

Q3 Q4

Q1 Q2

Bipolar cell NMOS cell

Fig.: Typical bipolar and NMOS static-RAM cells.
The bipolar cell contains two bipolar transistors and two resistors. It requires more chip area because a bipolar
transistor is more complex than a MOSFET and it requires separate resistors.
The NMOS cell contains four N-channel MOSFETs and two of them (Q3 and Q4) are used as resistors. Its chip
density is high.
A CMOS memory cell would be similar to the NMOS cell except that it would use P-channel MOSFETs in place of Q3
and Q4. This results in the lowest power consumption but increases the chip complexity.
Read Cycle –
Figure shows the timing diagrams for a complete read cycle for a typical RAM chip. The CPU supplies these input
signals to the RAM when it wants to read data from a specific RAM address location.
tRC
1
Address
New address valid
inputs
0
tACC
R /W 1
1
CS
0 tOD
tCO
Hi-Z Hi-Z
Data output Data valid
to bus
t0 t1 t2 t3 t4

Fig.: Typical timing for a static-RAM read cycle.

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Dated, the………………………….

Prior to time t0, the R/ W line is HIGH and stays HIGH throughout the read cycle. The RAM’s data output is in its Hi-Z
state since CS =1. The address inputs will be whatever address is on the address bus from the preceding operation.
Since CS =1, it will not respond to its old address.
At t0, the CPU applies to the RAM inputs the address of the location to be read. After allowing time for the address
signals to stabilize, the CS line is activated.
At t1, the RAM places the data from the addressed location onto the data output line.
At t2, the CS is returned HIGH, and the RAM output returns to its Hi-Z state after a time interval, tOD.
The CPU can take the data from the data bus at any point between t1 and t3.
At t4, the CPU changes the address inputs to a different address for the next read or write cycle.
The RAM’s access time tACC is the time between the application of the new address and the appearance of valid
output data.
The timing parameter tCO is the time it takes for the RAM output to go from Hi-Z to a valid data level once CS is
activated.
Write Cycle –
tWC
1
Address
New address valid
inputs
0
tAS tAH
1
R /W
0
tW
1
CS
0 tDH
tDS
Hi-Z Hi-Z
Data input Data valid
from bus
t0 t1 t2 t3 t4
Fig.: Typical timing for a static-RAM write cycle.
At t0, the CPU supplies to the RAM a new address of the location to write into.
After waiting for a time interval tAS, called the address setup time, the CPU drives the R/ W and CS lines LOW and
are held LOW for a time interval tW, called the write time interval.
At t1, the CPU applies valid data to the data bus to be written into the RAM.
At t2, R/ W and CS are deactivated.
The data must be held at the RAM input for at least a time interval tDS, called the data setup time, prior to t2, and for at
least a time interval tDH, called the data hold time, after t2.
Similarly, the address inputs must remain stable for the address hold time interval tAH after t2.
At t4, the CPU changes the address lines to a new address for the next read or write cycle.
The complete write-cycle time tWC extends from t0 to t4.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

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Ref. No............................ July 18, 2010

Dated, the………………………….

Asynchronous SRAM:
Asynchronous SRAMs are those whose operations are not synchronized with the system clock, i.e., they operate
independently of the clock frequency. Data in and data out in these RAMs are controlled by address transition.
Data inputs
I7 I6 I1 I0

Input buffers E R /W

0 Register 0
1 Register 1
A5
2 Register 2
A4
Address A3 Decoder - -
inputs A2 6-line-to-64-line - - CS
A1 - -
A0
62 Register 62
63
Register 63

Output buffers E

O7 O6 O1 O0
Data outputs
Fig.: Typical architecture of a 64x8 asynchronous SRAM.
Figure shows the typical architecture of a 64x8 asynchronous SRAM. It is capable of storing 64 words of eight bits
each. The main blocks include –
(I) a 6-to-64 line address decoder,
(II) I/O buffers,
(III) 64 memory cells – memory cells in a row are represented as an eight-bit register and
(IV) control logic for read/write operations.
Control functions are provide by R/ W and CS inputs.
During the read operation, the status of the R/ W and CS pins is 1 and 0, respectively. The input buffers are
disabled and the contents of the selected register appear at the output.
During the write operation, the status of the R/ W and CS pins is 0 and 0, respectively. The input buffers are
enabled and the output buffers are disabled. The contents of the input buffers are loaded into the selected register,
the previous data are overwritten by the new data. The output buffers, being tristate, are in the High-Z state.
CS =1 deselects the chip, and both the input and the output data buffers get disabled and go to the high-impedance
state. The contents of the memory remain unaffected.

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Ref. No............................ July 18, 2010

Dated, the………………………….

Synchronous SRAM:
Synchronous SRAMs are those whose timings are initiated by clock edges. Address, data in, data out and all other
control signals are synchronized with the clock signal and clocked registers are used for the synchronization. In the
case of a computer system it operates at the same clock frequency as the microprocessor. This synchronization of
microprocessor and memory ensures faster execution speeds. Synchronous SRAMs normally have an address burst
feature, which allows the memory to read and write at more than one location using a single address.
Burst
control Binary
Counter
Q1 Q0

A0

A1

CLK A0 Address
A0 A1 Decoder -
A1 (14-line- Memory array
Address - -
to-16K (16Kx8)
- register - -
- - decoder)
-
A13 A13
- - -
- - -

Data Input Data Output

WE Write Register Register
register
- - - - - -
Data I/O
Control Output
CS Enable Buffers
Register - - -
OE
Data
I/O -
lines -
(I/O0-I/O7) -

Fig.: Architecture of a 16Kx8 synchronous SRAM.

Figure shows the basic architecture of a 16Kx8 synchronous SRAM with a burst feature that has five basic building
blocks –
(I) an array of 64 registers each capable of storing eight bits,
(II) a burst-logic, which basically produces a sequence of internal addresses – comprises a binary counter and
EX-OR gates,
(III) an address decoder with fourteen-bit input code to select address locations for reading or writing –

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Dated, the………………………….

(a) a certain number of highest address bits are fed directly from address register and
(b) the rest lowest address bits are fed from burst-logic output,
(IV) a read/write control logic and
(V) I/O buffers.
In the case of a two-bit burst logic, the internal address sequence generated is given by A1A0, A1 A0 , A1 A0 and
A1 A0 , where A0 and A1 are the address bits applied to the burst logic.
During read operation, WE is kept to 1, and CS and OE are kept to 0. For each negative going CLK input, the
burst logic output changes and selects different memory locations for the same external address inputs A0-A13. Thus
the contents of the selected registers will appear at the eight data outputs one after another. The input buffers remain
disable so that the data inputs do not affect the memory during a read operation.
During write operation, WE and CS are kept to 0 and OE is kept to 1. With CLK inputs, the address decoder
selects a burst of memory locations for the same external address inputs A0-A13. Thus a sequence of eight-bit words
applied to the data inputs will be loaded into the selected registers one after another with CLK pulses. These inputs
disable the output buffers so that the data outputs are in their Hi-Z state during a write operation.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

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