dsPIC30F SMPS

dsPIC30F SMPS
dsPIC30F SMPS Flash Programming Specification

1.0 OVERVIEW AND SCOPE There are two different methods used to program the
chip in the user’s system. One method uses the
This document defines the programming specification Enhanced In-Circuit Serial ProgrammingTM (Enhanced
for the dsPIC30F Switched Mode Power Supply ICSPTM) protocol and works with the programming
(SMPS) and Digital Power Conversion family of Digital executive. The other method uses In-Circuit Serial
Signal Controller (DSC) devices. The programming Programming (ICSP) protocol and does not use the
specification is required only for developers of programming executive.
third-party tools that are used to program dsPIC30F
The Enhanced ICSP protocol uses the faster,
SMPS devices. Customers using dsPIC30F SMPS
high-voltage method that takes advantage of the
devices should use development tools that already
programming executive. The programming executive
provide support for device programming.
provides all the necessary functionality to erase,
This document includes programming specifications program and verify the chip through a small command
for the following devices: set. The command set allows the programmer to
• dsPIC30F1010 program the dsPIC30F without having to deal with the
• dsPIC30F2020 low-level programming protocols of the chip.
• dsPIC30F2023
FIGURE 2-1: OVERVIEW OF dsPIC30F
The dsPIC30F SMPS family enters programming SMPS FAMILY
modes via the 32-bit serial key sequence clocked into
PROGRAMMING
the PGD line, similar to the dsPIC33F family. On the
other hand, the programming operations themselves
are similar to the other dsPIC30F devices. Programmer
The dsPIC30F SMPS family does not contain data
EEPROM.
2
2.0 PROGRAMMING OVERVIEW Programming

OF THE dsPIC30F SMPS Executive
On-chip Memory
The dsPIC30F SMPS family of DSCs contains a region
of on-chip memory used to simplify device dsPIC30F
programming. This memory region can store a
programming executive, which allows the dsPIC30F
SMPS to be programmed faster than the traditional The ICSP programming method does not use the
method. Once the programming executive is stored to programming executive. It provides native, low-level
memory by an external programmer (such as programming capability to erase, program and verify
Microchip’s MPLAB® ICD 2 or PRO MATE® II), it can the chip. This method is significantly slower because it
then interact with the external programmer to efficiently uses control codes to serially execute instructions on
program devices. the dsPIC30F SMPS device.
The programmer and programming executive have a This specification describes both the Enhanced ICSP
master-slave relationship, where the programmer is and ICSP programming methods. Section 3.0
the master programming device and the programming “Programming Executive Application” describes
executive is the slave, as illustrated in Figure 2-1. the programming executive application and
Section 5.0 “Device Programming” describes its
application programmer’s interface for the host.
© 2007 Microchip Technology Inc. DS70284B-page 1

dsPIC30F SMPS
2.1 Hardware Requirements Locations 0x800000 through 0x8005BE are reserved
for executive code memory. This region stores either
In Enhanced ICSP mode, the dsPIC30F SMPS the programming executive or the debugging
requires a single programmable power supply for VDD. executive. The programming executive is used for
Refer to Section 13.0 “AC/DC Characteristics and device programming, while the debug executive is
Timing Requirements” for hardware parameters. used for in-circuit debugging. This region of memory
cannot be used to store user code.
2.2 Pins Used During Programming Locations 0xF80000 through 0xF8000E are reserved
Table 2-2 lists the pins that are required for for the Configuration registers. The bits in these
programming. Refer to the appropriate device data registers may be set to select various device options,
sheet for complete pin descriptions. and are described in Section 5.7 “Configuration Bits
Programming”. The Configuration bits read out
2.3 Program Memory Map normally, even after code protection is applied.
Locations 0xFF0000 and 0xFF0002 are reserved for
The program memory space extends from 0x0 to the Device ID registers. These bits can be used by the
0xFFFFFE. Code storage is located at the base of the programmer to identify which device type is being
memory map and supports up to 12 Kbytes (4K programmed and are described in Section 10.0
instruction words). Table 2-1 shows the location and “Device ID”. The device ID reads out normally, even
program memory size of each device variant. after code protection is applied.
TABLE 2-1: CODE MEMORY MAP AND Figure 2-2 shows the memory map for the dsPIC30F
SIZE SMPS variants.
dsPIC30F SMPS Code Memory Map
Device (Size in Instruction Words) 2.4 Data EEPROM Memory
dsPIC30F1010 0x000000-0x000FFE (2K) The dsPIC30F SMPS family has no data EEPROM.
dsPIC30F2020 0x000000-0x001FFE (4K)
dsPIC30F2023 0x000000-0x001FFE (4K)
TABLE 2-2: PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING)

During Programming
Pin Name
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable

VDD and AVDD(1) VDD P Power Supply
VSS and AVSS(1) VSS P Ground
PGC PGC I Primary Programming Pin Pair: Serial Clock
PGD PGD I/O Primary Programming Pin Pair: Serial Data
PGC1 PGC1 I Secondary Programming Pin Pair: Serial Clock
PGD1 PGD1 I/O Secondary Programming Pin Pair: Serial Data
PGC2 PGC2 I Tertiary Programming Pin Pair: Serial Clock
PGD2 PGD2 I/O Tertiary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
DS70284B-page 2 © 2007 Microchip Technology Inc.

dsPIC30F SMPS
FIGURE 2-2: PROGRAM MEMORY MAP
000000
User Flash
Code Memory
(48K x 24-bit)
017FFE
018000
User Memory
Space
Reserved
7FFFFE
800000
Executive Code Memory
(Reserved)
8005BE
8005C0
Unit ID
(32 x 24-bit) 8005FE
800600
Reserved
Configuration Memory
Space
F7FFFE
Configuration Registers F80000
(8 x 16-bit) F8000E
F80010
Reserved
FEFFFE
Device ID FF0000
(2 x 16-bit) FF0002
FF0004
Reserved
FFFFFE
Note: The address boundaries for user Flash code memory are device specific.

dsPIC30F SMPS
3.0 PROGRAMMING EXECUTIVE 4.0 CONFIRMING THE CONTENTS
APPLICATION OF EXECUTIVE MEMORY
The programmer must confirm that the programming
3.1 Programming Executive Overview executive is stored in executive memory, before the
The programming executive resides in executive programming is begun. The procedure for this task is
memory and is executed when Enhanced ICSP shown in Figure 4-1.
Programming mode is entered. The programming First, In-Circuit Serial Programming mode (ICSP) is
executive provides the mechanism for the programmer entered. The unique application ID word stored in
(host device) to program and verify the dsPIC30F executive memory is then read. If the programming
SMPS, using a simple command set and executive is resident, the application ID word is 0xBB,
communication protocol. which means programming can resume as normal.
The following capabilities are provided by the However, if the application ID word is not 0xBB, the
programming executive: programming executive must be programmed to
Executive Code memory using the method described in
• Read memory Section 12.0 “Programming the Programming
- Code memory Executive to Memory”.
- Configuration registers Section 11.0 “ICSP™ Mode” describes the process
- Device ID for the ICSP programming method. Section 11.11
• Erase memory “Reading the Application ID Word” describes the
- Bulk Erase by segment procedure to read the application ID word in ICSP
- Code memory (by row) mode.
• Program memory
FIGURE 4-1: CONFIRMING PRESENCE
- Code memory
OF PROGRAMMING
- Configuration registers
EXECUTIVE
• Query
- Blank Device
Start
- Programming executive software version
The programming executive performs the low-level
tasks required for erasing and programming. This Enter ICSP™ Mode
allows the programmer to program the device by
issuing the appropriate commands and data.
The programming procedure is outlined in Section 5.0 Read the
“Device Programming”. Application ID
from Address
0x805BE
3.2 Programming Executive Code
Memory
The programming executive is stored in executive code Is
Application ID No
memory and executes from this reserved region of 0xBB?
memory. It requires no resources from user code
memory. Yes
3.3 Programming Executive Data RAM Prog. Executive is Prog. Executive must
Resident in Memory be Programmed
The programming executive uses the device’s data
RAM for variable storage and program execution. Once
the programming executive is run, no assumptions
should be made about the contents of data RAM.
Finish

dsPIC30F SMPS
5.0 DEVICE PROGRAMMING FIGURE 5-1: PROGRAMMING FLOW
5.1 Overview of the Programming Start

Process
Once the programming executive has been verified Enter Enhanced
in memory (or loaded if not present), the dsPIC30F ICSP™ Mode
SMPS can be programmed using the command set
shown in Table 5-1. A detailed description for each
command is provided in Section 8.0 “Programming Perform chip
Executive Commands”. erase
TABLE 5-1: COMMAND SET SUMMARY Program config

registers to default
Command Description
value
SCHECK Sanity check
READD Read Configuration registers and
device ID Program and
verify code
READP Read code memory
PROGP Program one row of code memory and
verify Program and
PROGC Program Configuration bits and verify verify data
ERASEB Bulk Erase or Segment Erase
ERASEP Erase code memory
Program and verify
QBLANK Query if the code memory is blank Configuration bits
QVER Query the software version
A high-level overview of the programming process is Exit Enhanced

ICSP Mode
shown in Figure 5-1. The process begins by entering
Enhanced ICSP mode. The chip is then bulk erased,
which clears all memory to ‘1’ and allows the device to
Finish
be programmed. The Chip Erase is verified before
programming begins. Next, the code memory, data
Flash and Configuration bits are programmed. As
these memories are programmed, they are each
verified to ensure that programming was successful. If
no errors are detected, the programming is complete
and Enhanced ICSP mode is exited. If any of the
verifications fail, the procedure should be repeated,
starting from the Chip Erase.

dsPIC30F SMPS
5.2 Entering Enhanced ICSP Mode hexadecimal format). See Appendix A: “Hex File
Format” for more information. The device enters
Figure 5-2 shows the three steps required to enter Program/Verify mode only if the key sequence is valid.
Enhanced ICSP Program/Verify mode: The Most Significant bit (MSb) of the most significant
1. The MCLR pin is briefly driven high, then low. nibble must be shifted in first.
2. A 32-bit key sequence is clocked into PGD. The key data is clocked on the rising edge of the clock
3. MCLR is then driven high within a specified PGC. Once the key sequence is complete, VIH must be
period of time and held. applied to MCLR and held at that level for as long as
Program/Verify mode has to be maintained. An interval
The programming voltage applied to MCLR is VIH,
of at least time P17 and P7 must elapse before
which is essentially VDD in the case of dsPIC30F
presenting data on PGD. Signals appearing on PGD
SMPS devices. There is no minimum time requirement
before P7 has elapsed will not be interpreted as valid.
for holding at VIH. After VIH is removed, an interval of at
least P16 must elapse before presenting the key On successful entry, the program memory can be
sequence on PGD. accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
The key sequence is a specific 32-bit pattern,
the high-impedance state.
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 0x4D434850 in
FIGURE 5-2: ENTERING ENHANCED ICSP™ MODE
P6
P17 P7
P12
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 0x4D434850
0 1 0 0 1 ... 0 0 0 0
PGD
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGC
P16 P2B
P2A
5.3 Exiting Enhanced ICSP Mode 5.4 Chip Erase

Exiting Program/Verify mode is done by removing VIH Before a chip can be programmed, it must be erased.
from MCLR, as shown in Figure 5-3. The only The Bulk Erase command (ERASEB) is used to perform
requirement for exit is that an interval P9b should this task. Executing this command with the MS
elapse between the last clock and program signals on command field set to 0x3 erases all code memory and
PGC and PGD before removing VIH. code-protect Configuration bits. The Chip Erase
process sets all bits in these three memory regions to ‘1’.
FIGURE 5-3: EXITING ENHANCED Since code protection Configuration bits are not
ICSP™ MODE erasable, they must be manually set to ‘1’ using
multiple PROGC commands. One PROGC command
P9b P15
must be sent for each Configuration register (see
MCLR VIH Section 5.7 “Configuration Bits Programming”).
Note: The Device ID registers cannot be erased.
VDD These registers remain intact after a Chip
Erase is performed.
VIH
PGD
PGC
PGD = Input

dsPIC30F SMPS
5.5 Blank Check decremented by ‘1’ and compared to ‘0’. Since there are
more PROGP commands to send, ‘BaseAddress’ is
The term “Blank Check” means to verify whether the incremented by 0x40 to point to the next row of memory.
device has been successfully erased and has no
programmed memory cells. A blank or erased memory On the second PROGP command, the second row of each
cell reads as a ‘1’. The following memories must be memory panel is programmed. This process is repeated
blank checked: until the entire device is programmed. No special
handling must be performed when a panel boundary is
• All implemented code memory crossed.
• All Configuration bits (for their default value)
5.6.3 PROGRAMMING VERIFICATION
The Device ID registers (0xFF0000:0xFF0002) can be
ignored by the Blank Check since this region stores After programming the code memory, the contents of
device information that can not be erased. Additionally, memory can be verified to ensure that programming
all unimplemented memory space should be ignored was successful. Verification requires code memory to
from the Blank Check. be read back and compared against the copy held in
the programmer’s buffer.
The QBLANK command is used for the Blank Check. It
determines if the code memory is erased by testing The READP command can be used to read back all the
these memory regions. A ‘BLANK’ or ‘NOT BLANK’ programmed code memory.
response is returned. The READD command is used to Alternatively, you can have the programmer perform
read the Configuration registers. If it is determined that the verification once the entire device is programmed
the device is not blank, it must be erased (see using a checksum computation, as described in
Section 5.4 “Chip Erase”) before attempting to Section 6.6 “Checksum Computation”.
program the chip.
5.6 Code Memory Programming FIGURE 5-4: FLOWCHART FOR

PROGRAMMING dsPIC30F
5.6.1 OVERVIEW SMPS CODE MEMORY
The panel architecture for the Flash code memory
array consists of up to 128 rows of thirty-two, 24-bit Start
instructions. Each panel stores up to 4K instruction
words. Each dsPIC30F SMPS variant has one memory
panel (see Table 5-2). BaseAddress = 0x0
RemainingCmds =128
TABLE 5-2: DEVICE CODE MEMORY SIZE
Code Size Number Number
dsPIC30F SMPS
(24-bit of of
Device Send PROGP
Words) Rows Panels Command To Program
BaseAddress
dsPIC30F1010 2K 64 1
dsPIC30F2020 4K 128 1
dsPIC30F2023 4K 128 1
Is
PROGP response No
5.6.2 PROGRAMMING METHODOLOGY
PASS?
Code memory is programmed with the PROGP
command. PROGP programs one row of code memory Yes
to the memory address specified in the command. The
number of PROGP commands required to program a RemainingCmds =
device depends on the number of rows that must be RemainingCmds - 1
programmed in the device.
A flowchart for programming of code memory is shown BaseAddress =
in Figure 5-4. In this example, all 4K instruction words BaseAddress
of a dsPIC30F2020 device are programmed. First, the + 0x40
number of commands to send (called Is
‘RemainingCmds’ in the flowchart) is set to 128 and the No
RemainingCmds
destination address (called ‘BaseAddress’) is set to ‘0’. ‘0’?
Next, one row in the device is programmed with a PROGP Yes
command. Each PROGP command contains data for one
row of code memory. After the first command is Failure
processed successfully, ‘RemainingCmds’ is Finish Report Error

dsPIC30F SMPS
5.7 Configuration Bits Programming Table 5-3 shows the Configuration registers for the
SMPS devices, and Table 5-4 describes the individual
5.7.1 OVERVIEW bits.
The dsPIC30F SMPS has Configuration bits stored Note: If user software performs an erase opera-
in seven 16-bit registers. These bits can be set or tion on the configuration fuse, it must be
cleared to select various device configurations. followed by a write operation to this fuse
There are two types of Configuration bits: system with the desired value, even if the desired
operation bits and code-protect bits. The system value is the same as the state of the
operation bits determine the power-on settings for erased fuse.
system level components such as the oscillator and
Watchdog Timer. The code-protect bits prevent
program memory from being read and written.
TABLE 5-3: dsPIC30F SMPS FAMILY DEVICE CONFIGURATION REGISTER MAP

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0xF80000 FBS — BSS<2:0> BWRP
0xF80002 RESERVED —
0xF80004 FGS — GSS<1:0> GWRP
0xF80006 FOSCSEL — FNOSC<1:0>
0xF80008 FOSC FCKSM<1:0> FRANGE — OSCIOFNC POSCMD<1:0>
0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0>
0xF8000C FPOR — FPWRT<2:0>
0xF8000E FICD BKBUG — ICS<1:0>
TABLE 5-4: dsPIC30F SMPS DEVICE CONFIGURATION BITS DESCRIPTION

Bit Field Register Description
BSS<2:0> FBS Boot Segment Program Memory Code Protection
111 = No Boot Segment
110 = Standard security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF]
101 = Standard security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x000FFF
Note: This is for the dsPIC30F2020 and dsPIC30F2023 only.]
010 = High security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF]
001 = High security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x000FFF
Note: This is for the dsPIC30F2020 and dsPIC30F2023 only.]
BWRP FBS Boot Segment Program Memory Write Protection
1 = Boot Segment program memory is not write-protected
0 = Boot program memory is write-protected
GSS<1:0> FGS General Segment Code-Protect bit
11 = Code protection is disabled
10 = Standard security code protection is enabled
0x = Reserved
GWRP FGS General Segment Write-Protect bit
1 = General Segment program memory is not write-protected
0 = General Segment program memory is write-protected
FNOSC<1:0> FOSCSEL Initial Oscillator Source Selection bits
11 = Primary (HS, EC) oscillator with PLL
10 = Primary (HS, EC) oscillator
01 = Internal Fast RC (FRC) oscillator with PLL
00 = Internal Fast RC (FRC) oscillator

dsPIC30F SMPS
TABLE 5-4: dsPIC30F SMPS DEVICE CONFIGURATION BITS DESCRIPTION (CONTINUED)
FCKSM<1:0> FOSC Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FRANGE FOSC Frequency Range Selection for FRC oscillator
1 = High Range: nominal FRC frequency is 14.1 MHz
0 = Low Range: nominal FRC frequency is 9.7 MHz
OSCIOFNC FOSC OSC2 Pin Function bit (except in HS mode)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
POSCMD<1:0> FOSC Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS crystal oscillator mode
01 = Reserved
00 = EC (external clock) mode
FWDTEN FWDT Watchdog Enable bit
1 = Watchdog always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect)
0 = Watchdog enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS FWDT Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE FWDT Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> FWDT Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
FPWRT<2:0> FPOR Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT Disabled
BKBUG FICD Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
ICS<1:0> FICD ICD Communication Channel Select bits
11 = Communicate on PGC/EMUC and PGD/EMUD
10 = Communicate on PGC1/EMUC1 and PGD1/EMUD1
01 = Communicate on PGC2/EMUC2 and PGD2/EMUD2
00 = Reserved, do not use
— All Unimplemented (read as ‘0’, write as ‘0’)

dsPIC30F SMPS
5.7.2 PROGRAMMING METHODOLOGY BWRP and GWRP bits control write protection and
BSS<2:0> and GSS<1:0> bits control read protection.
System operation Configuration bits are inherently
The Chip Erase ERASEB command sets all the code
different than all other memory cells. Unlike code
protection bits to ‘1’, which allows the device to be
memory and code-protect Configuration bits, the
programmed.
system operation bits cannot be erased. If the chip is
erased with the ERASEB command, the system When write protection is enabled, any programming
operation bits retain their previous value. operation to code memory will fail. When read
Consequently, you should make no assumption about protection is enabled, any read from code memory will
the value of the system operation bits. They should cause a ‘0x0’ to be read, regardless of the actual
always be programmed to their desired setting. contents of code memory. Since the programming
executive always verifies what it programs, attempting
Configuration bits are programmed single word at
to program code memory with read protection enabled
a time using the PROGC command. The PROGC
will also result in failure.
command specifies the configuration data and
Configuration register address. When Configuration It is imperative that all code protection bits are ‘1’ while
bits are programmed, any unimplemented bits must be the device is being programmed and verified. Only after
programmed with a ‘0’, and any reserved bits must be the device is programmed and verified should any of
programmed with a ‘1’. the above bits be programmed to ‘0’.
Four PROGC commands are required to program all the Note: All bits in the FBS and FGS Configuration
Configuration bits. A flowchart for Configuration bit registers can only be programmed to a
programming is shown in Figure 5-5. value of ‘0’. The ERASEB command is the
only way to reprogram code-protect bits
Note: If the General Code Segment Code
from ON (‘0’) to OFF (‘1’).
Protect (GCP) bit is programmed to ‘0’,
code memory is code-protected and Before performing any segment erase operation, the
cannot be read. Code memory must programmer must first determine whether the
be verified before enabling read dsPIC30F device has defined a Boot Segment, and
protection. See Section 5.7.4 “Code- ensure that a segment does not get overwritten by
Guard™ Security Configuration Bits” operations on any other segment. Also, a Bulk Erase
for more information about code-protect should not be performed if a Boot Segment has been
Configuration bits. defined.
The BSS bit field in the FBS Configuration register can
5.7.3 PROGRAMMING VERIFICATION be read to determine whether a Boot Segment has
Once the Configuration bits are programmed, the been defined. If a Boot Segment has already been
contents of memory should be verified to ensure that defined (and has probably already been programmed),
the programming is successful. Verification requires the user must be warned about this fact.
the Configuration bits to be read back and compared A Bulk Erase operation is the recommended
against the copy held in the programmer’s buffer. The mechanism to allow a user to overwrite the Boot
READD command reads back the programmed Segment (if one chooses to do so).
Configuration bits and verifies that the programming
was successful. In general, the segments and CodeGuard Security
related Configuration registers should be programmed
Any unimplemented Configuration bits are read-only in the following order:
and read as ‘0’.
• FBS and Boot Segment
5.7.4 CodeGuard™ SECURITY • FGS and General Segment
CONFIGURATION BITS
5.7.5 USER UNIT ID
The FBS and FGS Configuration registers are special
Configuration registers that control the size and level of The dsPIC30F SMPS devices contain 32 instructions
code protection for the Boot Segment and General of Unit ID. These are located at addresses 0x8005C0
Segment, respectively. For each segment, two main through 0x8005FF. The Unit ID can be used for storing
forms of code protection are provided. One form product information such as serial numbers, system
prevents code memory from being written (write manufacturing dates, manufacturing lot numbers and
protection), while the other prevents code memory from other such application-specific information.
being read (read protection). The dsPIC30F SMPS Programming the UNIT ID is similar to programming
family devices do not contain a Secure Segment. the Programming Executive (see Section 12.0
“Programming the Programming Executive to
Memory” for details).

dsPIC30F SMPS
FIGURE 5-5: CONFIGURATION BIT PROGRAMMING FLOW
Start
ConfigAddress = 0xF80000
Send PROGC
Command
Is No
PROGC Response
PASS?
Yes
Is
ConfigAddress = No
ConfigAddress
ConfigAddress+2
0xF8000C?
Yes
Failure
Finish
Report Error
Note: If any of the code-protect bits in FBS or

FGS is clear, then the entire device must
be erased before it can be reprogrammed.

dsPIC30F SMPS
6.0 OTHER PROGRAMMING In these cases, when code memory is programmed,
single-panel programming must be specified in the
FEATURES
PROGP command.
6.1 Erasing Memory For modification of code-protect bits, the entire chip
must first be erased with the ERASEB command. The
Memory is erased by using an ERASEB or ERASEP code-protect bits can be reprogrammed using the
command, as detailed in Section 8.5 “Command PROGC command.
Descriptions”. Code memory can be erased by row
Note: If read or write code protection is enabled,
using the ERASEP command. When memory is erased,
no modifications can be made to any
the affected memory locations are set to ‘1’s.
region of code memory until code
The ERASEB command provides several Bulk Erase protection is disabled. Code protection
options. Performing a Chip Erase with the ERASEB can only be disabled by performing a Chip
command clears all code memory and code protection Erase with the ERASEB command.
registers. Alternatively, the ERASEB command can be
used to selectively erase individual program memory
6.3 Reading Memory
segments.Table 6-1 summarizes the Erase options.
The READD command reads the Configuration bits and
TABLE 6-1: ERASE OPTIONS device ID of the device. This command only returns
16-bit data and operates on 16-bit registers.
Command Affected Region
The READP command reads the code memory of the
ERASEB Entire chip(1) or all code memory device. This command only returns 24-bit data packed
ERASEP(2) Specified rows of code memory as described in Section 8.3 “Packed Data Format”.
Note 1: The system operation Configuration The READP command can be used to read up to 32K
registers and device ID registers are not instruction words of code memory (only 4K instruction
erasable. words are present on the dsPIC30F SMPS devices).
2: ERASEP can not be used to erase Note: Reading an unimplemented memory
code-protect Configuration bits. These bits location causes the programming
must be erased using ERASEB. executive to reset. All READD and READP
commands must specify only valid
6.2 Modifying Memory memory locations.
Instead of bulk-erasing the device before starting to 6.4 Programming Executive Software
program, it is possible that you may want to modify only
Version
a section of an already programmed device. In this
situation, Chip Erase is not a realistic option. At times, it may be necessary to determine the version
Instead, you can erase selective rows of code memory of programming executive stored in executive memory.
using the ERASEP command. You can then reprogram The QVER command performs this function. See
the modified rows with the PROGP command pairs. Section 8.5.9 “QVER Command” for details of QVER
command.

dsPIC30F SMPS
6.5 Configuration Information in the All memory locations are summed one byte at a time,
Hex File using only their native data size. More specifically,
configuration and device ID registers are summed by
To allow portability of code, the programmer must read adding the lower two bytes of these locations (the
the Configuration register locations from the hex file upper byte is ignored), while code memory is summed
(see Appendix A: “Hex File Format”). If configuration by adding all three bytes of code memory.
information is not present in the hex file, a simple
Table 6-2 shows how this 16-bit computation can be
warning message should be issued by the
made for each dsPIC30F SMPS device. Computations
programmer. Similarly, while saving a hex file, all
for read code protection are shown both enabled and
configuration information must be included. An option
disabled. The checksum values assume that the
can be provided not to include the configuration
Configuration registers are also erased. However,
information.
when code protection is enabled, the value of the FGS
Microchip Technology Inc. feels strongly that this register is assumed to be 0x5.
feature is important for the benefit of the end customer.
Note: The checksum calculation differs
depending on the code-protect setting.
6.6 Checksum Computation Table 6-2 describes how to compute the
Checksums for the dsPIC30F SMPS are 16 bits in size. checksum for an unprotected device and a
The checksum is calculated by summing the following: read-protected device. Regardless of the
code-protect setting, the Configuration
• Contents of code memory locations
registers can always be read.
• Contents of Configuration registers
TABLE 6-2: CHECKSUM COMPUTATION

Value with
Read Code Erased 0xAAAAAA at 0x0
SMPS Device Checksum Computation
Protection Value and Last
Code Address
dsPIC30F1010 Disabled CFGB + SUM(0:000FFF) 0xEA69 0xE86B
Enabled CFGB 0x0267 0x0267
dsPIC30F2020 Disabled CFGB + SUM(0:001FFF) 0xD269 0xD06B
dsPIC30F2023 Disabled CFGB + SUM(0:001FFF) 0xD269 0xD06B
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x000F) + (FGS & 0x0007) + (FOSCSEL &
0x0003) + (FOSC & 0x00E7) + (FWDT & 0x00DF) + (FPOR & 0x0007) + (FICD & 0x0083))

dsPIC30F SMPS
7.0 PROGRAMMER – Since a 2-wire SPI interface is used, and data
transmissions are bidirectional, a simple protocol is
PROGRAMMING EXECUTIVE
used to control the direction of PGD. When the
COMMUNICATION programmer completes a command transmission, it
releases the PGD line and allows the programming
7.1 Communication Overview executive to drive this line high. The programming
executive keeps the PGD line high to indicate that it is
The programmer and programming executive have a processing the command.
master-slave relationship, where the programmer is
the master programming device and the programming After the programming executive has processed the
executive is the slave. command, it brings PGD low for 15 μsec to indicate to
the programmer that the response is available to be
All communication is initiated by the programmer in the clocked out. The programmer can begin to clock out
form of a command. Only one command at a time can the response 20 μsec after PGD is brought low, and it
be sent to the programming executive. In turn, the must provide the necessary amount of clock pulses to
programming executive only sends one response to receive the entire response from the programming
the programmer after receiving and processing a executive.
command. The programming executive command set
is described in Section 8.0 “Programming Executive Once the entire response is clocked out, the
Commands”. The response set is described in programmer should terminate the clock on PGC until it
Section 9.0 “Programming Executive Responses”. is time to send another command to the programming
executive. This protocol is shown in Figure 7-2.
7.2 Communication Interface and
Protocol 7.3 SPI Rate
In Enhanced ICSP mode, the dsPIC30F SMPS
The Enhanced ICSP interface is a 2-wire SPI interface
operates from the fast internal RC oscillator FRC,
implemented using the PGC and PGD pins. The PGC
which has a nominal frequency of 10 or 15 MHz. This
pin is used as a clock input pin, and the clock source
oscillator frequency yields an effective system clock
must be provided by the programmer. The PGD pin is
frequency of 2.5 or 3.75 MHz. Since the SPI module
used for sending command data to, and receiving
operates in Slave mode, the programmer must limit the
response data from the programming executive. All
SPI clock rate to a frequency not greater than 1 MHz.
serial data is transmitted on the rising edge of PGC and
is latched on the falling edge of PGC. All data Note: If the programmer provides the SPI with a
transmissions are sent to the Most Significant bit (MSb) clock faster than 1 MHz, the behavior of
first, using 16-bit mode (see Figure 7-1). the programming executive will be
unpredictable.
FIGURE 7-1: PROGRAMMING
EXECUTIVE SERIAL 7.4 Time Outs
TIMING
The programming executive uses no Watchdog Timer
P1 or time out for transmitting responses to the
1 2 3 4 5 6 11 12 13 14 15 16 programmer. If the programmer does not follow the
PGC flow control mechanism using PGC, as described in
Section 7.2 “Communication Interface and Proto-
P1b
P3 col”, it is possible that the programming executive will
P1a
behave unexpectedly while trying to send a response
P2
PGD to the programmer. Since the programming executive
MSb 14 13 12 11 ... 5 4 3 2 1 LSb has no time out, it is imperative that the programmer
correctly follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in Table 8-1. If the
command time out expires, the programmer should
reset the programming executive and start
programming the device again.

dsPIC30F SMPS
FIGURE 7-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
Host Transmits Programming Executive

Host Clocks Out Response
Last Command Word Processes Command
1 2 15 16 1 2 15 16 1 2 15 16
PGC
PGD MSB X X X LSB 1 0 MSB X X X LSB MSB X X X LSB
P8 P9a P9b P10 P11
PGC = Input PGC = Input (Idle) PGC = Input

PGD = Input PGD = Output PGD = Output

dsPIC30F SMPS
8.0 PROGRAMMING EXECUTIVE 8.3 Packed Data Format
COMMANDS When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
8.1 Command Set space using the format shown in Figure 8-2. This
format minimizes traffic over the SPI and provides the
The programming executive command set is shown in programming executive with data that is properly
Table 8-1. This table contains the opcode, mnemonic, aligned for performing table write operations.
length, time out and description for each command.
Functional details on each command are provided in
FIGURE 8-2: PACKED INSTRUCTION
the command descriptions (Section 8.5 “Command
Descriptions”). WORD FORMAT
15 8 7 0
8.2 Command Format
lsw1
All programming executive commands have a general MSB2 MSB1
format consisting of a 16-bit header and any required
lsw2
data for the command (see Figure 8-1). The 16-bit
header consists of a 4-bit opcode field, which is used to lswx: Least significant 16-bits of instruction word
identify the command, followed by a 12-bit command MSBx: Most significant byte of instruction word
length field.
Note: When the number of instruction words

FIGURE 8-1: COMMAND FORMAT
transferred is odd, MSB2 is zero and lsw2
15 12 11 0 can not be transmitted.
Opcode Length
8.4 Programming Executive Error
Command Data First Word (if required)
Handling
•
The programming executive will “NACK” all
•
unsupported commands. Additionally, due to the
Command Data Last Word (if required) memory constraints of the programming executive, no
checking is performed on the data contained in the
The command opcode must match one of those in the
programmer command. It is the responsibility of the
command set. Any command that is received which
programmer to command the programming executive
does not match the list in Table 8-1 will return a “NACK”
with valid command arguments, or the programming
response (see Section 9.2.1 “Opcode Field”).
operation may fail. Additional information on error
The command length is represented in 16-bit words handling is provided in Section 9.2.3 “QE_Code
since the SPI operates in 16-bit mode. The Field”.
programming executive uses the Command Length
field to determine the number of words to read from the
SPI port. If the value of this field is incorrect, the
command will not be properly received by the
programming executive.

dsPIC30F SMPS
TABLE 8-1: PROGRAMMING EXECUTIVE COMMAND SET
Length
Opcode Mnemonic (16-bit Time Out Description
words)
0x0 SCHECK 1 1 msec Sanity check.
0x1 READD 4 1 Read N 16-bit words of Configuration registers or device ID
msec/row starting from specified address.
0x2 READP 4 1 Read N 24-bit instruction words of code memory starting from
msec/row specified address.
0x3 RESERVED N/A N/A This command is reserved. It will return a NACK.
0x4 PROGD 19 5 msec Not implemented.
0x5 PROGP(1) 51 5 msec Program one row of code memory at the specified address, then
verify.
0x6 PROGC 4 5 msec Write byte or 16-bit word to specified Configuration register.
0x7 ERASEB 2 5 msec Bulk Erase (entire program memory), or erase by segment.
0x8 ERASED 3 5 Not Implemented.
msec/row
0x9 ERASEP(1) 3 5 Erase rows of code memory from specified address.
msec/row
0xA QBLANK 3 300 msec Query if the code memory is blank.
0xB QVER 1 1 msec Query the programming executive software version.
Note 1: One row of code memory consists of thirty-two 24-bit words. Refer to Table 5-2 for device-specific
information.

dsPIC30F SMPS
8.5 Command Descriptions 8.5.2 READD COMMAND
All commands supported by the programming 15 12 11 8 7 0
executive are described in Section 8.5.1 “SCHECK Opcode Length
Command” through Section 8.5.9 “QVER
Reserved0 N
Command”.
Reserved1 Addr_MSB
8.5.1 SCHECK COMMAND Addr_LS
15 12 11 0
Opcode Length Field Description
Opcode 0x1
Field Description Length 0x4
Opcode 0x0 Reserved0 0x0
Length 0x1 N Number of 16-bit words to read
(max of 2048)
The SCHECK command instructs the programming
executive to do nothing, but generate a response. This Reserved1 0x0
command is used as a “sanity check” to verify that the Addr_MSB MSB of 24-bit source address
programming executive is operational. Addr_LS LS 16 bits of 24-bit source address
Expected Response (2 words): The READD command instructs the programming
0x1000 executive to read N 16-bit words of memory starting
0x0002 from the 24-bit address specified by Addr_MSB and
Addr_LS. This command can only be used to read
16-bit data. It can be used to read Configuration
Note: This instruction is not required for registers and the device ID.
programming, but is provided for
development purposes only. Expected Response (2 + N words):
0x1100
N+2
Data word 1
...
Data word N
Note: Reading unimplemented memory will

cause the programming executive to
Reset.

dsPIC30F SMPS
8.5.3 READP COMMAND 8.5.4 PROGP COMMAND
15 12 11 8 7 0 15 12 11 8 7 0
Opcode Length Opcode Length
N Reserved Addr_MSB
Reserved Addr_MSB Addr_LS
Addr_LS D_1
D_2
...
Field Description
D_N
Opcode 0x2
Length 0x4
N Number of 24-bit instructions to read Field Description
(max of 32768) Opcode 0x5
Reserved 0x0 Length 0x33
Addr_MSB MSB of 24-bit source address Reserved 0x0
Addr_LS LS 16 bits of 24-bit source address Addr_MSB MSB of 24-bit destination address
The READP command instructs the programming Addr_LS LS 16 bits of 24-bit destination address
executive to read N 24-bit words of code memory D_1 16-bit data word 1
starting from the 24-bit address specified by Addr_MSB
and Addr_LS. This command can only be used to read D_2 16-bit data word 2
24-bit data. All data returned in response to this ... 16-bit data word 3 through 47
command uses the packed data format described in D_48 16-bit data word 48
Section 8.3 “Packed Data Format”.
The PROGP command instructs the programming
Expected Response (2 + 3 * N/2 words for N even): executive to program one row of code memory (32
0x1200 instruction words) to the specified memory address.
2 + 3 * N/2 Programming begins with the row address specified in
Least significant program memory word 1 the command. The destination address should be a
... multiple of 0x40.
Least significant data word N
The data to program memory, located in command
words D_1 through D_48, must be arranged using the
Expected Response (4 + 3 * (N–1)/2 words for N odd): packed instruction word format shown in Figure 8-2.
0x1200 After all data has been programmed to code memory,
4 + 3 * (N–1)/2 the programming executive verifies the programmed
Least significant program memory word 1 data against the data in the command.
...
MSB of program memory word N (zero padded) Expected Response (2 words):
0x1500
0x0002
Note: Reading unimplemented memory will
cause the programming executive to
reset. Note: Refer to Table 5-2 for code memory size
information.

dsPIC30F SMPS
8.5.5 PROGC COMMAND 8.5.6 ERASEB COMMAND
15 12 11 8 7 0 15 12 11 2 0
Reserved Addr_MSB Reserved MS
Addr_LS
Data
Field Description
Opcode 0x7
Field Description Length 0x2
Opcode 0x6 Reserved 0x0
Length 0x4 MS Select memory to erase:
Reserved 0x0 0x0 = All Code in General Segment
0x1 = Reserved
Addr_MSB MSB of 24-bit destination address
0x2 = All Code in General Segment,
Addr_LS LS 16 bits of 24-bit destination interrupt vectors, and FGS Configuration
address register
Data Data to program 0x3 = Full Chip Erase
0x4 = All Code in Boot and General
The PROGC command programs data to the specified
Segments, and the FBS and FGS
Configuration register and verifies whether the
Configuration registers
programming. Configuration registers are 16 bits wide,
0x5 = All Code in General Segment,
and this command allows one Configuration register to
and the FGS Configuration register
be programmed.
0x6 = Reserved
Expected Response (2 words): 0x7 = Reserved
0x1600
The ERASEB command performs a Bulk Erase. The MS
0x0002
field selects the memory to be bulk erased, with options
for erasing individual memory segments.
Note: This command can only be used for When Full Chip Erase is selected, the following
programming Configuration registers. memory regions are erased:
• All code memory (even if code-protected)
• All code-protect Configuration registers, including
Unit ID
Only the executive code memory, device ID and
Configuration registers that are not code-protected
remain intact after a Full Chip Erase.
Expected Response (2 words):
0x1700
0x0002

dsPIC30F SMPS
8.5.7 ERASEP COMMAND 8.5.8 QBLANK COMMAND
15 12 11 8 7 0 15 12 11 0
Num_Rows Addr_MSB PSize
Addr_LS Reserved DSize
Field Description Field Description

Opcode 0x9 Opcode 0xA
Length 0x3 Length 0x3
Num_Rows Number of rows to erase PSize Length of program memory to check
Addr_MSB MSB of 24-bit base address (in 24-bit words), max of 49152
Addr_LS LS 16 bits of 24-bit base address Reserved 0x0
DSize Length of data memory to check
The ERASEP command erases the specified number of
(in 16-bit words), max of 2048
rows of code memory from the specified base address.
The specified base address must be a multiple of 0x40. The QBLANK command queries the programming
Once the erase is performed, all targeted words of executive to determine whether the contents of code
code memory contain 0xFFFFFF. memory is blank (contains all ‘1’s). The size of code
memory to check must be specified in the command.
0x1900 The Blank Check for code memory begins at 0x0 and
0x0002 advances toward larger addresses for the specified
number of instruction words.
The QBLANK command returns a QE_Code of 0xF0 if
Note: The ERASEP command cannot be used to the specified code memory is blank. Otherwise,
erase the Configuration registers or QBLANK returns a QE_Code of 0x0F.
device ID. CodeGuard Security
Expected Response (2 words for blank device):
code-protect Configuration registers can
0x1AF0
only be erased with ERASEB, while the
0x0002
device ID is read-only.
Expected Response (2 words for non-blank device):
0x1A0F
0x0002
Note: The QBLANK command does not check

the system Configuration registers. The
READD command must be used to
determine the state of the Configuration
registers.

dsPIC30F SMPS
8.5.9 QVER COMMAND 9.2 Response Format
15 12 11 0 All programming executive responses have a general
Opcode Length format consisting of a two-word header and any
required data for the command.
Field Description
Opcode 0xB 15 12 11 8 7 0
Length 0x1 Opcode QE_Code
The QVER command queries the version of the Last_Cmd
programming executive software stored in test
Length
memory. The “version.revision” information is returned
in the response’s QE_Code using a single byte with the D_1 (if applicable)
following format: main version in upper nibble and
revision in the lower nibble (i.e., 0x23 means version ...
2.3 of programming executive software).
D_N (if applicable)
0x1BMN (where “MN” stands for version M.N)
0x0002
Field Description
9.0 PROGRAMMING EXECUTIVE Opcode Response opcode.
RESPONSES Last_Cmd Programmer command that
generated the response.
9.1 Overview QE_Code Query code or Error code.
The programming executive sends a response to the Length Response length in 16-bit words
programmer for each command that it receives. The (includes 2 header words.)
response indicates if the command was processed D_1 First 16-bit data word (if applicable).
correctly, and includes any required response, or error,
D_N Last 16-bit data word (if applicable).
data.
The programming executive response set is shown in 9.2.1 Opcode FIELD
Table 9-1. This table contains the opcode, mnemonic
The Opcode is a 4-bit field in the first word of the
and description for each response. The response
response. The Opcode indicates how the command is
format is described in Section 9.2 “Response
processed (see Table 9-1). If the command is
Format”.
processed successfully, the response opcode is PASS.
If there is an error in processing the command, the
TABLE 9-1: PROGRAMMING EXECUTIVE response opcode is FAIL, and the QE_Code indicates
RESPONSE SET the reason for the failure. If the command sent to
Opcode Mnemonic Description the programming executive is not identified, the
programming executive returns a NACK response.
0x1 PASS Command successfully
processed. 9.2.2 Last_Cmd FIELD
0x2 FAIL Command unsuccessfully The Last_Cmd is a 4-bit field in the first word of
processed. the response and indicates the command that the
0x3 NACK Command not known. programming executive processed. Since the
programming executive can only process one
command at a time, this field is technically not required.
However, it can be used to verify that the programming
executive correctly received the command that the
programmer transmitted.

dsPIC30F SMPS
9.2.3 QE_Code FIELD TABLE 9-3: QE_Code FOR NON-QUERY
The QE_Code is a byte in the first word of the COMMANDS
response. This byte is used to return data for query QE_Code Description
commands and error codes for all other commands.
0x0 No error
When the programming executive processes one of the
0x1 Verify failed
two query commands (QBLANK or QVER), the returned
opcode is always PASS and the QE_Code holds the 0x2 Other error
query response data. The format of the QE_Code for
both queries is shown in Table 9-2. 9.2.4 RESPONSE LENGTH
The response length indicates the length of the
TABLE 9-2: QE_Code FOR QUERIES programming executive’s response in 16-bit words.
This field includes the 2 words of the response header.
Query QE_Code
With the exception of the response for the READD and
QBLANK 0x0F = Code memory is NOT blank READP commands, the length of each response is only
0xF0 = Code memory is blank 2 words.
QVER 0xMN, where programming executive The response to the READD command is N + 2 words,
software version = M.N where N is the number of words specified in the READD
(i.e., 0x32, means software version 3.2) command.
When the programming executive processes any The response to the READP command uses the
command other than a query, the QE_Code represents packed instruction word format described in
an error code. Supported error codes are shown in Section 8.3 “Packed Data Format”. When reading
Table 9-3. If a command is successfully processed, the an odd number of program memory words (N odd),
returned QE_Code is set to 0x0, which indicates that the response to the READP command is (3 •
there is no error in the command processing. If the (N + 1)/2 + 2) words. When reading an even number
verification of the programming for the PROGD, PROGP of program memory words (N even), the response to
or PROGC command fails, the QE_Code is set to 0x1. the READP command is (3 • N/2 + 2) words.
For all other programming executive errors, the
QE_Code is 0x2.

dsPIC30F SMPS
10.0 DEVICE ID
The device ID region of memory can be used to
determine mask, variant and manufacturing
information about the chip. The device ID region is
2 x 16 bits and can be read using the READD command.
This region of memory is read-only and can also be
read when code protection is enabled.
Table 10-1 shows the device ID for each device, Table
10-2 shows the device ID registers and Table 10-3
describes the bit field of each register.
TABLE 10-1: DEVICE IDS

SMPS Device Mask Variant DEVID
dsPIC30F1010 0x010 0x4 0x0404
dsPIC30F2020 0x010 0x0 0x0400
dsPIC30F2023 0x010 0x3 0x0403
TABLE 10-2: dsPIC30F SMPS DEVICE ID REGISTERS

Bit
Address Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xFF0000 DEVID MASK<7:0> VARIANT<2:0>
0xFF0002 DEVREV PROC<3:0> REV<2:0> DOT<2:0>
TABLE 10-3: DEVICE ID BITS DESCRIPTION

MASK<7:0> DEVID Encodes the MASKSET ID of the device.
VARIANT<2:0> DEVID Encodes the VARIANT derived from MASKSET of the device.
PROC<3:0> DEVREV Encodes the process of the device.
REV<2:0> DEVREV Encodes the major revision number of the device.
DOT<2:0> DEVREV Encodes the minor revision number of the device.

dsPIC30F SMPS
11.0 ICSP™ MODE 11.2.1 SIX SERIAL INSTRUCTION
EXECUTION
11.1 ICSP Mode The SIX control code allows execution of dsPIC30F
SMPS assembly instructions. When the SIX code is
ICSP mode is a special programming protocol that
received, the CPU is suspended for 24 clock cycles as
allows you to read and write to dsPIC30F SMPS
the instruction is then clocked into the internal buffer.
memory. The ICSP mode is the second (and slower)
Once the instruction is shifted in, the state machine
method used to program the device. This mode also
allows it to be executed over the next four clock cycles.
has the ability to read the contents of executive
While the received instruction is executed, the state
memory to determine if the programming executive is
machine simultaneously shifts in the next 4-bit
present. This capability is accomplished by applying
command (see Figure 11-1).
control codes and instructions serially to the device
using pins PGC and PGD. Note 1: Coming out of Reset, the first 4-bit control
In ICSP mode, the system clock is taken from the PGC code is always forced to SIX, and a forced
pin, regardless of the device’s oscillator Configuration NOP instruction is executed by the CPU.
bits. All instructions are first shifted serially into an Once the forced SIX is clocked in, ICSP
internal buffer, then loaded into the instruction register operation resumes as normal (the next 24
and executed. No program fetching occurs from clock cycles load the first instruction word
internal memory. Instructions are fed in 24 bits at a to the CPU).
time. PGD is used to shift data in, and PGC is used as 2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
both the serial shift clock and the CPU execution clock. instructions must be followed by a NOP
Data is transmitted on the rising edge and latched on instruction.
the falling edge of PGC. For all data transmissions, the
11.2.2 REGOUT SERIAL INSTRUCTION
Least Significant bit (LSb) is transmitted first.
EXECUTION
Note 1: During ICSP operation, the operating
The REGOUT control code allows for data to be
frequency of PGC must not exceed
extracted from the device in ICSP mode. It is used to
5 MHz.
clock the contents of the VISI register out of the device
2: On the first serial word (in ICSP mode) to over the PGD pin. Once the REGOUT control code is
be shifted into the device following a received, eight clock cycles are required to process the
Reset, an additional 5 clocks must be command. During this time, the CPU is held idle. After
provided to the device on the PGC pin. these eight cycles, an additional 16 cycles are required
to clock the data out (see Figure 11-2).
11.2 ICSP Operation The REGOUT instruction is unique because the PGD
Upon entry into ICSP mode, the CPU is idle. Execution pin is an input when the control code is transmitted to
of the CPU is governed by an internal state machine. A the device. However, once the control code is
4-bit control code is clocked in using PGC and PGD, processed, the PGD pin becomes an output as the VISI
and this control code is used to command the CPU register is shifted out. After the contents of the VISI are
(see Table 11-1). shifted out, PGD becomes an input again as the state
machine holds the CPU idle until the next 4-bit control
The SIX control code is used to send instructions to the code is shifted in.
CPU for execution, while the REGOUT control code is
used to read data out of the device via the VISI register. Note: Once the contents of VISI are shifted out,
The operation details of ICSP mode are provided in the dsPIC® DSC device maintains PGD as
Section 11.2.1 “Six Serial Instruction Execution” an output until the first rising edge of the
and Section 11.2.2 “REGOUT Serial Instruction next clock is received.
Execution”.
TABLE 11-1: CPU CONTROL CODES IN

ICSP™ MODE
4-bit
Mnemonic Description
Control Code
0000b SIX Shift in 24-bit
instruction and execute.
0001b REGOUT Shift out the VISI
register.
0010b-1111b N/A Reserved.

dsPIC30F SMPS
FIGURE 11-1: SIX SERIAL EXECUTION
P1
1 2 3 4 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4
PGC
P4 P4a
P1b
P3
P1a
P2
PGD 0 0 0 0 LSB X X X X X X X X X X X X X X MSB 0 0 0 0
Execute PC-1, 24-bit Instruction Fetch Execute 24-bit Instruction,

Fetch SIX Control Code Fetch Next Control Code
PGD = Input
FIGURE 11-2: REGOUT SERIAL EXECUTION
1 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4
PGC
P4 P5 P4a
PGD 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0
Execute Previous Instruction, CPU Held In Idle Shift Out VISI Register <15:0> No Execution Takes Place,
Fetch REGOUT Control Code Fetch Next Control Code
PGD = Input PGD = Output PGD = Input
11.3 Entering ICSP Mode Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Figure 11-3 shows the three required steps to enter Program/Verify mode has to be maintained. An interval
the ICSP Program/Verify mode: of at least time P17 and P7 must elapse before
1. MCLR is briefly driven high then low. presenting data on PGD. Signals appearing on PGD
2. A 32-bit key sequence is clocked into PGD. before P7 has elapsed will not be interpreted as valid.
3. MCLR is then driven high within a specified On successful entry, the program memory can be
period of time and held. accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
The programming voltage applied to MCLR is VIH,
high-impedance state.
which is essentially VDD in the case of dsPIC30F
SMPS devices. There is no minimum time requirement
for holding at VIH. After VIH is removed, an interval of at
least P16 must elapse before presenting the key
sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 0x4D434851 in
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit (MSb) of the most significant nibble must be shifted
in first.

dsPIC30F SMPS
FIGURE 11-3: ENTERING ICSP™ MODE
P6
P12 P17 P7
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 0x4D434851
0 1 0 0 1 ... 0 0 0 1
PGD
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGC
P16 P2B
P2A
11.4 Flash Memory Programming in TABLE 11-2: NVMCON ERASE

ICSP Mode OPERATIONS
Programming in ICSP mode is described in NVMCON
Erase Operation
Section 11.4.1 “Programming Operations” through Value
Section 11.4.3 “Starting and Stopping a 0x407F Erases all code memory, data memory,
Programming Cycle”. executive memory and code-protect
Step-by-step procedures are described in bits (does not erase UNIT ID).
Section 11.5 “Bulk Erasing Program Memory” 0x406E Erases Boot Segment, General Seg-
through Section 11.11 “Reading the Application ID ment and Interrupt Vector Table, then
Word”. erase FBS and FGS Configuration
All programming operations must use serial execution, registers.
as described in Section 11.2 “ICSP Operation”. 0x404E Erases General Segment, then erase
FGS Configuration register.
11.4.1 PROGRAMMING OPERATIONS 0x4042 Erases General Segment without eras-
Flash memory write and erase operations are ing Interrupt Vector Table (when Boot
controlled by the NVMCON register. Programming is Segment is not defined).
performed by setting NVMCON to select the type of 0x4072 Erases all executive memory.
erase operation (Table 11-2) or write operation (Table
0x4071 Erases 1 row (32 instruction words)
11-3), writing a key sequence to enable the
from 1 panel of code memory.
programming and initiating the programming by setting
the WR control bit, NVMCON<15>.
TABLE 11-3: NVMCON WRITE
In ICSP mode, all programming operations are
OPERATIONS
externally timed. An external 2 msec delay must be
used between setting the WR control bit and clearing NVMCON
Write Operation
the WR control bit to complete the programming Value
operation.
0x4008 Writes 1 word to configuration
memory.
0x4001 Writes 1 row (32 instruction words) into
1 panel of program memory.

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11.4.2 UNLOCKING NVMCON FOR All erase and write cycles must be externally timed. An
PROGRAMMING external delay must be used between setting and
clearing the WR bit. Starting and stopping a
Writes to the WR bit (NVMCON<15>) are locked to
programming cycle is performed as follows:
prevent accidental programming from taking place.
Writing a key sequence to the NVMKEY register BSET NVMCON, #WR
unlocks the WR bit and allows it to be written to. The <Wait 2 msec>
unlock sequence is performed as follows: BCLR NVMCON, #WR
MOV #0x55, W8
MOV W8, NVMKEY 11.5 Bulk Erasing Program Memory
MOV #0xAA, W9 The procedure for bulk erasing program memory (all
MOV W9, NVMKEY code memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
Note: Any working register or working register
0x407F, unlocking NVMCON for erasing and then
pair can be used to write the unlock
executing the programming cycle.
sequence.
Table 11-4 shows the ICSP programming process for
11.4.3 STARTING AND STOPPING A bulk erasing program memory. This process includes
PROGRAMMING CYCLE the ICSP command code, which must be transmitted
(for each instruction) to the Least Significant bit first
Once the unlock key sequence has been written to the using the PGC and PGD pins (see Figure 11-1).
NVMKEY register, the WR bit (NVMCON<15>) is used
to start and stop an erase or write cycle. Setting the WR Note: Program memory must be erased before
bit initiates the programming cycle. Clearing the WR bit writing any data to program memory.
terminates the programming cycle.
TABLE 11-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASING PROGRAM MEMORY
Command Data
Description
(Binary) (Hex)
Step 1: Exit the Reset vector.
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Set the NVMCON to erase all Program Memory.
00000 2407FA MOV #0x407F, W10
0000 883B0A MOV W10, NVMCON
Step 3: Unlock the NVMCON for programming.
0000 200558 MOV #0x55, W8
0000 883B38 MOV W8, NVMKEY
0000 200AA9 MOV #0xAA, W9
Step 4: Initiate the erase cycle.
0000 A8E761 BSET NVMCON, #WR
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
— — Externally time 200 msec
0000 A9E761 BCLR NVMCON, #WR
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP

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11.6 Row Erasing Program Memory However, since this method is more time consuming
and does not clear the code-protect bits, it is not
Instead of using a Bulk Erase operation, each region of recommended in most cases.
memory can be individually erased by row. In this case,
all of the code memory, executive memory and Note 1: Program memory must be erased before
Configuration registers must be erased one row at a writing any data to program memory.
time. The procedure for erasing individual rows of 2: To erase the first two rows of program
program memory is quite different from the procedure memory (the Reset vector and Interrupt
for erasing the entire chip. This procedure is detailed in Vector Table), ICSP Mode must be exited
Table 11-5. If a Segment Erase operation is required, and re-entered after erasing each of
Step 3 must be modified with the appropriate NVMCON these two rows. Other rows of program
value as per Table 11-2. memory can only be erased if this
procedure is followed.
TABLE 11-5: SERIAL INSTRUCTION EXECUTION FOR ROW ERASING PROGRAM MEMORY
Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Initialize NVMADR and NVMADRU to erase code memory and initialize W7 for row address updates.
0000 EB0300 CLR W6
0000 883B16 MOV W6, NVMADR
0000 883B26 MOV W6, NVMADRU
0000 200407 MOV #0x40, W7
Step 3: Set NVMCON to erase 1 row of code memory.
0000 24071A MOV #0x4071, W10
Step 4: Unlock the NVMCON to erase 1 row of code memory.
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP

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TABLE 11-5: SERIAL INSTRUCTION EXECUTION FOR ROW ERASING PROGRAM MEMORY
Command Data
Description
(Binary) (Hex)
Step 6: Update the row address stored in NVMADRU:NVMADR. When W6 rolls over to 0x0, NVMADRU must be
incremented.
0000 430307 ADD W6, W7, W6
0000 AF0042 BTSC SR, #C
0000 EC2764 INC NVMADRU
Step 7: Reset device internal PC.
0000 040100 GOTO 0x100
0000 000000 NOP
Step 8: Repeat Steps 3-7 until all rows of code memory are erased.
Step 9: Initialize NVMADR and NVMADRU to erase executive memory and initialize W7 for row address updates.
0000 EB0300 CLR W6
0000 200807 MOV #0x80, W7
0000 883B27 MOV W7, NVMADRU
0000 200407 MOV #0x40, W7
Step 10: Set NVMCON to erase 1 row of executive memory.
0000 24071A MOV #0x4071, W10
Step 11: Unlock the NVMCON to erase 1 row of executive memory.
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
Step 13: Update the row address stored in NVMADR.
0000 430307 ADD W6, W7, W6
0000 040100 GOTO 0x100
0000 000000 NOP
Step 15: Repeat Steps 10-14 until all 24 rows of executive memory are erased.

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11.7 Writing Configuration Memory Configuration register. In Step 4, the TBLPAG register
is initialized to 0xF8 for writing to the Configuration
The FOSC, FWDT, FPOR and FICD registers are not registers. In Step 5, the value to write to each
erasable. It is recommended that all Configuration Configuration register (0xFFFF) is loaded to W6. In
registers be set to a default value after erasing program Step 6, the Configuration register data is written to the
memory. The FWDT, FPOR and FICD registers can be write latch using the TBLWTL instruction. In Steps 7 and
set to a default all ‘1’s value by programming 0xFFFF 8, the NVMCON is unlocked for programming and the
to each register. Since these registers contain programming cycle is initiated, as described in
unimplemented bits that read as ‘0’, the default values Section 11.4 “Flash Memory Programming in ICSP
shown in Table 11-6 will be read instead of 0xFFFF. Mode”. In Step 9, the internal PC is set to 0x100 as a
The recommended default FOSC value is 0xC100, safety measure to prevent the PC from incrementing
which selects the FRC clock oscillator setting. into unimplemented memory. Finally, Steps 3-9 are
The FBS and FGS Configuration registers are special repeated six times until all seven Configuration
since they enable code protection for the device. For registers are programmed.
security purposes, once the bits in these registers are
programmed to ‘0’ (to enable code protection), they TABLE 11-6: DEFAULT CONFIGURATION
can only be set back to ‘1’ by performing a Bulk Erase REGISTER VALUES
as described in Section 11.5 “Bulk Erasing Program
Memory”, or by using a Segment Erase operation. Address Register Default Value
Programming the FBS or FGS Configuration register 0xF80000 FBS 0x000F
bits from a ‘0’ to ‘1’ is not possible, but they can be 0xF80002 RESERVED 0x0000
programmed from a ‘1’ to a ‘0’ to enable code
protection. 0xF80004 FGS 0x0007
0xF80006 FOSCSEL 0x0003
Table 11-7 shows the ICSP programming details for
clearing the Configuration registers. In Step 1, the 0xF80008 FOSC 0x00E7
Reset vector is exited. In Step 2, the write pointer (W7) 0xF8000A FWDT 0x00DF
is loaded with 0x0000, which is the original destination 0xF8000C FPOR 0x0007
address (in TBLPAG 0xF8 of program memory). In
Step 3, the NVMCON is set to program one 0xF8000E FICD 0x0083
TABLE 11-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS

Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Initialize the write pointer (W7) for the TBLWT instruction.
0000 200007 MOV #0x0000, W7
Step 3: Set the NVMCON to program 1 Configuration register.
0000 24008A MOV #0x4008, W10
Step 4: Initialize the TBLPAG register.
0000 200F80 MOV #0xF8, W0
0000 880190 MOV W0, TBLPAG
Step 5: Load the Configuration register data to W6.
0000 2xxxx0 MOV #<CONFIG_VALUE>, W6

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TABLE 11-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS
Command Data
Description
(Binary) (Hex)
Step 6: Write the Configuration register data to the write latch and increment the write pointer.
0000 BB1B86 TBLWTL W6, [W7++]
0000 000000 NOP
0000 000000 NOP
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
Step 8: Initiate the write cycle.
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 040100 GOTO 0x100
0000 000000 NOP
Step 10: Repeat steps 3-9 until all seven Configuration registers are programmed.

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11.8 Writing Code Memory Since code memory is programmed 32 instruction
words at a time, Steps 4 and 5 are repeated eight times
The procedure for writing code memory is similar to the to load all the write latches (Step 6).
procedure for clearing the Configuration registers,
except that 32 instruction words are programmed at a After the write latches are loaded, programming is
time. To facilitate this operation, working registers initiated by writing to the NVMKEY and NVMCON
W0:W5 are used as temporary holding registers for the registers in Steps 7 and 8. In Step 9, the internal PC is
data to be programmed. reset to 0x100. This is a precautionary measure to
prevent the PC from incrementing into unimplemented
Table 11-8 shows the ICSP programming details, memory when large devices are being programmed.
including the serial pattern with the ICSP command Lastly, in Step 10, Steps 3-9 are repeated until all of
code, which must be transmitted Least Significant bit code memory is programmed.
first using the PGC and PGD pins (see Figure 11-1). In
Step 1, the Reset vector is exited. In Step 2, the
FIGURE 11-4: PACKED INSTRUCTION
NVMCON register is initialized for single panel
WORDS IN W0:W5
programming of code memory. In Step 3, the 24-bit
starting destination address for programming is loaded
into the TBLPAG register and W7 register. The upper 15 8 7 0
byte of the starting destination address is stored to
W0 lsw0
TBLPAG, while the lower 16 bits of the destination
address are stored to W7. W1 MSB1 MSB0
To minimize the programming time, the same packed W2 lsw1
instruction format that the programming executive uses W3 lsw2
is utilized (Figure 8-2). In Step 4, four packed
instruction words are stored to working registers
W4 MSB3 MSB2
W0:W5 using the MOV instruction and the read pointer W5 lsw3
W6 is initialized. The contents of W0:W5 holding the
packed instruction word data is shown in Figure 11-4.
In Step 5, eight TBLWT instructions are used to copy the
data from W0:W5 to the write latches of code memory.
TABLE 11-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY

Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Set the NVMCON to program 32 instruction words.
0000 24001A MOV #0x4001, W10
Step 3: Initialize the write pointer (W7) for TBLWT instruction.
0000 200xx0 MOV #<DestinationAddress23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx7 MOV #<DestinationAddress15:0>, W7
Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.
0000 2xxxx0 MOV #<LSW0>, W0
0000 2xxxx1 MOV #<MSB1:MSB0>, W1
0000 2xxxx4 MOV #<MSB3:MSB2>, W4

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TABLE 11-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 5: Set the read pointer (W6) and load the (next set of) write latches.
0000 EB0300 CLR W6
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 BBDBB6 TBLWTH.B [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BBEBB6 TBLWTH.B [W6++], [++W7]
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
Step 6: Repeat steps 3-5 eight times to load the write latches for 32 instructions.
Step 7: Unlock the NVMCON for writing.
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
Step 8: Initiate the write cycle.
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 040100 GOTO 0x100
0000 000000 NOP
Step 10: Repeat steps 3-9 until all code memory is programmed.

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11.9 Reading Code Memory To minimize the reading time, the packed instruction
word format that was utilized for writing is also used for
Reading from code memory is performed by executing reading (see Figure 11-4). In Step 3, the write pointer
a series of TBLRD instructions and clocking-out the W7 is initialized, and four instruction words are read
data using the REGOUT command. To ensure efficient from code memory and stored to working registers
execution and facilitate verification on the programmer, W0:W5. In Step 4, the four instruction words are
four instruction words are read from the device at a clocked out of the device from the VISI register using
time. the REGOUT command. In Step 5, the internal PC is
Table 11-9 shows the ICSP programming details for reset to 0x100, as a precautionary measure, to prevent
reading code memory. In Step 1, the Reset vector is the PC from incrementing into unimplemented memory
exited. In Step 2, the 24-bit starting source address for when large devices are being read. Lastly, in Step 6,
reading is loaded into the TBLPAG and W6 registers. Steps 3-5 are repeated until the desired amount of
The upper byte of the starting source address is stored code memory is read.
to TBLPAG, while the lower 16 bits of the source
address are stored to W6.
TABLE 11-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY

Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRD instruction.
0000 200xx0 MOV #<SourceAddress23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx6 MOV #<SourceAddress15:0>, W6
Step 3: Initialize the write pointer (W7) and store the next four locations of code memory to W0:W5.
0000 EB0380 CLR W7
0000 BA1B96 TBLRDL [W6], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BADBB6 TBLRDH.B [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BADBD6 TBLRDH.B [++W6], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BA1BB6 TBLRDL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BA1B96 TBLRDL [W6], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP

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TABLE 11-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 4: Output W0:W5 using the VISI register and REGOUT command.
0000 883C20 MOV W0, VISI
0000 000000 NOP
0001 <VISI> Clock out contents of VISI register
0000 000000 NOP
0000 883C21 MOV W1, VISI
0000 000000 NOP
0000 000000 NOP
0000 883C22 MOV W2, VISI
0000 000000 NOP
0000 000000 NOP
0000 883C23 MOV W3, VISI
0000 000000 NOP
0000 000000 NOP
0000 883C24 MOV W4, VISI
0000 000000 NOP
0000 000000 NOP
0000 883C25 MOV W5, VISI
0000 000000 NOP
0000 000000 NOP
Step 5: Reset the device internal PC.
0000 040100 GOTO 0x100
0000 000000 NOP
Step 6: Repeat steps 3-5 until all desired code memory is read.

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11.10 Reading Configuration Memory Table 11-10 shows the ICSP programming details for
reading all of the configuration memory. Note that the
The procedure for reading configuration memory is TBLPAG register is hard-coded to 0xF8 (the upper byte
similar to the procedure for reading code memory, address of configuration memory), and the read pointer
except that 16-bit data words are read instead of 24-bit W6 is initialized to 0x0000.
words. Since there are seven Configuration registers,
they are read one register at a time.
TABLE 11-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY
Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Initialize TBLPAG, and the read pointer (W6) and the write pointer (W7) for TBLRD instruction.
0000 200F80 MOV #0xF8, W0
0000 880190 MOV W0, TBLPAG
0000 EB0300 CLR W6
0000 EB0380 CLR W7
Step 3: Read the Configuration register and write it to the VISI register (located at 0x784).
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 883C20 MOV W0, VISI
0000 000000 NOP
Step 4: Output the VISI register using the REGOUT command.
0000 000000 NOP
0000 040100 GOTO 0x100
0000 000000 NOP
Step 6: Repeat steps 3-5 until all desired code memory is read.

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11.11 Reading the Application ID Word 11.12 Exiting ICSP Mode
The application ID word is stored at address 0x8005BE To exit from Program/Verify mode, remove VIH from
in executive code memory. To read this memory MCLR, as shown in Figure 11-5. The only requirement
location, you must use the SIX control code to move for exit is that an interval P9b should elapse between
this program memory location to the VISI register. The the last clock and program signals on PGC and PGD
REGOUT control code must then be used to clock the before removing VIH.
contents of the VISI register out of the device. The
corresponding control and instruction codes that must FIGURE 11-5: EXITING ICSP™ MODE
be serially transmitted to the device to perform this
operation are shown in Table 11-11. P9b P15
Once the programmer has clocked-out the application MCLR VIH
ID word, it must be inspected. If the application ID has
the value 0xBB, the programming executive is resident
in memory and the device can be programmed using VDD
the mechanism described in Section 5.0 “Device
Programming”. However, if the application ID has any PGD
VIH
other value, the programming executive is not resident
in memory. It must be loaded to memory before the
device can be programmed. The procedure for loading PGC
the programming executive to memory is described in
Section 12.0 “Programming the Programming
PGD = Input
Executive to Memory”.
TABLE 11-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD
Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 205BE0 MOV #0x5BE, W0
0000 207841 MOV VISI, W1
0000 BA0890 TBLRDL [W0], [W1]
0000 000000 NOP
0000 000000 NOP
Step 3: Output the VISI register using the REGOUT command.
0001 <VISI> Clock out contents of the VISI register
0000 000000 NOP

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12.0 PROGRAMMING THE Storing the programming executive to executive
memory is similar to normal programming of code
PROGRAMMING EXECUTIVE
memory. Namely, the executive memory must first be
TO MEMORY erased, and then the programming executive must be
programmed 32 words at a time. This control flow is
12.1 Overview summarized in Table 12-1.
If it is determined that the programming executive does
not reside in executive memory (as described in
Section 4.0 “Confirming The Contents of Executive
Memory”), it must be programmed into executive
memory using ICSP and the techniques described in
Section 11.0 “ICSP™ Mode”.
TABLE 12-1: PROGRAMMING THE PROGRAMMING EXECUTIVE

Command Data
Description
(Binary) (Hex)
Step 1: Exit the Reset vector and erase executive memory.
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
Step 2: Initialize the NVMCON to erase executive memory.
0000 24072A MOV #0x4072, W10
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
0000 A8E761 BSET NVMCON, #15
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 A9E761 BCLR NVMCON, #15
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
Step 5: Initialize the NVMCON to program 32 instruction words.
0000 24001A MOV #0x4001, W10
Step 6: Initialize TBLPAG and the write pointer (W7).
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 EB0380 CLR W7
0000 000000 NOP
0000 000000 NOP

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TABLE 12-1: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 7: Load W0:W5 with the next 4 words of packed programming executive code and initialize W6 for
programming. Programming starts from the base of executive memory (0x800000) using W6 as a read
pointer and W7 as a write pointer.
0000 2<LSW0>0 MOV #<LSW0>, W0
0000 2<MSB1:MSB0>1 MOV #<MSB1:MSB0>, W1
0000 2<LSW1>2 MOV #<LSW1>, W2
0000 2<LSW2>3 MOV #<LSW2>, W3
0000 2<MSB3:MSB2>4 MOV #<MSB3:MSB2>, W4
0000 2<LSW3>5 MOV #<LSW3>, W5
Step 8: Set the read pointer (W6) and load the (next four write) latches.
0000 EB0300 CLR W6
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BB0BB6 TBLWTL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BB1BB6 TBLWTL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
Step 9: Repeat Steps 7-8 eight times to load the write latches for the 32 instructions.
0000 200558 MOV #0x55, W8
0000 200AA9 MOV #0xAA, W9
Step 11: Initiate the programming cycle.
0000 A8E761 BSET NVMCON, #15
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 A9E761 BCLR NVMCON, #15
0000 000000 NOP
0000 000000 NOP
0000 040100 GOTO 0x100
0000 000000 NOP
Step 13: Repeat Steps 7-12 until all 23 rows of executive memory are programmed.

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12.2 Programming Verification Reading the contents of executive memory can be
performed using the similar technique described in
After the programming executive has been Section 11.9 “Reading Code Memory”. A procedure
programmed to executive memory using ICSP, it must for reading executive memory is shown in Table 12-2.
be verified. Verification is performed by reading out the Note that, in Step 2, the TBLPAG register is set to 0x80
contents of executive memory and comparing it with such that executive memory may be read.
the image of the programming executive stored in the
programmer.
TABLE 12-2: READING EXECUTIVE MEMORY

Command Data
Description
(Binary) (Hex)
0000 040100 GOTO 0x100
0000 040100 GOTO 0x100
0000 000000 NOP
0000 200800 MOV #0x80, W0
0000 880190 MOV W0, TBLPAG
0000 EB0300 CLR W6
Step 3: Initialize the write pointer (W7), and store the next four locations of executive memory to W0:W5.
0000 EB0380 CLR W7
0000 BA1B96 TBLRDL [W6], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BA1BB6 TBLRDL [W6++], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 BA1B96 TBLRDL [W6], [W7++]
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 000000 NOP
0000 BA1BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP

dsPIC30F SMPS
TABLE 12-2: READING EXECUTIVE MEMORY (CONTINUED)
Command Data
Description
(Binary) (Hex)
Step 4: Output W0:W5 using the VISI register and REGOUT command.
0000 883C20 MOV W0, VISI
0000 000000 NOP
0001 — Clock out contents of VISI register
0000 883C21 MOV W1, VISI
0000 000000 NOP
0000 883C22 MOV W2, VISI
0000 000000 NOP
0000 883C23 MOV W3, VISI
0000 000000 NOP
0000 883C24 MOV W4, VISI
0000 000000 NOP
0000 883C25 MOV W5, VISI
0000 000000 NOP
0000 040100 GOTO 0x100
0000 000000 NOP
Step 6: Repeat Steps 3-5 until all 736 instruction words of executive memory are read.

dsPIC30F SMPS
13.0 AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 13-1 lists AC/DC characteristics and timing
requirements.
TABLE 13-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS

Standard Operating Conditions
AC/DC Characteristics (unless otherwise stated)
Operating Temperature: 25°C is recommended
Param.
Sym Characteristic Min Max Units Conditions
No.
D110 VIHH Programming Voltage on MCLR 0.8 VDD VDD V

D112 IPP Programming Current on MCLR — 5 mA
D113 IDDP Supply Current during programming — 30 mA Row Erase
Program
memory
— 30 mA Bulk Erase
D001 VDD Supply voltage 3.0 5.5 V
D002 VDDBULK Supply voltage for Bulk Erase 3.0 5.5 V
programming
D031 VIL Input Low Voltage VSS 0.2 VSS V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA
D012 CIO Capacitive Loading on I/O Pin (PGD) — 50 pF To meet AC
specifications
P1 TPGC Serial Clock (PGC) Period 100 — ns
P1A TPGCL Serial Clock (PGC) Low Time 40 — ns
P1B TPGCH Serial Clock (PGC) High Time 40 — ns
P2 TSET1 Input Data Setup Time to Serial Clock ↓ 15 — ns
P3 THLD1 Input Data Hold Time from PGC ↓ 15 — ns
P4 TDLY1 Delay between 4-bit Command and 40 — ns
Command Operand
P4A TDLY1A Delay between 4-bit Command Operand 40 — ns
and Next 4-bit Command
P5 TDLY2 Delay between Last PGC ↓ of Command 20 — ns
Byte to First PGC ↑ of Read of Data Word
P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns
P7 THLD2 Input Data Hold Time from MCLR ↑ 500 — ns
P8 TDLY3 Delay between Last PGC ↓ of Command 20 — ms
Byte to PGD ↑ by Programming
Executive
P9a TDLY4 Programming Executive Command 10 — ms
Processing Time
P9b TDLY5 Delay between PGD ↓ by Programming 15 — ms
Executive to PGD Released by
Programming Executive
P10 TDLY6 PGC Low Time After Programming 400 — ns

dsPIC30F SMPS
TABLE 13-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions
AC/DC Characteristics (unless otherwise stated)
Operating Temperature: 25°C is recommended
Param.
Sym Characteristic Min Max Units Conditions
No.
P11 TDLY7 Delay to allow Bulk Erase to Occur 200 — ms
P12 TR MCLR Rise Time to Enter ICSP mode — 1.0 ms
P13 TVALID Data Out Valid from PGC ↑ 10 — ns
P14 TDLY8 Delay between Last PGC ↓ and MCLR ↓ 0 — s
P15 THLD3 MCLR ↓ to VDD ↓ — 100 ns
P16 TKEY1 Delay from First MCLR ↓ to First PGC ↑ 40 — ns
for Key Sequence on PGD
P17 TKEY2 Delay from Last PGC ↓ for Key Sequence 40 — ns
on PGD to Second MCLR ↑
P18 TPROG Programming cycle time 1 4 ms ICSP™ mode
P19 TERA Erase cycle time 1 4 ms ICSP mode

APPENDIX A: HEX FILE FORMAT Because the Intel hex file format is byte-oriented, and
the 16-bit program counter is not, program memory
Flash programmers process the standard HEX format sections require special treatment. Each 24-bit
used by the Microchip development tools. The format program word is extended to 32 bits by inserting a so-
supported is the Intel® HEX 32 Format (INHX32). called “phantom byte”. Each program memory
Please refer to Appendix A in the “MPASM™ address is multiplied by 2 to yield a byte address.
Assembler, MPLINK™ Linker, MPLIB™ Object
As an example, a section that is located at 0x100 in
Librarian User’s Guide” (DS33014) for more
program memory will be represented in the hex file as
information about hex file formats.
0x200.
The basic format of the hex file is:
The hex file will be produced with the following
:BBAAAATTHHHH...HHHHCC contents:
Each data record begins with a 9-character prefix and :020000040000fa
always ends with a 2-character checksum. All records
:040200003322110096
begin with ':' regardless of the format. The individual
elements are described below. :00000001FF
• BB - is a two-digit hexadecimal byte count Notice that the data record (line 2) has a load address
representing the number of data bytes that of 0200, while the source code specified address
appear on the line. Divide this number by two to 0x100. Note also that the data is represented in “little-
get the number of words per line. endian” format, meaning the least significant byte
• AAAA - is a four-digit hexadecimal address appears first. The phantom byte appears last, just
representing the starting address of the data before the checksum.
record. Format is high byte first followed by low
byte. The address is doubled because this format
only supports 8-bits. Divide the value by two to
find the real device address.
• TT - is a two-digit record type that will be '00' for
data records, '01' for end-of-file records and '04'
for extended-address record.
• HHHH - is a four-digit hexadecimal data word.
Format is low byte followed by high byte. There
will be BB/2 data words following TT.
• CC - is a two-digit hexadecimal checksum that is
the two's complement of the sum of all the
preceding bytes in the line record.

APPENDIX B: REVISION HISTORY • Replaced the number 9 with the word seven in the
last sentence of the last paragraph of
Revision A (February 2007) Section 11.7 “Writing Configuration Memory”.
• Initial release of this document. • Changed the max values for parameters TPROG
Revision B (September 2007) and TERA in Table 13-11.
• Added Appendix A: “Hex File Format”.
• Updated paragraph in Section 2.2 “Pins Used
During Programming” to include reference to
location of complete pin diagrams
• Removed all pin diagrams
• Modified the first sentence in Section 5.7.1
“Overview” to read as follows: The dsPIC30F
SMPS has Configuration bits stored in seven 16-
bit registers. Bold text denotes the change.
• Added the following note after the second
paragraph in Section 5.7.1 “Overview”:
Note: If user software performs an erase opera-
tion on the configuration fuse, it must be
followed by a write operation to this fuse
with the desired value, even if the desired
value is the same as the state of the
erased fuse.
• Added the following sentence to the end of the
paragraph in Section 5.7.5 “User Unit ID”:
Programming the UNIT ID is similar to
programming the Programming Executive (see
Section 12.0 “Programming the Programming
Executive to Memory” for details).
• Updated instructions in the following tables:
- Table 11-4 (removed two NOPs before the
GOTO instruction in Step 1 and added two
NOPs after BSET and BCLR in Step 12)
GOTO instruction in Step 1 and added two
NOPs after BSET and BCLR in Step 5 and
Step 12)
GOTO instruction in Step 1, changed BB1B96
to BB1B86 in Step 6, added two NOPs after
BSET and BCLR in Step 8, and changed 9 to
seven in Step 10)
GOTO instruction in Step 1)
- Table 12-1 (removed two NOPs before the GOTO
instruction in Step 1 and added two NOPs after
BSET and BCLR in Step 4 and Step 11)

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt
MICROCHIP MAKES NO REPRESENTATIONS OR
are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
QUALITY, PERFORMANCE, MERCHANTABILITY OR Embedded Control Solutions Company are registered
FITNESS FOR PURPOSE. Microchip disclaims all liability trademarks of Microchip Technology Incorporated in the
arising from this information and its use. Use of Microchip U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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dsPIC30F SMPS

dsPIC30F SMPS Flash Programming Specification

2.0 PROGRAMMING OVERVIEW Programming

© 2007 Microchip Technology Inc. DS70284B-page 1

TABLE 2-2: PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING)

MCLR MCLR P Programming Enable

DS70284B-page 2 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 3

DS70284B-page 4 © 2007 Microchip Technology Inc.

5.1 Overview of the Programming Start

TABLE 5-1: COMMAND SET SUMMARY Program config

A high-level overview of the programming process is Exit Enhanced

© 2007 Microchip Technology Inc. DS70284B-page 5

FIGURE 5-2: ENTERING ENHANCED ICSP™ MODE

5.3 Exiting Enhanced ICSP Mode 5.4 Chip Erase

DS70284B-page 6 © 2007 Microchip Technology Inc.

5.6 Code Memory Programming FIGURE 5-4: FLOWCHART FOR

© 2007 Microchip Technology Inc. DS70284B-page 7

TABLE 5-3: dsPIC30F SMPS FAMILY DEVICE CONFIGURATION REGISTER MAP

TABLE 5-4: dsPIC30F SMPS DEVICE CONFIGURATION BITS DESCRIPTION

DS70284B-page 8 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 9

DS70284B-page 10 © 2007 Microchip Technology Inc.

Note: If any of the code-protect bits in FBS or

© 2007 Microchip Technology Inc. DS70284B-page 11

DS70284B-page 12 © 2007 Microchip Technology Inc.

TABLE 6-2: CHECKSUM COMPUTATION

© 2007 Microchip Technology Inc. DS70284B-page 13

DS70284B-page 14 © 2007 Microchip Technology Inc.

Host Transmits Programming Executive

PGD MSB X X X LSB 1 0 MSB X X X LSB MSB X X X LSB

P8 P9a P9b P10 P11

PGC = Input PGC = Input (Idle) PGC = Input

© 2007 Microchip Technology Inc. DS70284B-page 15

Note: When the number of instruction words

DS70284B-page 16 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 17

Note: Reading unimplemented memory will

DS70284B-page 18 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 19

DS70284B-page 20 © 2007 Microchip Technology Inc.

Field Description Field Description

Note: The QBLANK command does not check

© 2007 Microchip Technology Inc. DS70284B-page 21

DS70284B-page 22 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 23

TABLE 10-1: DEVICE IDS

TABLE 10-2: dsPIC30F SMPS DEVICE ID REGISTERS

TABLE 10-3: DEVICE ID BITS DESCRIPTION

DS70284B-page 24 © 2007 Microchip Technology Inc.

TABLE 11-1: CPU CONTROL CODES IN

© 2007 Microchip Technology Inc. DS70284B-page 25

Execute PC-1, 24-bit Instruction Fetch Execute 24-bit Instruction,

FIGURE 11-2: REGOUT SERIAL EXECUTION

PGD 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0

PGD = Input PGD = Output PGD = Input

DS70284B-page 26 © 2007 Microchip Technology Inc.

11.4 Flash Memory Programming in TABLE 11-2: NVMCON ERASE

© 2007 Microchip Technology Inc. DS70284B-page 27

DS70284B-page 28 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS70284B-page 29

DS70284B-page 30 © 2007 Microchip Technology Inc.

TABLE 11-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS