Logic Gates NAND NOR

Digital Electronics
Topic 2:
Logic Gates
FLB 20203
DIGITAL SYSTEMS Introduction to Logic Gates 1
Logic Gates
The Inverter
The AND Gate
The OR Gate
The NAND Gate
The NOR Gate
The XOR Gate
The XNOR Gate
Drawing Logic Circuit
Analysing Logic Circuit
Propagation Delay
FLB 20203
Universal Gates: NAND and NOR
NAND Gate
NOR Gate
Implementation using NAND Gates
Implementation using NOR Gates
Implementation of SOP Expressions
Implementation of POS Expressions
Positive and Negative Logic
Integrated Circuit Logic Families
FLB 20203
Logic Gates
Gate Symbols Symbol set 1 Symbol set 2
(ANSI/IEEE Standard 91-1984)
a a
AND a.b & a.b
b b
a a
OR a+b ≥1 a+b
b b
NOT a a' a 1 a'
a a
(a.b)' & (a.b)'
NAND b b
a a
NOR (a+b)' ≥1 (a+b)'
b b
a a
EXCLUSIVE OR a⊕b =1 a⊕b
b b
FLB 20203
Logic Gates: The Inverter
The Inverter
A A'
A A' A A' 0 1
1 0
Application of the inverter: complement.
Binary number
1 1 0 1 0 0 0 1
0 0 1 0 1 1 1 0
1’s Complement
FLB 20203
Logic Gates: The AND Gate
The AND Gate
A A &
A.B A.B
B B
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
FLB 20203
Logic Gates: The AND Gate
Application of the AND Gate
1 sec
A A
Counter
Enable
Enable
1 sec
Register,
Reset to zero decode
between and
frequency
Enable pulses
display
FLB 20203
Logic Gates: The OR Gate
The OR Gate
A A ≥1
A+B A+B
B B
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
FLB 20203
Logic Gates: The NAND Gate
The NAND Gate

A
(A.B)' ≡ A
(A.B)'
A &
(A.B)'
B B B
A B (A.B)'
0 0 1
0 1 1 ≡
1 0 1
1 1 0 NAND Negative-OR
FLB 20203
Logic Gates: The NOR Gate
The NOR Gate

A
B
(A+B)' ≡ A
(A+B)'
A
B
≥1
(A+B)'
B
A B (A+B)'
0 0 1
0 1 0 ≡
1 0 0
1 1 0 NOR Negative-AND
FLB 20203
Logic Gates: The XOR Gate
The XOR Gate
A A =1
A⊕B A⊕B
B B
A B A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
FLB 20203
Logic Gates: The XNOR Gate
The XNOR Gate
A A =1
(A ⊕ B)' (A ⊕ B)'
B B
A B (A ⊕ B) '
0 0 1
0 1 0
1 0 0
1 1 1
FLB 20203
When a Boolean expression is provided, we can easily draw
the logic circuit.
Examples:
(i) F1 = xyz' (note the use of a 3-input AND gate)
x
y F1
z z'
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(ii) F2 = x + y'z (can assume that variables and their
complements are available)
x
F2
y'
z y'z
(iii) F3 = xy' + x'z

x xy'
y'
F3
x'
z x'z
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Analysing Logic Circuit
When a logic circuit is provided, we can analyse the circuit to

obtain the logic expression.
Example: What is the Boolean expression of F4?
A' A'B'
B' A'B'+C (A'B'+C)'
F4
C
F4 = (A'B'+C)' = (A+B).C'
FLB 20203
Propagation Delay
Every logic gate experiences some delay (though very small)

in propagating signals forward.
This delay is called Gate (Propagation) Delay.
Formally, it is the average transition time taken for the output
signal of the gate to change in response to changes in the
input signals.
Three different propagation delay times associated with a
logic gate:
tPHL: output changing from the High level to Low level
tPLH: output changing from the Low level to High level
tPD=(tPLH + tPHL)/2 (average propagation delay)
FLB 20203
Propagation Delay
Input Output
H
Input
L
H
Output
L
tPHL tPLH
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Propagation Delay
A B C
Ideally, no In reality, output signals

normally lag behind input
delay:
signals:
1 1
Signal for A Signal for A
0 0
1 1
0 Signal for B 0 Signal for B
1 1
Signal for C Signal for C
0 0
time time
FLB 20203
Calculation of Circuit Delays
Amount of propagation delay per gate depends on:

(i) gate type (AND, OR, NOT, etc)
(ii) transistor technology used (TTL,ECL,CMOS etc),
(iii) miniaturisation (SSI, MSI, LSI, VLSI)
To simplify matters, one can assume
(i) an average delay time per gate, or
(ii) an average delay time per gate-type.
Propagation delay of logic circuit
= longest time it takes for the input signal(s) to propagate to the
output(s).
= earliest time for output signal(s) to stabilise, given that input
signals are stable at time 0.
FLB 20203
In general, given a logic gate with delay, t.

t1
t2 Logic
: : Gate
tn max (t1, t2, ..., tn ) + t
If inputs are stable at times t1,t2,..,tn, respectively; then the

earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t
To calculate the delays of all outputs of a combinational

circuit, repeat above rule for all gates.
FLB 20203
As a simple example, consider the full adder circuit where all

inputs are available at time 0. (Assume each gate has delay
t.)
X 0 max(0,0)+t = t
max(t,0)+t = 2t
Y 0 S
t 2t max(t,2t)+t = 3t
C
0
Z
where outputs S and C, experience delays

of 2t and 3t, respectively.
FLB 20203
Universal Gates: NAND and NOR
AND/OR/NOT gates are sufficient for building any Boolean
functions.
We call the set {AND, OR, NOT} a complete set of logic.
However, other gates are also used because:
(i) usefulness
(ii) economical on transistors
(iii) self-sufficient
NAND/NOR: economical, self-sufficient

XOR: useful (e.g. parity bit generation)
FLB 20203
NAND Gate
NAND gate is self-sufficient (can build any logic circuit with

it).
Therefore, {NAND} is also a complete set of logic.
Can be used to implement AND/OR/NOT.
Implementing an inverter using NAND gate:
x x'
(x.x)' = x' (T1: idempotency)
FLB 20203
NAND Gate
Implementing AND using NAND gates:
(x.y)'
x
x.y
y
((xy)'(xy)')' = ((xy)')' idempotency
= (xy) involution
Implementing OR using NAND gates:

x'
x ((xx)'(yy)')' = (x'y')' idempotency
x+y = x''+y'' DeMorgan
= x+y involution
y
y'
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NOR Gate
NOR gate is also self-sufficient.

Therefore, {NOR} is also a complete set of logic
Can be used to implement AND/OR/NOT.
Implementing an inverter using NOR gate:
x x'
(x+x)' = x' (T1: idempotency)
FLB 20203
NOR Gate
Implementing AND using NOR gates:
x'
x
x.y
((x+x)'+(y+y)')'=(x'+y')' idempotency
y
y' = x''.y'' DeMorgan
= x.y involution
Implementing OR using NOR gates:

(x+y)'
x
x+y
y
((x+y)'+(x+y)')' = ((x+y)')' idempotency
= (x+y) involution
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Implementation using NAND gates
Possible to implement any Boolean expression using NAND
gates.
Procedure:
(i) Obtain sum-of-products Boolean expression:
e.g. F3 = xy'+x'z
(ii) Use DeMorgan theorem to obtain expression
using 2-level NAND gates
e.g. F3 = xy'+x'z
= (xy'+x'z)' ' involution
= ((xy')' . (x'z)')' DeMorgan
FLB 20203
Implementation using NAND gates
x (xy')'
y'
F3
x'
z (x'z)'
F3 = ((xy')'.(x'z)') ' = xy' + x'z
FLB 20203
Implementation using NOR gates
Possible to implement any Boolean expression using NOR
gates.
Procedure:
(i) Obtain product-of-sums Boolean expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain expression
using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')' DeMorgan
FLB 20203
Implementation using NOR gates
x (x+y')'
y'
F6
x'
z (x'+z)'
F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)
FLB 20203
Sum-of-Products expressions can be implemented using:
2-level AND-OR logic circuits
2-level NAND logic circuits
AND-OR logic circuit
A
B
F = AB + CD + E
C
F
D
FLB 20203
NAND-NAND circuit (by circuit A
transformation) B
a) add double bubbles C
F
b) change OR-with- D
inverted-inputs to NAND E
& bubbles at inputs to
their complements
A
B
C
F
D
E'
FLB 20203
Product-of-Sums expressions can be implemented using:
2-level OR-AND logic circuits
2-level NOR logic circuits
OR-AND logic circuit
A
B
G = (A+B).(C+D).E
C
G
D
FLB 20203
NOR-NOR circuit (by circuit A

transformation): B
a) add double bubbles C
G
D
b) changed AND-with-
inverted-inputs to NOR E
& bubbles at inputs to
their complements
A
B
C
G
D
E'
FLB 20203
Positive & Negative Logic
In logic gates, usually:
H (high voltage, 5V) = 1
L (low voltage, 0V) = 0
This convention – positive logic.
However, the reverse convention, negative logic possible:
H (high voltage) = 0
L (low voltage) = 1
Depending on convention, same gate may denote different
Boolean function.
FLB 20203
A signal that is set to logic 1 is said to be asserted, or active,

or true.
A signal that is set to logic 0 is said to be deasserted, or
negated, or false.
Active-high signal names are usually written in
uncomplemented form.
Active-low signal names are usually written in complemented
form.
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Positive logic:
Active High:
Enable 0: Disabled
1: Enabled
Negative logic:
Active Low:
Enable 0: Enabled
1: Disabled
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Some digital integrated circuit families: TTL, CMOS, ECL.

TTL: Transistor-Transistor Logic.
Uses bipolar junction transistors
Consists of a series of logic circuits: standard TTL, low-power
TTL, Schottky TTL, low-power Schottky TTL, advanced
Schottky TTL, etc.
FLB 20203
TTL Series Prefix Designation Example of Device
Standard TTL 54 or 74 7400 (quad NAND gates)
Low-power TTL 54L or 74L 74L00 (quad NAND gates)
Schottky TTL 54S or 74S 74S00 (quad NAND gates)
Low-power 54LS or 74LS 74LS00 (quad NAND gates)

Schottky TTL
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CMOS: Complementary Metal-Oxide Semiconductor.

Uses field-effect transistors
ECL: Emitter Coupled Logic.

Uses bipolar circuit technology.
Has fastest switching speed but high power consumption.
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Performance characteristics
Propagation delay time.
Power dissipation.
Fan-out: Fan-out of a gate is the maximum number of inputs
that the gate can drive.
Speed-power product (SPP): product of the propagation
delay time and the power dissipation.
FLB 20203
Summary
Logic Gates Drawing Logic Analysing
Circuit Logic Circuit
AND, NAND Given a Boolean Given a circuit, find

OR, expression, draw the the function.
NOT NOR circuit.
Implementation Positive and

Implementation of a of SOP and POS Negative Logic
Boolean expression Expressions
using these
Universal gates. Concept of Minterm
and Maxterm
FLB 20203
End of file
FLB 20203

Logic Gates NAND NOR

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Digital Electronics

NOT a a' a 1 a'

 The AND Gate

 The NAND Gate

 The NOR Gate

 The XOR Gate

 The XNOR Gate

(iii) F3 = xy' + x'z

 When a logic circuit is provided, we can analyse the circuit to

 Every logic gate experiences some delay (though very small)

 Ideally, no  In reality, output signals

 Amount of propagation delay per gate depends on:

 In general, given a logic gate with delay, t.

If inputs are stable at times t1,t2,..,tn, respectively; then the

 To calculate the delays of all outputs of a combinational

 As a simple example, consider the full adder circuit where all

where outputs S and C, experience delays

NAND/NOR: economical, self-sufficient

 NAND gate is self-sufficient (can build any logic circuit with

(x.x)' = x' (T1: idempotency)

 Implementing OR using NAND gates:

 NOR gate is also self-sufficient.

(x+x)' = x' (T1: idempotency)

 Implementing OR using NOR gates:

F3 = ((xy')'.(x'z)') ' = xy' + x'z

 AND-OR logic circuit

 OR-AND logic circuit

 NOR-NOR circuit (by circuit A

 A signal that is set to logic 1 is said to be asserted, or active,

 Some digital integrated circuit families: TTL, CMOS, ECL.

TTL Series Prefix Designation Example of Device

Standard TTL 54 or 74 7400 (quad NAND gates)

Low-power TTL 54L or 74L 74L00 (quad NAND gates)

Schottky TTL 54S or 74S 74S00 (quad NAND gates)

Low-power 54LS or 74LS 74LS00 (quad NAND gates)

 CMOS: Complementary Metal-Oxide Semiconductor.

 ECL: Emitter Coupled Logic.

AND, NAND Given a Boolean Given a circuit, find

Implementation Positive and

Potrebbero piacerti anche

The AND Gate

The NAND Gate

The NOR Gate

The XOR Gate

The XNOR Gate

When a logic circuit is provided, we can analyse the circuit to

Every logic gate experiences some delay (though very small)

Ideally, no In reality, output signals

Amount of propagation delay per gate depends on:

In general, given a logic gate with delay, t.

To calculate the delays of all outputs of a combinational

As a simple example, consider the full adder circuit where all

NAND gate is self-sufficient (can build any logic circuit with

Implementing OR using NAND gates:

NOR gate is also self-sufficient.

Implementing OR using NOR gates:

AND-OR logic circuit

OR-AND logic circuit

NOR-NOR circuit (by circuit A

A signal that is set to logic 1 is said to be asserted, or active,

Some digital integrated circuit families: TTL, CMOS, ECL.

CMOS: Complementary Metal-Oxide Semiconductor.

ECL: Emitter Coupled Logic.