BSC3153 Nokia GSM/EDGE BSS, Rel. BSS13, BSC and TCSM, Rel. S13, Product Documentation, v.1

BSC3153
Nokia GSM/EDGE BSS, Rel. BSS13, BSC and

TCSM, Rel. S13, Product Documentation, v.1
AS7-C
DN02176023 # Nokia Siemens Networks 1 (38)

Issue 1-4 en
AS7-C
The information in this document is subject to change without notice and describes only the
product defined in the introduction of this documentation. This documentation is intended for the
use of Nokia Siemens Networks customers only for the purposes of the agreement under which
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and the customer assumes full responsibility when using it. Nokia Siemens Networks welcomes
customer comments as part of the process of continuous development and improvement of the
documentation.
The information or statements given in this documentation concerning the suitability, capacity, or
performance of the mentioned hardware or software products are given “as is” and all liability
arising in connection with such hardware or software products shall be defined conclusively and
finally in a separate agreement between Nokia Siemens Networks and the customer. However,
Nokia Siemens Networks has made all reasonable efforts to ensure that the instructions
contained in the document are adequate and free of material errors and omissions. Nokia
Siemens Networks will, if deemed necessary by Nokia Siemens Networks, explain issues which
may not be covered by the document.
Nokia Siemens Networks will correct errors in this documentation as soon as possible. IN NO
EVENT WILL NOKIA SIEMENS NETWORKS BE LIABLE FOR ERRORS IN THIS
DOCUMENTATION OR FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO SPECIAL,
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Other product names mentioned in this document may be trademarks of their respective owners,
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Copyright © Nokia Siemens Networks 2008. All rights reserved.
2 (38) # Nokia Siemens Networks DN02176023

Issue 1-4 en
Contents
Contents
Contents 3
List of tables 4
List of figures 5
Summary of changes 7
1 AS7-C overview 9
2 Capacity and performance of AS7-C 11
3 Structure of AS7-C 13
3.1 Mechanical structure 13
3.2 Logical structure 13
3.3 Interfaces 19
4 Operation of AS7-C 25
5 Power consumption of AS7-C 29
6 AS7-C C105007 31
7 Connector maps of AS7-C 35

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AS7-C
List of tables
Table 1. I/O Bridge address ranges 17

Table 2. Interface signals of the AS7-C 20
Table 3. AS7-C front panel LED indicators 26
Table 4. Power Consumption of AS7-C 29
Table 5. SW1 switch settings. 32
Table 6. Interchangeability code settings of AS7-C 32
Table 7. P5 connector 35

Issue 1-4 en
List of figures
List of figures
Figure 1. Operational environment of the AS7-C plug-in unit. 10

Figure 2. Block diagram of the AS7-C plug-in unit. 14
Figure 3. Interfaces of the AS7–C. 20
Figure 4. AS7-C front panel. 26
Figure 5. DIP switches of the plug-in unit AS7-C 31

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AS7-C

Issue 1-4 en
Summary of changes
Summary of changes
Changes between document issues are cumulative. Therefore, the latest

document issue contains all changes made to previous issues.
Changes between issues 1-3 and 1-4
Ethernet interface information removed.
Added a table for setting the SW1 interchangeability switch.
Section AS7-C C105007 updated.
AS7-B corrected to AS7-C in figure Operational environment of the AS7-C

plug-in unit.
Issue 1-0
First issue.

Issue 1-4 en
AS7-C

Issue 1-4 en
AS7-C overview
1 AS7-C overview
The AS7-C preprocessing unit for multichannel signalling is a general
purpose peripheral slot computing plug-in unit. The AS7-C plug-in unit
fulfils various telecommunications protocols of the Nokia network elements
such as SS7, LAPD and X.25.
Purpose of the AS7-C
The AS7-C plug-in unit functions as a general purpose peripheral slot

computing engine with the necessary hardware to handle 256 HDLC, PPP
or transparent (TMA) channels in the Nokia network element. The plug-in
unit provides the hardware required by the DMX operating system and
application software such as the boot memory, SDRAM, interrupt handling,
process timing and V.24/V.28 based serial interfaces for service terminals.
The unit is connected to the back plane CompactPCI bus.
Operational environment of the AS7-C
The following figure illustrates the operational environment of the AS7-C

plug-in unit.

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AS7-C
PCM CIRCUIT
(TO SWITCHING NETWORK)
AS7-C 8M, 8k
(FROM CLOCK SYSTEM)
COMPACTPCI BUS
MASTER
UNIT
DN03514383
Figure 1. Operational environment of the AS7-C plug-in unit.
Notice that there are two V.24/V.28 based serial interfaces for service
terminals to provide an interface for controlling and monitoring the AS7-C
plug-in unit.
Data can be transferred between the AS7-C and the host processor unit of
the same cartridge via the CompactPCI bus on the back plane. The AS7-C
is connected to the CompactPCI bus with an Embedded PCI/PCI Bridge.
In addition to the CompactPCI connection, the unit also has two interrupt
lines to the host processor unit connected via the back plane.
The AS7-C plug-in unit is connected to the GSW0/1 via five (4+1)
duplicated 4.096 Mbit/s full duplex PCM line interfaces.
The unit gets the +5V, -5V and +3.3V supply voltages through back
connectors. V(I/O) pins are used for 3.3V supply.

Issue 1-4 en
Capacity and performance of AS7-C
2 Capacity and performance of AS7-C

The AS7-C plug-in unit replaces up to four AS7-A plug-in units in M98
mechanics.
Processor and memory
. 650 MHz Mobile Intel Celeron in a micro FCBGA-479 package.

. 256 MB SDRAM, assembled directly on PWB, 100 MHz bus, CL=2.
. 256 kB L2 cache on processor die, running at the processor
frequency.
. 8 MB boot FLASH.
PCI Buses
The unit has two internal PCI buses. The other bus is a 33 MHz, 32 bit PCI
bus and it is used as a compatibility PCI bus. Boot memory is located in
this bus, which is referred to as 'bus 0' in this document.
The other PCI bus is a 33/66MHz, 32 bit PCI bus. This bus is referred to as
'bus 2' in this document.
Serial interfaces
.
Two V.24/V.28 based maintenance terminal connections are
connected to the back plane.
.
Typical data transfer rate used is 9600 bit/s or 19200 bit/s. Maximum
38 400 bit/s.
PCM interfaces
The AS7-C has five (4+1) duplicated 4.096 Mbit/s full duplex PCM line
interfaces. Four PCMs are connected directly (behind the slot) to the
GSW0/1 and one is connected to the GSW0/1 via a PCM connector of the
cartridge.

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AS7-C
The HDLC controller
. Munich 256 in a P-BGA388 package.

. Implements HDLC, PPP and transparent (TMA) protocol processing
for 256 channels.

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Structure of AS7-C
3 Structure of AS7-C
3.1 Mechanical structure

The size of the AS7-C PWB is 233.4 x 220 mm and its nominal thicknes is
1.6 mm. The unit connects to the back plane with two shielded (P1, P4)
and one non–shielded (P5) 2 mm Hard Metric connectors. The front panel
contains two LEDs that indicate the state of the unit, and it is fastened to
the PWB with four M2.5 screws. The holes for the screws are copper
plated to ground the front panel to the PWB.
The front panel has cooling fins and a heat pipe is also connected to it. The
other end of the heat pipe is attached to a heat sink that covers the
processor.
3.2 Logical structure

The AS7-C unit has a Mobile Celeron processor with an internal speed of
650 MHz and a 100 MHz front side bus. The processor has 256KB L2
cache integrated on the same die, running with full processor core
frequency. The Mobile Celeron uses the Tualatin technology (0.13 µs
process).
The processor is connected to RadiSys 82600 north bridge. In addition to

the front side bus, the 82600 contains a 33 MHz, 32 bit PCI bus and a 33/
66 MHz, 32 bit PCI bus. The first PCI bus (33 MHz, 32 bit), bus 0, is used
as the compatibility PCI bus (the South bridge is located on this bus).
The compatibility PCI bus of the North bridge contains the South bridge
ASIC (interface to the unit I/O and Boot Flash) and AS7 specific FPGA.
The PCI/PCI bridge to the CompactPCI is also located on the compatibility
PCI bus.
The second PCI bus, bus 2, contains the HDLC controller.

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AS7-C
The HDLC controller and PCI/PCI Bridge need to be able to act as bus
masters on PCI buses they are connected to. The I/O Bridge can be target
only.
The following block diagram illustrates the logical structure of the AS7–C.
The components of the diagram are explained in more detail below.
82600
Celeron
Estacada SDRAM
Processor
North Bridge
CompactPCI
Ethernet Embedded Bus
82544EI PCI/PCI
10/100/1000
33MHz, 32bit PCI-bus 0
33/66MHz, 32bit PCI-bus 2
MAC+PHY Bridge
Mbit
Ethernet Interrupts
V.24/V.28
Ethernet I/O Bridge etc
82544EI ("South Bridge")
10/100/1000 MAC+PHY Including:
Mbit -DMX specific I/O
Ethernet
I/O Bus
("Universal"
non-multiplexed bus)
Boot Flash
AS7-
HDLC-
10 specific
Controller
FPGA
2 Mbit/s full
duplex PCM 4 Mbit/s full
2 8K
Alarm 5 duplex internal
Int 8M
DN03275349
PCM
Figure 2. Block diagram of the AS7-C plug-in unit.
The AS7-C has two internal PCI buses. The compatibility bus of the 82600
is a 33 MHz, 32 bit PCI bus (the ISA bridge is located behind this bus). The
secondary PCI bus is a 33/66 MHz, 32 bit PCI bus.
The compatibility bus of the 82600 is configured as bus 0. The secondary

PCI bus is configured as bus 2.

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Structure of AS7-C
82600 configuration registers are located on the bus 0, device 0. The host
bridge, memory controller configuration registers and compatibility PCI bus
registers are located in function 0. The secondary PCI configuration
registers are located in function 1.
The devices on PCI buses are identified with device number. The device
number is defined by PCI bus ADXX signal connected to device IDSEL
signal.
A device that can act as a master in the PCI bus has a unique request and
grant signal pair. The count of these masters on the bus 0 is limited to four
and on the bus 2 to seven by the bus arbiter, in addition to the 82600.
Celeron processor
The unit contains a Mobile Intel Celeron Processor with internal/bus

frequencies of 650/100 MHz and RadiSys 82600 Embedded Host Bridge.
The processor has 256 kB L2 cache integrated on the same die, running
with full processor core frequency.
SDRAM
The unit has 256 MB synchronous DRAM assembled directly on PWB.

The memory technology used is 256 Mbit technology. The memory bus
operates at 100 MHz speed.
HDLC controller
The HDLC controller of the AS7-C is the Munich 256 by Infineon. It is a

highly integrated protocol controller that implements HDLC, PPP and
transparent (TMA) protocol processing for 256 bidirectional channels.
The HDLC controller has a connection to the AS7-C internal PCI bus 2
(32Bit, 33/66 MHz) for transmitting data using DMA. It is able to act as bus
master.
The HDLC controller on bus 2 uses AD20 as the IDSEL signal and is
device 4. It uses the REQ/GNT pair 0.
The serial line interface of the HDLC controller is configured in a 16-port

mode. The HDLC controller is connected to AS7CL-FPGA via ten 2.048
Mbit/s serial lines.
The interrupt controller has an interrupt request line reserved for the HDLC
controller.

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AS7-C
AS7CL-FPGA
The AS7CL-FPGA is implemented with an FPGA designed by Nokia,

containing AS7-specific registers and devices.
The FPGA takes care of PCM line interfaces and clock supervision. It
includes Time Slot Selection, ANSI and JT1 registers for all 2.048 Mbit/s
PCM lines.
There are 128 application-specific interrupt timers for SS7 links and two
general purpose interrupt timers.
In addition to these there are various status and control registers.
The AS7CL-FPGA on bus 0 uses as the AD15 IDSEL signal and is device
4. It uses the REQ/GNT pair 1. The AS7CL-FPGA can only be a PCI target
so the arbitration signals are connected just in case more functionality is
needed in some other application in the future.
The device used for AS7CL-FPGA is Xilinx XC2S150 in PBGA256

package.
PCI/PCI Bridge
The PCI/PCI Bridge of the AS7-C is Intel 21555.
The Embedded Non-Transparent PCI/PCI bridge on bus 0 uses the AD14

signal as IDSELand is device 3. It uses the REQ/GNT pair 0.
Secondary PCI bus INTA signal (CPCI_INT) of the PCI/PCI Bridge is

connected to the interrupt controller of the unit.
Primary PCI bus INTA signal of the PCI/PCI Bridge is connected to back
connector pin P1A3 via 0 ohm resistor and to AS7CL-FPGA. The interrupt
signal is connected to AS7CL-FPGA just in case more functionality is
needed in some other applications in the future.
I/O Bridge
The I/O bridge is connected to bus 0 and uses the AD18 signal as IDSEL
and is device 7. The I/O Bridge can only be a PCI Bus target.
The I/O bridge controls the boot FLASH and the DMX related I/O devices.
The I/O bridge is implemented using the South Bridge ASIC by RadiSys.

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Structure of AS7-C
The various functions are implemented as addresses in one device. The

flash memory is implemented in the memory space, the memory address
range being 32 Mbytes. There are two separate I/O address ranges. The
primary I/O range is 512 bytes in size. This range includes the legacy DMX
functions (timers, interrupt controllers, serial interfaces and various status
and control registers) and the I2 C Interface. The secondary I/O range
includes the host CPU warm reset register and the AS7CL-FPGA
configuration register. This secondary I/O range is 2 kB in size.
Table 1. I/O Bridge address ranges
Range Size Description

Memory 32 MB Boot Flash.
Primary I/O 512 kB Legacy DMX functions.
Secondary I/O 2 kB The host CPU warm reset
register and AS7CL-FPGA
configuration register.
The primary I/O range contains devices with both 8 and 16 bit interface to
the data bus.
In most cases the 8 bit devices are connected to even addresses. The
exceptions are the 16550 UART and the interrupt controller. In these cases
all the bytes in the 32 bit DWORD are connected to the device (address bit
A0 is also connected).
Boot Memory range
The boot memory is 8 Mbytes. The primary I/O range contains the DMX
related I/O devices.
There are three 82C54 compatible timers. The timer clocks are mostly
generated from an onboard 20 MHz oscillator.
In AS7-C there are 17 internal interrupt signals. In addition to these signals

the interrupt signals from the PMC connectors are connected to the
interrupt controller. The interrupt controller is implemented within the South
Bridge ASIC.
The two serial interfaces are of the V.24/V.28 (RS-232) type. The
interfaces use 16550 compatible UARTs. The UART clock generator input
is to be connected to the 1.25 MHz clock signal divided from the unit 20
MHz clock oscillator. The connection is 1.25 MHz to XTAL1 and
BAUDOUT to RCLK.

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AS7-C
In addition to these there are various status and control registers.
The secondary I/O range contains 8 bit registers needed for host CPU
warm reset and the interface to down load AS7CL-FPGA code.
Reset Logic
The AS7-C unit is reset due to the following reasons:
.
power up / power fail (cold reset)
. initial hardware watchdog (cold reset)
.
programmable watchdog (warm reset)
. the CompactPCI bus reset signal goes active (warm reset)
. the host CPU performs an AS7-C specific warm reset operation
(warm reset)
. the host CPU performs an AS7-C specific hard reset operation (cold
reset)
. emulator reset (cold reset).
The programmable watchdog is implemented with an 82C54 compatible

timer (timer 0 counter 0). The counter is reset with a read operation to an I/
O address. There must be an additional control circuitry (initial hardware
watchdog) that will cause a new reset if the watchdog counter is not reset
within 419 ms after the CPU has been reset. This initial watchdog must
generate a cold reset restarting the whole plug-in unit (including the host
bridge). This prevents the unit from ending up in a hang situation.
The reset from CompactPCI is the input signal _RST (pin P1C21). This
signal is received with an RC circuitry and schmitt trigger input. The values
for R and C are chosen so that RC value is 0.00001 (for example R=1
kohm, C=10 nF).
The host CPU can reset the AS7-C in two different ways. The normal
operation is a warm reset that is performed by the host CPU writing to a
register in secondary I/O range of PCI/IO Bridge. The host CPU can also
cause a hard reset to the AS7-C unit. This is done by writing to the Reset
Control register within the embedded PCI/PCI Bridge. This operation
causes a total hard reset, as in power up.
In addition to the actual reset signal the processor uses also the INIT signal
depending on the type of restart.

Issue 1-4 en
Structure of AS7-C
Power feed
AS7-C gets the +5V, -5V and +3.3V supply voltages from the back plane.
All other voltages needed in the unit must be generated in the unit. Back
plane V(I/O) pins are used for 3,3V supply.
Processor voltages must be generated from 5V to divide the load of power

supply voltages.
The power up order of +5V and 3.3V of the cartridge power source is not
specified.
The AS7-C has current limiting electronics when it is plugged into a

powered on cartridge.
3.3 Interfaces
The connections of the AS7-C with the system are presented in the
following figure. The meanings of the interface signals are presented in the
table below.

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AS7-C
DR00B, DR00A...DR03B, DR03A

DR10B, DR10A...DR13B, DR13A
DT00B, DT00A...DT03B, DT03A
DT10B, DT10A...DT13B, DT13A SERIAL BUS
CLK R0A, R0B INTERFACE
_RST R1A, R1B
T0A, T0B
AD[31:0] T1A, T1B
C/_BE[3:0] RxD0, RxD1 SERIAL TERMINAL
PAR TxD0, TxD1 INTERFACE
COMPACTPCI _FRAME CPU_INT0
BUS _IRDY CPU_INT1 INTERRUPT
INTERFACE _TRDY
_STOP AS7-C CSA,
IDSEL CHANGEOVER
CSB
_DEVSEL
_PERR
_SERR TR0 X3_N, TR0 X3_P
_REQ TR0 X2_N, TR0 X2_P
_GNT TR0 X1_N/R-, TR0 X1_P/R+ ETHERNET
_INTA TR0 X0_N/T-, TR0 X0_P/T+
CLOCK
8M0A, 8M0B +5V
SYSSTEM
8K0A, 8K0B -5V POWER
INTERFACE
0V SUPPLY
+3,3V
JTAG
DN00249545
Figure 3. Interfaces of the AS7–C.
Table 2. Interface signals of the AS7-C
Signal Meaning
CLK Bus timing signal
_RST Reset signal
AD[31:0] Address and data signals
C/_BE[3:0]PAR Command and byte enable signals
PAR Parity signal
_FRAME Bus frame beginning and length
_IRDY Master ready signal
_TRDY Target ready signal
_STOP Target stop signal
IDSEL Selection signal for target of configuration
_DEVSEL Target has recognized its address

Issue 1-4 en
Structure of AS7-C
Table 2. Interface signals of the AS7-C (cont.)
Signal Meaning
_PERR Bus parity error
_SERR Bus system error
_REQ Master or target requests the bus to itself
_GNT CompactPCI arbitration grants the bus to
requester
_INTA Interrupt signal
JTAG The plug-in unit's JTAG interface
8M0A, 8M0B, Basic timing signals
8K0A, 8K0B
R0A, R0B, R1A, Serial bus signals (received data)
R1B
T0A, T0B T1A, T1B Serial bus signals (sent data)
DR00B, DR00A, Serial bus signals (received data)
DR01B, DR01A,
DR02B, DR02A,
DR03B, DR03A,
DR10B, DR10A,
DR11B, DR11A,
DR12B, DR12A,
DR13B, DR13A
DT00B, DTR00A, Serial bus signals (sent data)
DT01B, DTR01A,
DT02B, DT02A,
DT03B, DT03A,
DT10B, DT10A,
DT11B, DT11A,
DTR12B, DT12A,
DT13B, DT13A
RxD0, RxD1 Serial terminal interface (received data)
TxD0, TxD1 Serial terminal interface (sent data)
CPU_INT0, Interrupt
CPU_INT1
CSA, CSB Changeover signals
+5V, -5V, 0V, +3.3V Operating voltages
Serial Interfaces
The AS7-C has two serial terminal interfaces which are connected to the
back connector P4.

Issue 1-4 en
AS7-C
Compact PCI bus
AS7-C is connected to the back plane CompactPCI bus. The back plane
connector pin assignment supports 32 bit CompactPCI bus only. The
connector P1 is used for CompactPCI bus. The P2 connector is not
assembled.
5V signalling is used on CompactPCI bus. However, V(I/O) is connected to

3.3V on the back plane. V(I/O) pins are used for 3.3V supply. These V(I/O)
pins are not used as specified in CompactPCI Specification.
Changeover signal
The LM311 comparator is used in the change over signal interface as a

receiver. There are 100 kΩ serial resistors in the inputs of the differential
side selection signal. 100 kΩ and 100 pF RC circuit is used for filtering the
noise in the signal.
Interface to basic timing signals
The AS7-C interfaces to 8,192 MHz and 8 kHz basic timing signals. The
75107-type receiver is used in the interfaces. One kΩ serial resistors are
used in the basic timing signal inputs.
PCM line interfaces
The AS7-C interfaces with five 4,096 Mbit/s serial lines (internal PCM
lines) in the back plane. Four of these internal PCM lines (DT/DR) are
connected directly to the GSW0/1 and one of these PCM lines (T/R) are
shared with other AS7 plug-in units in the same cartridge so the
termination resistors of this PCM line are not in AS7-C. The interface logic
(AS7CL-FPGA) multiplex/demultiplex a 4,096 Mbit/s serial line to two
2,048 Mbit/s PCM lines connected to the HDLC controller.
The PCM line interfaces are duplicated. The AS7-C transmits on both
sides of the PCM lines and it receives data from the side selected by the
change over signal. If the change over signal is set low then PCM lines
from the GSW0 are selected in receive direction.
Type 75110 transmitter and type 75107 receiver is used in the 4,096 Mbit/s
PCM line interfaces.
There are 2.2 kΩ pull-ups in the A-line of the differential inputs of PCM line
receivers.

Issue 1-4 en
Structure of AS7-C
In the PCM lines, which are directly connected to the GWS, there are 68Ω
pull-down termination resistors in the differential inputs/outputs of PCM
line receivers/transmitters.
Other signals
The following signal are connected to the P5 back connector:
.
output interrupt signal AS7_INT0 driven by the AS7CL-FPGA
. output interrupt signal AS7_INT1 driven by the AS7CL-FPGA
.
the alarm signal and the alarm test signal (_AL, ALTEST), ALTEST
with 100 kΩ pull down, 10 kΩ serial resistor, 100 pF capacitor to
ground + schmitt trigger , _AL with MBT3904 + 68 ohm resistor.
Power Feed
AS7-C gets its +5V, -5V and +3.3V power feed from the back plane. All
other voltages need to be generated within the unit. V(I/O) pins are used
for 3,3V supply. These pins are connected to the 3.3V PWB layer on the
back plane.
The +5V and +3.3V supplies are controlled by a power control unit. This
provides the following capabilities for the AS7-C:
. overcurrent protection
. power up ramping and inrush current limitation
. check for threshold value to reset the unit if supply voltages are too
low.
The lack of -5V power is read from the I/O bridge status register.
The AS7-C may be unpowered due to a failure on the unit power supply
controller or a short circuit on the unit. However, even an unpowered AS7–
C does not prevent CompactPCI bus transactions between host CPU and
other peripheral units as the embedded PCI/PCI Bridge is powered directly
(via fuse) from the back plane supply voltages. The embedded PCI/PCI
Bridge resets if the AS7-C internal supply voltages are off. The embedded
PCI/PCI Bridge tri-states its buses if the primary reset input is asserted.
This ensures that the CompactPCI bus is not disturbed by AS7-C in this
situation.
The power up order of +5V and 3.3V of the cartridge power supply unit is
not specified.

Issue 1-4 en
AS7-C

Issue 1-4 en
Operation of AS7-C
4 Operation of AS7-C
Front panel
The AS7-C plug-in unit has two software-controlled LED indicators (red
and yellow) on its front panel. The red LED indicator is lit when the plug-in
unit is in start state; otherwise the LED indicators are software-controlled,
as indicated in the table below.
The size of the front panel is 20 x 262 mm. The front panel of the AS7–C
looks like this:

Issue 1-4 en
AS7-C
AP
DN03275434
Figure 4. AS7-C front panel.
Table 3. AS7-C front panel LED indicators
LED Colour Function

Red The LED is turned on after power-up and
when processor reset is activated.
AP Yellow The LED is turned off after power-up and
when processor reset is activated.
Back plane connectors
The back plane has the following connectors:

Issue 1-4 en
Operation of AS7-C
. P5 type: B(22), female 2mm Hard Metric connector, unshielded

. P4 type: A(22), female 2mm Hard Metric connector, shielded
. P1 type: A(22), female 2mm Hard Metric connector, shielded

Issue 1-4 en
AS7-C

Issue 1-4 en
Power consumption of AS7-C
5 Power consumption of AS7-C

AS7-C gets +3.3 V, +5 V and -5 V supply voltages through its back plane
connectors.
Table 4. Power Consumption of AS7-C
State +3.3 +5 V –5 V Total

Idle 8,98W 2,75W 1,02W 12,75W
Memory test 11,39W 5,61W 1,02W 18,02W
Boot up 9,72W 5,87W 0,87W 16,46W

Issue 1-4 en
AS7-C

Issue 1-4 en
AS7-C C105007
6 AS7-C C105007
J2 SW1
P5
P4
SW1
OFF ON
1 12
2 11
3 10
4 9
5 8
6 7
P1
DN03309124
Figure 5. DIP switches of the plug-in unit AS7-C
Altera Bit Blaster header J2
The J2 (Altera Bit Blaster) pin header is used for reprogramming the Altera
CPLD. No jumpers are installed.

Issue 1-4 en
AS7-C
Interchangeability code settings
The Interchangeability Switch Block consists of a 6–position DIP switch.

This switch contains the four interchangeability code bits. The
interchangeability lines drive to '0' when the switches are OFF.
Note
'OFF' is GND, 'ON' is VCC.
Table 5. SW1 switch settings.
Switch 1 Setting Meaning

1-12 OFF*) Interchangeability code bit 3 (MSB)
2-11 OFF*) Interchangeability code bit 2
3-10 OFF*) Interchangeability code bit 1
4-9 OFF*) Interchangeability code bit 0 (LSB)
5-8 OFF Not in use
6-7 OFF Not in use.
*) The first interchangeability code A corresponds to all switches OFF, after

which the settings start to roll for each interchangeability code change.
The table below presents the setting of the interchangeability code.
Table 6. Interchangeability code settings of AS7-C
ICC code Meaning

SW 1: 1–12 SW 1: 2–11 SW 1: 3–10 SW 1: 4–9 (LSB)
(MSB)
A OFF OFF OFF OFF
B OFF OFF OFF ON
C OFF OFF ON OFF
D OFF OFF ON ON
E OFF ON OFF OFF
F OFF ON OFF ON

Issue 1-4 en
AS7-C C105007
Table 6. Interchangeability code settings of AS7-C (cont.)
ICC code Meaning

G OFF ON ON OFF
H OFF ON ON ON
J ON OFF OFF OFF
K ON OFF OFF ON
L ON OFF ON OFF
M ON OFF ON ON
N ON ON OFF OFF
P ON ON OFF ON
R ON ON ON OFF

Issue 1-4 en
AS7-C

Issue 1-4 en
Connector maps of AS7-C
7 Connector maps of AS7-C

P5 connector
Connector P5 type: B(22), female 2mm Hard Metric connector, unshielded.
Table 7. P5 connector
CPCI ROW
NUMBERS
1 GND +5V +5V +5V +5V +5V GND
2 GND +5V +5V +5V +5V +5V GND
3 GND -5V -5V -5V -5V -5V GND
4 GND 8M0B 8M0A 8k0B 8k0A GND
5 GND CGSB CGSA _AS7_IN _AS7_IN GND
T1 T0
PCM to/ 6 GND R04B R04A T04B T04A GND
from
GSW0
PCM to/ 7 GND R14B R04A T14B T14A GND
from
GSW1
8 GND _AL ALTST GND
9 GND GND
Direct 10 GND DR00B DR00A DT00B DT00A GND
PCMs to/
from 11 GND DR01B DR01A DT01B DT01A GND
GSW0 12 GND DR02B DR02A DT02B DT02A GND
13 GND DR03B DR03A DT03B DT03A GND
14 GND GND
15 GND GND
16 GND GND
17 GND GND

Issue 1-4 en
AS7-C
Table 7. P5 connector (cont.)
CPCI ROW
NUMBERS
18 GND GND
19 GND GND
20 GND GND
21 GND GND
22 GND GND
F E D C B A Z
P4 connector
Connector P4 type: A(22), female 2mm Hard Metric connector, shielded
CPCI ROW
NUMBERS
1 GND GND
2 GND GND
3 GND GND
4 GND GND
5 GND GND
6 GND GND
7 GND GND
8 GND GND
9 GND GND
10 GND GND
11 GND GND
12 GND GND
13 GND GND
14 GND GND

Issue 1-4 en
Connector maps of AS7-C
CPCI ROW
NUMBERS
Direct 15 GND DR10B DR10A DT10B DT10A GND
PCMs to/
from 16 GND DR11B DR11A DT11B DT11A GND
GSW1 17 GND DR12B DR12A DT12B DT12A GND
18 GND DR13B DR13A DT13B DT13A GND
19 GND GND
20 GND GND
21 GND GND
22 GND GND
RS232 for 23 GND TxD0 GND* GND* RxD0 GND
UART0
RS232 for 24 GND TxD1 GND* GND* RxD1 GND
UART1
25 GND GND
F E D C B A Z
Note
GND-signals marked as GND* are connected to ground only in AS7-C

plug-in unit (not back plane).
P1 connector
Connector P1 type: A(22), female 2mm Hard Metric connector, shielded.
CPCI ROW
NUMBERS
1 GND 5V 3.3V _ENUM _REQ64 5V GND
2 GND _ACK64 AD[0] V(I/O) 5V AD[1] GND
3 GND AD[2] 5V AD[3] AD[4] 3.3V GND
4 GND AD[5] AD[6] 3.3V GND AD[7] GND
5 GND C/_BE[0] M66EN AD[8] AD[9] 3.3V GND

Issue 1-4 en
AS7-C
CPCI ROW
NUMBERS
6 GND AD[10] AD[11] V(I/O) GND AD[12] GND
7 GND AD[13] GND AD[14] AD[15] 3.3V GND
8 GND C/_BE[1] PAR 3.3V GND _SERR GND
9 GND _PERR GND _SBO SDONE 3.3V GND
10 GND _LOCK _STOP V(I/O) GND _DEVSEL GND
11 GND _TRDY GND _IRDY _FRAME 3.3V GND
12 GND CODING GND
13 GND - GND
14 GND AREA GND
15 GND C/_BE[2] GND AD[16] AD[17] AD[18] GND
16 GND AD[19] AD[20] 3.3V GND AD[21] GND
17 GND AD[22] GND AD[23] IDSEL C/_BE[3] GND
18 GND AD[24] AD[25] V(I/O) GND AD[26] GND
19 GND AD[27] GND AD[28] AD[29] AD[30] GND
20 GND AD[31] CLK0 3.3V GND _REQ GND
21 GND _GNT GND _RST BRSV2 BRSV1 GND
22 GND INTS INTP V(I/O) GND BRSV0 GND
23 GND _INTD 5V _INTC _INTB _INTA GND
24 GND TDI TDO TMS 5V TCK GND
25 GND 5V +12V _TRST -12V 5V GND
F E D C B A Z
Note
+12V and -12V are not used in the cartridge. These pins are unused.
CompactPCI Bus signals V(I/O) are used for 3.3V voltage supply. They
are not to be used as the supply voltage pins for the CompactPCI Bus
signal interface.

Issue 1-4 en

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DN02176023 # Nokia Siemens Networks 1 (38)

2 (38) # Nokia Siemens Networks DN02176023

2 Capacity and performance of AS7-C 11

5 Power consumption of AS7-C 29

7 Connector maps of AS7-C 35

DN02176023 # Nokia Siemens Networks 3 (38)

Table 1. I/O Bridge address ranges 17

4 (38) # Nokia Siemens Networks DN02176023

Figure 1. Operational environment of the AS7-C plug-in unit. 10

DN02176023 # Nokia Siemens Networks 5 (38)

6 (38) # Nokia Siemens Networks DN02176023

Changes between document issues are cumulative. Therefore, the latest

Changes between issues 1-3 and 1-4

Ethernet interface information removed.

Changes between issues 1-2 and 1-3

Added a table for setting the SW1 interchangeability switch.

Changes between issues 1-1 and 1-2

Section AS7-C C105007 updated.

Changes between issues 1-0 and 1-1

AS7-B corrected to AS7-C in figure Operational environment of the AS7-C

DN02176023 # Nokia Siemens Networks 7 (38)

8 (38) # Nokia Siemens Networks DN02176023

Purpose of the AS7-C

The AS7-C plug-in unit functions as a general purpose peripheral slot

The unit is connected to the back plane CompactPCI bus.

Operational environment of the AS7-C

The following figure illustrates the operational environment of the AS7-C

DN02176023 # Nokia Siemens Networks 9 (38)

Figure 1. Operational environment of the AS7-C plug-in unit.

10 (38) # Nokia Siemens Networks DN02176023

2 Capacity and performance of AS7-C

Processor and memory

. 650 MHz Mobile Intel Celeron in a micro FCBGA-479 package.

DN02176023 # Nokia Siemens Networks 11 (38)

The HDLC controller

. Munich 256 in a P-BGA388 package.

12 (38) # Nokia Siemens Networks DN02176023

3.1 Mechanical structure

3.2 Logical structure

The processor is connected to RadiSys 82600 north bridge. In addition to

The second PCI bus, bus 2, contains the HDLC controller.

DN02176023 # Nokia Siemens Networks 13 (38)

Figure 2. Block diagram of the AS7-C plug-in unit.

The compatibility bus of the 82600 is configured as bus 0. The secondary

14 (38) # Nokia Siemens Networks DN02176023

The unit contains a Mobile Intel Celeron Processor with internal/bus

The unit has 256 MB synchronous DRAM assembled directly on PWB.

The HDLC controller of the AS7-C is the Munich 256 by Infineon. It is a

The serial line interface of the HDLC controller is configured in a 16-port

DN02176023 # Nokia Siemens Networks 15 (38)

The AS7CL-FPGA is implemented with an FPGA designed by Nokia,

In addition to these there are various status and control registers.

The device used for AS7CL-FPGA is Xilinx XC2S150 in PBGA256

The PCI/PCI Bridge of the AS7-C is Intel 21555.

The Embedded Non-Transparent PCI/PCI bridge on bus 0 uses the AD14

Secondary PCI bus INTA signal (CPCI_INT) of the PCI/PCI Bridge is

16 (38) # Nokia Siemens Networks DN02176023

The various functions are implemented as addresses in one device. The

Table 1. I/O Bridge address ranges

Range Size Description