COMPARATIVE STUDY OF 32-BIT

MICROPROCESSORS

Submitted by:

Shalini Rai

MCA IInd sem.

80386

The block diagram of an 80386 is shown below:

EU

SU
Translation
PTU PU
Segment look aside
REGISTERS Registers buffer
BARREL SHIFTERS BUS
CONTROL
MUL/DIV Segment Page
ALU Translator Translator
ADDRESS DRIVER

PIPELINE/BUS SIZE
CONTROL

DECODER AND
SEUENCING
CONTROL
ROM
PREFETCH
QUEUE(16 MUX/TRANSCEIVER
BYTES)
INSTRUCTION
QUEUE
PREFETCHER
(3 Decoded
instructions)
DU

The 80386 includes a Bus Interface Unit for reading and providing data and instructions,
With a Prefetch Queue, an IU for controlling the EU with its registers, as well as an AU (SU + PU) for
Generating memory and I/O addresses.

The features of the 80386 are:

 32-bit general and offset registers
 16-byte prefetch queue
 Memory Management Unit with a Segmentation Unit and a Paging Unit
 32-bit Address and Data Bus
 4-Gbyte Physical address space
 64-Tbyte virtual address space
 80387 numerical coprocessor with IEEE standard-754-1985 for floating point arithmetic
 64K 8-, 16-, or 32-bit ports
 Built In Self Test Feature(BIST) that tests the microprocessor, coprocessor and cache when the
chip is reset; if it passes the test, EAX=0.
  Implementation of real, protected and virtual 8086 modes
 Associated on-chip cache to ensure high virtual memory performance.
 A Paging cache stores the last 32 entries and at 4 KB/Page entry; 128 KB of memory can be
directly addressed.

 By pipelining its functional units, it can overlap the execution of different stages of one instruction
and can process multiple instructions simultaneously.
 Its multiply/divide unit can perform 32-bit multiplication in 9-41 clock cycles depending upon the
no. of significant digits. It can divide 32 bit operands in 38 clocks (unsigned) or 43 clocks (signed).
 Its barrel shifter can shift 1-64 bits in a single clock cycle.
 Addressing Modes: 11 modes for instructions to specify operands.
 2 modes provide for instruction that operate on register or immediate operands.
REGISTER, IMMEDIATE
 9 are memory addressing modes.
DIRECT, INDIRECT, BASED, INDEXED, SCALED INDEXED, BASED INDEXED, BASED
SCALED INDEXED, BASED INDEXED WITH DISPLACEMENT, BASED SCALED INDEXED
WITH DISPLACEMENT

Functional PIN Diagram:

CLK2 Vcc
GND
D0-D31
A2-A31 ADDRESS BUS
BE0’-BE3’

ADS’ BUS CYCLE

W/R’ DEFINITION
Processor STATUS HOLD D/C’
and HLDA M/IO’
CONTROL LINES INTR LOCK’
NMI
RESET

NA’ BUS CYCLE

Coprocessor PEREQ BS16’ CONTROL
CONTROL BUSY’ READY’
lines ERROR’
 REGISTER ARCHITECTURE:

Instruction Pointers EFLAG Registers

31 16 15 0 31 16 15 0

EIP IP EFLAG FLAG

General Purpose Registers Segment Registers

31 16 15 87 0 15 0
EAX AH AL
EBX BH BL

ECX CH CL

EDX DH DL

ESI SI

EDI DI

EBP BP

ESP SP
CS
SS

DS

ES

FS

GS

The 80386 maintains compatibility with the 8086, and 80286, so even though its general registers are 32-
bit, they can also be used as 16- or 8-bit registers. The table above illustrates this. Note that this
Programming model of the 80386 also applies to the Pentium.
The 32-bit EIP register can support programs up to 4Gbytes, whereas the 8086 and 80286, with their 16-
bit IP register, could only support program segments of 64kbytes. The CS register enables larger
programs. Note that the CS can be changed under program control, but that the instruction pointer cannot
be written to directly by a program. It can only be changed by jumps, calls, returns or interrupts. Note that
far calls and jumps change the value of the CS register as well as the value of the instruction pointer.

Stack Segment and Stack Pointer:

Usually every program has its own stack segment. As on the 8086 the stack grows downwards, that is,
the value of the stack pointer decreases with a PUSH instruction and increases with a POP instruction. In
the 80386, if data is stored on the stack the value of ESP is reduced by 4, because the 80386 always
writes a
Complete double word (2*16 bits = 4*8 bits). When the i386 operates in 16-bit mode, only 2 bytes are
Written to the stack, and the value of SP is only reduced by 2, with each push.

Data Segments:

The 80386 adds two more data segment registers, called FS and GS.
The 80386 has four control registers and four memory management registers for protected mode, as well
as 8 debug registers. These registers are particularly useful in a multitasking environment. The debug
registers can be useful in locating errors in a given task.

32-bit 16-bit 8-bit NAME MAIN USE

register register register
EAX AX AH, AL Accumulator Multiplication/division/I/O, fast shifts
EBX BX BH,BL Base Register Pointer to Base Address in data
segment
ECX CX CH,CL Count Register Count value for repetitions, shifts,
Rotates
EDX DX DH,DL Data Register Multiplication, Division, I/O
EBP BP Base Pointer Pointer to Base Address in Stack
Segment
ESI SI Source Index Source String and index pointer
EDI DI Destination Index Destination String and index
pointer
ESP SP Stack Pointer
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment
FS Extra Segment
GS Extra Segment
EIP IP Instruction Pointer Instruction Offset
EFLAG FLAG Flags Processor Status

MEMORY MANAGEMENT, CONTROL AND DEBUG REGISTERS

 15 0 31 0 19 0

TSS SELECTOR TSS BASE ADDRESS TSS LIMIT

LDTSS SELECTOR LDT BASE ADDRESS LDT LIMIT

IDT BASE ADDRESS IDT LIMIT

GDT BASE ADDRESS GDT LIMIT

Control Registers:

31 16 15 0
CR0 for Paging

CR1 RESERVED

CR2 Page Fault

Linear Address

CR3 Page Directory

Base address

Debug Registers:

31 0

DR0 LINEAR BP ADDRESS 0

DR1 LINEAR BP ADDRESS 1

DR2 LINEAR BP ADDRESS 2

DR3 LINEAR BP ADDRESS 3

DR4 RESERVED
RESERVED
DR5
DEBUG STATUS
DR6
DEBUG CONTROL
DR7
Test Registers:

31 0

TEST CONTROL

TEST STATUS

(For page cache)

FLAGS:
Two new flags introduced in addition to those present till 80286

 VM (Virtual Mode): If set, while 80386 is in protected mode, switches to virtual 8086 operation,
handling segment loads as 8086 but generates exception 13 fault on privileged opcodes.
 RF (Resume Flag): This flag is used with the debug register breakpoints. It is checked at
instruction boundaries before breakpoint processing. When RF is set, it causes any debug fault to
be ignored on the next instruction. RF is then automatically reset at the successful completion of
every instruction.
So now total of 13 flags are there in 80386.

CONTROL REGISTERS:

 CR0: contains the MACHINE STATUS WORD(MSW)-

Monitor Coprocessor, Protection Enable, Emulate Coprocessor, Task Switch,
Paging Enable and Extension Type.
 CR2: holds the linear address that caused the last page fault detected. The error code, pushed
on to the page fault handler’s stack when it is invoked provides additional status information on
this page fault.
 CR3: contains the physical base address of the Page Directory Table.PDT is always page
aligned.

CR0 (MSW):

 PG: If set, enables on-chip paging unit.

 ET: (Processor Extension Type) If set, 80387 compatible 32 bit protocol is used. If Reset, 80287
compatible 16 bit protocol used.
 TS:(Task Switch) It is automatically set whenever any task switch operation is performed. If set, a
coprocessor escape code will cause a coprocessor not available trap.
 EM: (Emulate Coprocessor) It is set to cause all coprocessor opcodes to generate a coprocessor
not available fault. It is reset to allow coprocessor opcodes to be executed on 80287/80387.
  MP: (Monitor Coprocessor) It is used with TS bit to determine if the wait opcode will generate a
coprocessor not available fault when TS=1
When MP=1,TS=1, the wait opcode generates a trap else not.
 PE: (Protection Enable) It is set to enable the protected mode.

80486

The block diagram of 80486 is as:

Cache (8 Paging Segmentati Register

KB) Unit on Unit and ALU

BUS

INTERFA
CE

Prefetch
Decodin
er (32 Control Floating
g Unit
Bytes Unit Point Unit
Queue)

The 80486 was the first x86 to incorporate RISC elements into its design to improve performance. In
Addition to maintaining compatibility with the 80386 and earlier x86 processors it added the following
Features:
  Improved 80386 CPU (6 extra instructions)
 Hard-wired implementation of frequently used instructions (as in RISCs)
 A 5 stage instruction pipeline
 An 8K Cache Memory + cache controller (previously a separate device)
 An on-chip Floating Point coprocessor
 Longer Prefetch Queue (32-bytes as opposed to 16 on the 80386)
 Higher frequency operation
 Parity Generator/Checker
 Register architecture same as 80386
 EFLAG register contains an additional bit AC(Alignment Check)
(It is used to indicate that the processor has accessed a word at an odd
address or a double word at a non double word boundary.)

Like the 80386 it uses real, protected and virtual 8086 modes and its Memory Management Unit includes
a Segmentation Unit and a Paging Unit.

PARITY CHECKER/GENERATOR:

Parity is often used to determine if data are correctly read from a memory location. To facilitate this, Intel
has incorporated an internal parity generator/checker. Parity is generated by 80486 during each write
cycle.Parity is generated by the 80486 during each write cycle. Parity is generated as even parity, and a
parity bit is provided for each byte of memory. The parity check bits appear on pins DP0-DP3, which are
also parity inputs as well as outputs. These are typically stored in memory during each write cycle and
read from memory during each read cycle.

On a read, the microprocessor checks parity and generates a parity check error, if it occurs, on the PCHK
pin. A parity error causes no change in processing unless the user applies the PCHK signal to an interrupt
input.

CACHE MEMORY:

The cache memory system stores data used by a program and also the instructions of the program. The
cache is organized as a four- way set associative cache, with each line (location) containing 16 bytes or
four double words of data. The cache operates as write through cache.

Control Register 0(CR0) is used to control the cache with two new control bits not present in 80386.

 CD (Cache Disable): If CD=1, all cache operations are inhibited.

 NW(Non-Cache Write Through): It is used to inhibit cache write through operation.

These are inhibited only for testing. For normal program operation, CD=0 and NW=0.

When a bus line is filled , it must acquire $, 32-bit numbers from the memory to fill a line in the in the
cache. Filling is done with a burst cycle.
Two new control bits are added to disable caching for sections of translated memory pages.

 PWT (Page Write Through): Controls how the cache functions for a write operation of the
extended cache memory. It does not control writing to the internal cache.Externally it can be
used to dictate the write through policy of the external cache.

 PCD (Page Cache Disable): controls the on-chip cache. If PCD=0, the on-chip cache is
enabled for the current page of the memory.

New instructions to control internal cache

 XADD: To allow fast addition.

 CMPXCHG: Comparison with an exchange.

 BSWAP: Byte Swap

68020

• 32-bit address & ALU.

• 3 stage pipeline.
• Instruction cache of 128K 16-bit word cache. At start of an instruction fetch,
the 68020 always outputs LOW on ECS’ (Early cycle start) pin and accesses
the cache. If instruction is found in the cache the 68020 inhibits outputting
LOW on AS’ pin and reads instruction from main memory.
• Unrestricted word and long word data access.
• 4GB of physical memory
• 8 x Multiprocessing capability.
• Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and
32 bits remainder) instructions, and bit field manipulations.
• ADDRESSING MODES :

 Register Direct (Data Register Direct, Address Register

Direct)
  Register Indirect (Address Register Indirect ARI,ARI with
postincrement, ARI with predecrement, ARI with
displacement).
 Register Direct with index (ARI with index (8-bit
displacement), ARI with index (base displacement)).
 Memory Indirect (post indexed, preindexed)
 Program Counter indirect with displacement.
 Program Counter Indirect with index (8-bit displacement,
Base displacement).
 Program Counter memory indirect (Post indexed, pre
indexed)
 Absolute(short, long)
 Immediate

• REGISTERS:

 8 32-bit data registers

 7 32-bit address registers
 3 32-bit SP’s
 1 32-bit PC (all bits used)
 1 16-bit SR
 1 32-bit VBR(Vector Base Register)
 2 3-bit function code registers(SFC and DFC)
 1 32-bit CAAR (cache address register)
 1 CACR (Cache control register)

68030:

• Split instruction and data cache of 256 bytes each

• On-chip MMU (68851).
• Low cost EC = No MMU.

68040:

• Instruction and data caches of 4 kilobytes each

• 6 stage pipeline.
• Low cost LC = No FPU.
• Low cost EC = No FPU & MMU.
The 68040 was the first Motorola family member with an on-chip Floating Point Unit
(FPU). It thus included all of the functionality that previously required external chips,
namely the FPU and Memory Management Unit (MMU), which was added in the
68030. It also had split instruction and data caches of 4 Kilobytes each. It was fully
pipelined with six stages.

Zilog Z80000

This was Zilog's 32-bit processor from 1986, an expansion of its 16-bit predecessor,
the Zilog Z8000. It included multiprocessing capability, a six-stage instruction
pipeline, and a 256-byte cache. Its memory addressing system could access 4
gigabytes of RAM. Described at the time as a "mainframe on a chip," the processor
was in many ways an equivalent to Intel's 80386. It could execute code written for
the Z8000, but was not compatible with the Intel x86 architecture, nor was it Z80
compatible.

Sixteen general-purpose registers of variable size were available through use of a

64-byte "register file." The processor included a memory management unit that
provided protected memory, important for multitasking, and virtual memory
addressing for temporary storage of RAM on a hard disk. The processor had three
methods of accessing memory:

• compact mode – meant for small programs, could only access 64 kB

(equivalent to the Z8000's non-segmented mode)
• segmented mode – 32,768 segments of 64 kB or 128 segments of 16 MB,
making a total of 2 GB of accessible memory
• linear mode – direct 4 GB access

The processor was designed to interoperate with other integrated circuits designed
for use with the Z8000, such as the Zilog Z8070 floating-point coprocessor

REFERENCES:

 Microprocessors Theory and applications: Intel and Motorola by

RAFIQUZZAMUN

 The Intel microprocessors By Barry B. Brey and C.R. Sharma

 Computer System Architecture by M. MORRIS MANO

 Wikipedia