School of Electrical and Information Engineering

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ELEC5402 Digital Integrated Circuit Design

Semester 1, 2010
Description
(The essential points of the description in the Handbook and School web pages are repeated here
for convenience.)
Recommended elective unit of study for Computer, Electrical, Software and Telecommunications
Engineering.
Prerequisite: ELEC3404 Electronic Circuit Design Offered: Semester 1
Classes: One 2hr lecture and a 2hr laboratory practice per week. Assessment: Design work
and a 2hr Final Exam.
Syllabus Fundamentals of CMOS transistors and technology for digital IC design (IC production
process, design rules, layout). Design automation and verification (DRC, circuit extraction,
simulation). Basic digital building blocks (inverters, simple logic gates, transmission gates,
propagation delays, power dissipation and noise margins). Digital circuits and systems (dynamic
circuits, sequential ciruicts, RAM, ROM, ALUs). Semicustom design (gate arrays and standard
cells).

Aims/Goals
This unit of study builds upon ELEC3401 (Electronic devices and circuits) and explores CMOS
technology and integrated circuit design and fabrication. The fundamental theory and techniques
behind digital integrated circuit design are introduced. Furthermore, a primary focus of this
course is providing the student with practical laboratory experience using a professional VLSI
CAD tool to design digital integrated circuits. This course provides a foundation for more
advanced digital integrated circuit design techniques and also analogue integrated circuit design.
Learning Commitments and Contact
Learning will be primarily face-to-face with a limited amount on-line.
Learning Situations
One two hour lecture and a 2 hour laboratory session is timetabled for each week of the semester.
Students are expected to
• attend all lectures,
• maintain awareness of any information made available on the unit web pages,
• attend all laboratory classes
• complete all assignments.

Learner Preparation
Basic circuit analysis skills are essential as is a basic understanding of semiconductors. A
knowledge of CMOS circuits and SPICE simulation is desirable.
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Student Learning Outcomes
Students who complete this unit will have the ability to
• design digital integrated circuits from layout of the circuit to simulation
• employ standard digital design techniques such as static logic, dynamic and tristate
logic, arithmetic building blocks, sequential logic
• analyse CMOS circuits

Assessment
Grade descriptors
Students awarded the various passing grades are expected to have the following attributes:
Pass (P) A P grade student is expected to have sufficient understanding of the core
material to solve the basic problems arising in the laboratory work. The student should
demonstrate some ability to design digital integrated circuits.
Credit (CR) A CR level student is expected to have a good understanding of the core
material as evidenced by the ability to solve all relevant problems. The student should
demonstrate an ability to choose an appropriate design technique and apply this
technique in the design of a digital integrated circuit.
Distinction (D) A D level student is expected to have an excellent understanding of the
core material plus a good understanding of some advanced material. The student should
demonstrate an ability to apply course material to new problems similar to those
presented in class and be able to differentiate between different design techniques and
optimise a digital integrated circuit design.
High Distinction (HD) A HD level student is expected to have a deep understanding of
material covered in the unit. The student should demonstrate an ability to apply the
course material in a creative and comprehensive fashion. In addition to the attributes
described above, the student will be able to formulate new digital integrated circuit
designs based on the principles of standard design techniques and modify the design
according to simulation results and design goals.
Assessment components
The total mark for the unit will be obtained by adding two components:
1. Laboratory work (70 marks)
2. Final Examination (25 marks)
3. Class Participation (5 marks)

The class participation marks encourage active participation during lectures and the labs.
The laboratory work will consist of three projects:
1. Digital logic gate design (5 marks)
2. Adder (30 marks)
3. Arithmetic Logic Unit (ALU) (35 marks)
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Program
The topics covered in lectures and tutorials are shown in the table.
Wk Lecture Topic Laboratory
Date
1 1 March Introduction to Digital IC Design SPICE/Assignment 1
2 8 March CMOS Technology and Assignment 1
Manufacturing Technology
3 15 March CMOS Inverter and Basic Static Logic Assignment 1

4 22 March Layout Techniques and Dynamic Assignment 1

Logic
5 29 March Sequential Logic Assignment 2

6 12 April Switch RC Model and Logical Effort Assignment 2

Theorem
7 19 April Finite State Machine and Verilog Assignment 2
Introduction
8 26 April Arithmetic Building Blocks Assignment 2
9 3 May Memory Assignment 3

10 10 May Wires, Interconnect and Clocking Assignment 3

11 17 May To be announced Assignment 3

12 24 May Case Studies/Catch-Up/Other Assignment 3

Technologies
13 31 May Review Assignment 3
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References and Web Links

Prescribed text
rd
CMOS VLSI Design A circuit and systems perspective (3 Edition), Neil Weste, David Harris,
Addison Wesley
Recommended texts
Digital Integrated Circuits, Jan Rabaey, A. Chandrakasan, B. Nikolic, Prentice Hall
rd
CMOS Digital Integrated Circuits Analysis and design, Sung-Mo Kang, Yusuf Leblebici, 3
Edition, McGraw Hill
Analog VLSI: Circuits and Principles, Shih-Chii Liu et al., The MIT Press
Web page for this unit of study
http://www.eelab.usyd.edu.au/elec5402/
Related Web sites
http://www.cmosvlsi.com
http://bwrc.eecs.berkeley.edu/IcBook/
Examinations timetable
http://www.usyd.edu.au/su/recserv/exam/exams.html
University policy directory
http://fmweb01.ucc.usyd.edu.au/FMPro?-db=POL_Main.fp5&-format=/pol/pol_search.html&-
lay=www&-view
University policy on academic honesty
http://fmweb01.ucc.usyd.edu.au/FMPro?-db=POL_Main.fp5&-lay=www&-
format=/pol/pol_summary.html&-RecID=10&-find
Staff Contact Information
Lecturer
Alistair McEwan, Room 850 (Electrical Engineering Bldg.) alistair@ee.usyd.edu.au
Tutor
Sean Luskey Rm. 840, sluskey@ee.usyd.edu.au
Mark (runchun) Wang, Rm. 840, rwang@ee.usyd.edu.au