INSTRUCTION SET

PRINCIPLES AND EXAMPLES

Source: Book
support materials
By: Alfonso Avila
Alfonso Avila, ITESM Campus Monterrey

Instruction set design

… Evolution of instruction sets
… Classifying instruction set architectures
… Memory addressing
… Operations in the instruction set
… Type and operand size
… Encoding an instruction set
… MIPS instruction set
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Evolution of Instruction Set

Single Accumulator (EDSAC 1950)

Accumulator + Index Registers

(Manchester Mark I, IBM 700 series 1953)

Separation of Programming Model

from Implementation

High-level Language Based Concept of a Family

(B5000 1963) (IBM 360 1964)

General Purpose Register Machines

Complex Instruction Sets Load/Store Architecture

(Vax Intel 432 1977-80)
(Vax, ((CDC 6600,, Cray
y 1 1963-76))

RISC
(Mips,Sparc,HP-PA,IBM RS6000, . . .1987)
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Classifying ISA’s
ISAs
… ISA = Instruction Set Architecture

… Differentiation based upon the type of internal

storage in the CPU

… Four different categories:

† Stack
† Accumulator
A l
† Register 1 (register-memory)
† Register 2 (load-store)
(load store)
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Classifying ISA’s
ISAs
… Implement the following statement using an register-memory
architecture
C = A + B assuming: A in address 100
B in address 101
C in address 102

load R1, 100 ; R1 <- MEM[100]

add R1, 101 ; R1 <- R1 + MEM[101]
store 102, R1 ; MEM[102] <- R1

This architecture uses general purpose registers (GPRs)

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Classifying ISA’s
ISAs
… Implement the following statement using an accumulator architecture
C = A + B assuming: A in address 100
B in address 101
C in address 102

load 100 ; ACC <- MEM[100]

add 101 ; ACC <- ACC + MEM[101]
store 102 ; MEM[102] <- ACC

ACC = Accumulator register

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Classifying ISA’s
ISAs
… Implement the following statement using a
stack architecture
C = A + B assuming: A in address 100
B in address 101
C in address 102

Push 100 ; SP <- SP+1; MEM[SP]<- MEM[100]

Push 101 ; SP <- SP+1;; MEM[SP]<-
[ ] MEM[101]
[ ]
Add ; MEM[SP-1]<-MEM[SP]+MEM[SP-1] ;SP<-SP-1
Pop 102 ; MEM[102]<-MEM[SP];SP<-SP-1

SP = STACK POINTER
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Classifying ISA’s
ISAs
… Implement the following statement using an register-register or
load-store architecture
C = A + B assuming: A in address 100
B in address 101
C in address 102

load R1, 100 ; R1 <- MEM[100]

load R2, 101 ; R2 <- MEM[101]
add R3,
R3 R1
R1, R2 ; R3 <-
< R1 + R2
store 102, R3 ; MEM[102] <- R3

This architecture uses general purpose registers (GPR´s)

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Classifying ISA’s
ISAs
… Implement the following statement using an memory-
memory architecture
C = A + B assuming: A in address 100
B in address 101
0
C in address 102

move 102, 100 ; MEM[102] <- MEM[100]

add 102, 101 ; MEM[102] <- MEM[102] + MEM[101]
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Classifying ISA’s
ISAs
Implicit operands vs explicit operands

# Operands
Architecture
A hit t I li it
Implicit E li it
Explicit
Stack
Accumulator
Register-memory
Register-register
eg s e eg s e
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GPR vs SPR
… General purpose registers (R0,R1,..RN) are used
instead of specific purpose registers
(Accumulator, B, etc.)

… What are the reasons for the emergence of GPRs?

† Registers are faster than memory

† Registers are easy to use by the compiler

(Holding variables, easier expression evaluation)
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GPR machines won

… Operands for a typical ALU instruction
Number of Maximum number Examples
memory addresses of operands allowed
SPARC, MIPS, Precision
0 3 Architecture, PowerPC, Alpha

1 2 Intel 80x86, Motorola 68000

2 2 VAX (also has 3-operand format)

3 3 VAX (also has 2-operand

2 operand format)
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Advantages and Disadvantages

Register-Register
g g type
yp ((0,3)
, )
Advantage
† Simple
† Fix-length instruction encoding
† Simple code generation model
† Instructions take the same number of cycles to execute
Disadvantage
† Higher instruction count than architectures with memory references
in instruction
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Advantages and Disadvantages

Register-Memory
g y type
yp ((1,3))
Advantage
† Data is accessed without loading first
† Instruction format tends to be easy to code

Di d t
Disadvantage
† Source operand is destroyed in a binary operation
† Clocks per instruction varies by operand type
† Register number may be restricted due to encoding a register
and a memory address on each instruction
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Advantages and Disadvantages

Memory-Memory
y y type
yp ((3,0)
, )
Advantage
† Most compact
† Does not waist registers for temporary values

Disadvantage
† Large variation on instruction size specially for
three operand instructions
† Large variations in work per instruction

† Memory accesses create bottleneck

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Addressing modes tried

Addressing Format Operations Effective Address (EA)
Mode Calculation
Register Mov R4,R3 R4<-R3 NA
Immediate Mov R4,#3 R4<-3 NA
Direct Mov R4,200 R4<-Mem[200] EA = 200
Indirect with Mov R4,(R1)
R4 (R1) R4< Mem[R1]
R4<-Mem[R1] EA = R1
register
Indirect with Mov R4,20(R1) R4<-Mem[R1+20] EA = 200 + R1
displacement
Indirect with Mov R4,(R1)+
R4 (R1)+ R4< Mem[R1]
R4<-Mem[R1] EA = R1
postincrement R1<-R1+d
Indirect with Mov R4,-(R1) R1<-R1-d EA = R1
predecrement R4<-Mem[R1]

Indexed Mov R4,(R1,R2) R4<-Mem[R1 + R2] EA = R1+R2

Indexed with Mov R4,20(R1,R2) R4<-Mem[R1 + R2 + EA = R1+R2
displacement 20]
Memoryy Indirect Mov R4,@(R3)
@( ) R4<-Mem[Mem[R3]]
[ [ ]] EA1 = R3
EA2 = Mem[R3]
Scaled Mov R4 <-
R4,100(R2)[R4] Mem[100+R2+R4*d]
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Addressing mode usage

What addressing modes are useful for current application requirements?
Af running three
After h SPEC88
S C88 programs on a VAX
A computer

Addressing Percentage Percentage

Mode Range Average
- Displacement 32% - 55% 42%
- Immediate 17% - 43% 33%
- Indirect 3% - 24% 13%
- Scaled 0% - 16% 7%
- M
Memory IIndirect
di t 1% - 6% 3%
- Misc 0% - 3% 2%

75% displacement, immediate

88% displacement, immediate and indirect
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Addressing and alignment

How do byte addresses map onto words?
…

… Big endian: address of most significance

† IBM
M 370, Mo
Motorola
o o a 68
68K,, M
MIPS,
S, Spa
Sparc,
c, HP

… Little endian: address of least significance

† Intel 80x86
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Field size for displacement

Workload: Average of 5 programs from SPECint92 and average of 5 programs
from SPECfp92
Axis: X-axis is in powers of 2 the displacement’s size for the displacement
addressing mode
Example: 4 => 23 < addresses < 24
% of displacement
Observations: for addressing memory Int. Avg. FP Avg.

… 1% greater than 30%

Too many zero displacement
16bits 25%

20%

… 50% to 60% fit 15%

in 8 bits 10%

5%

0%
… 75% to 80% fit
0

10

11

12

13

14

15
within 16 bits Number of bits needed for a displacement
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Addressing summary
… Important addressing modes are:
† Displacement, immediate, register indirect

… Displacement size:
† 12 bit displacement – 75%
† 16 bit and 32 bit - 99%

… Immediate value size

† 50% to 70% fit in 8 bits
† 75% to 80% fit in 16bits
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Typical ISA operations

… A rule of thumb across all architectures is that the most
widely executed instructions are the simple operations of
an instruction set
… The figure shows that 10 simple instructions account for
96% of the total instructions executed
° Rank instruction Integer Average Percent total executed
1 load 22%
2 conditional branch 20%
3 compare 16%
4 store 12%
5 add 8%
6 and 6%
7 sub 5%
8 move register-register 4%
9 call 1%
10 return
t 1%
Total 96%
° Simple instructions dominate instruction frequency
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Instructions for flow control

… What does control flow means?
† Instructions changing the program’s flow control
† In 1950 these instructions were called transfers
† In 1960
960 these
ese instructions
s uc o s wewere
e ca
called
ed branches
b a c es

… Four types of instructions for control flow

† Conditional branches
† Jumps
† Procedure calls
† Procedure returns
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Instructions for flow control

… Jumps – unconditional transfer
… Conditional branches
† How is the condition code set?
† H iis the
How h target specified?
ifi d? How
H ffar away is
i it?
i?
… Calls
† How is the target specified? How far away is it?
† Where is the return address kept?
† How are the arguments passed?
… Returns
† Where is the return address? How are the results passed?
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Target address specification

… How to specify the destination of target address of
a jump?
j ?
† The explicit specification uses:
(a) A displacement (PC-relative)
(b) A register

… With displacement
† The displacement
p is added to the PC
† Useful for short jumps
† Supports position independent coding

… With register
† It applies for indirect jumps and returns only known during program
execution
† examples:
l switch,
wit h case, iin C
C; virtual
i t l ffunctions
ti en C++
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Branch address specification

p
… Compiler determines the address for unconditional
and conditional branches.
† Specified as a register containing the target address
† Specified
p as a PC-relative offset
… Considering how the branch instruction is coded?
† The full address is desired? How long is the instruction?
† Use a register to hold the address,
address do setup and effective address
calculation take longer?
† Small offsets are good for PC-relative branches
† PC relative is also position independent simplifying linker work
… How to choose the best option?
† Obtaining program measurements
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Statistics - type of branch

… What is the type of instruction more common?

Program Type
Instruction Tex Spice Gcc
Type
Call/Return 16% 13% 10%
Jump 18% 12% 12%
Conditional 66% 75% 78%
… C diti l b
Conditional branches
h are more common
† What is the condition most frequently tested?
† Are the branches going forward or backward?
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Jump´´s condition specification

Jump
Name Condition test Advantages Disadvantage
s
Conditional ALU Condition Instructions
code determines the activated must execute
value of the automatically in order
codes
Condition Stores in a Simple Uses one
register register the register
comparison
result
Compare and Compare and One Too much
Jump jump instructions work for one
operations in for both instruction
the same operations
instruction
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Types of compares of branches

… What is the type of compare more frequent?

Program Type
Compare Tex Spice Gcc
Type
LT/GE 25% 0% 11%
GT/LE 3% 25% 0%
EQ/NE 72% 75% 89%
Immediate 83% 92% 84%
… An average of 50% of the compares are simple
EQ or NE with the immediate value of 0 (zero)
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Types of compares of branches

… What is the direction of branch more common?

Program % of % of taken % of all inst

Type backward branches modifying
the PC
GCC 26% 54% 16.4%
Spice 31% 51% 13%
Tex 17% 54% 24%
Average 25% 53% 17.8%
…

… Most backward branches are loops (Taken 90%)

… The statistics are compiler and application

dependent
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Important branch
branch’ss property
… Statistics obtained using benchmarks show:

† A large number of compares make tests using equal or

no equal

† A large number of comparisons are against zero

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MIPS instruction set

… MIPS instruction types
MIPS assembly language
Category Instruction Example Meaning Comments
add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract
sub ac sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three
ee ope
operands;
a ds; da
data
a in registers
eg s e s

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register
store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register
store byte sb $s1,, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory
load upper immediate lui $s1, 100 $s1 = 100 * 2
16 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to Equal test; PC-relative branch
PC + 4 + 100

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to Not equal test; PC-relative
PC C + 4 + 100
00
Conditional
C diti l
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; for beq, bne
else $s1 = 0

set less than slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than constant
immediate else $s1 = 0

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return
tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
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MIPS instruction set

… MIPS operands

Name Register number Usage

$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7
$s0 $s7 16-23
16 23 saved
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$f
$fp 30 frame pointer
$ra 31 return address
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MIPS instruction set

… Software conventions 0
1
zero
at
constant 0
reserved for assembler
2 v0 expression evaluation and
3 v1 function results
4 a0 arguments
5 a1
6 a2
7 a3
8 t0 temporary: caller saves
...
15 t7
16 s0 callee saves
...
23 s7
24 t8
25 t9
26 k0 reserved for OS kernel
27 k1
28 gp Pointer to g
global area
29 sp Stack pointer
30 fp frame pointer
31 ra Return Address (HW)
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MIPS instruction set

… MIPS Instruction Formats
1 Immediate addressing
1.
op rs rt Immediate

2. Register addressing
op rs rt rd ... funct Registers
R i t
Register

3. Base addressing
op rs rt Address Memory

Register + Byte Halfword Word

4. PC-relative addressing
op rs rt Address Memory

PC + Word

5. Pseudodirect addressing
op Add
Address Memory

PC Word
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MIPS instruction set

… Arithmetic MIPS instructions
† All instructions have 3 operands
† Operand order is fixed (destination first)

Example:

C code: A=B+C

MIPS code: add $s0, $s1, $s2

(associated with variables by compiler)

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MIPS instruction set

… Arithmetic MIPS instructions
† Design Principle: simplicity favors regularity

C code: A = B + C + D;
E = F - A;

MIPS code: add $t0, $s1, $s2

add $s0, $t0, $s3
sub $s4, $s5, $s0
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MIPS instruction set

… Arithmetic MIPS instructions
Instruction Example Meaning Comments
add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible
subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible
add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible
add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions
subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions
add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions
multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product
multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product
divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder Hi = $2 mod $3
divide unsigned divu $2,$3
$2 $3 Lo = $2 ÷ $3,
$3 Unsigned quotient & remainder Hi = $2 mod $3
Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi
Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

.
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MIPS instruction set

… Logical MIPS instructions
Instruction Example Meaning Comment
and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND
or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR
xor xor $1,$2,$3 $1 = $2 Å $3 3 reg. operands; Logical XOR
nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR
and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant
or immediate ori $1
$1,$2,10
$2 10 $1 = $2 | 10 Logical OR reg,
reg constant
xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant
shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant
shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant
shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)
shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable
shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable
shift
hift right
i ht arithm.
ith srav $1,$2,
$1 $2 $3 $1 = $2 >> $3 Shift right
i ht arith.
ith by
b variable
i bl

.
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MIPS instruction set

… Memory organization
† Viewed as a large, single-dimension array, with an
address.
† A memory address is an index into the array
† "Byte addressing" means that the index points to a
byte
y of memory. y
0 8 bits of data

1 8 bits of data

2 8 bits of data

3 8 bits of data

4 8 bits of data

5 8 bits of data

6 8 bits of data

...
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MIPS instruction set

… Memory organization
† Most data items use larger "words“instead of bytes
† For MIPS, a word is 32 bits or 4 bytes.

0 32 bits of data

4 32 bits of data

8 32 bits of data

12 32 bits of data

...

† 232 bytes with byte addresses from 0 to 232-1 1

† 230 words with byte addresses 0, 4, 8, ... 232-4
† Words are aligned. What are the least 2 significant bits
of a word address?
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MIPS instruction set

… Load and store instructions
† Example:

C code: A[8]
[ ] = h + A[8];
[ ];
A[] start address in $s3; h value in $s2

MIPS code:
d lw $t0,
l $ 0 32($
32($s3)
3)
add $t0, $s2, $t0
sw $t0, 32($s3)

† Store word has destination last

† Remember arithmetic operands are registers, not
memory!
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MIPS instruction set

… Load/Store instructions
Instruction Comment
sw 500($4), $3 Store word
sh 502($2), $3 Store half
sb 41($3), $2 Store byte

lw $1, 30($2) Load word

lh $1, 40($3) Load halfword
lhu $1, 40($3) Load halfword unsigned
lb $1, 40($3) Load byte
y
lbu $1, 40($3) Load byte unsigned

lui $1,
, 40 Load Upper
pp Immediate (
(16 bits
shifted left by 16)
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MIPS instruction set

… Example:
swap(int v[], int k);
{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
} swap:
muli $2, $5, 4
add $2, $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16,, 0($2)
( )
sw $15, 4($2)
jr $31
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MIPS instruction set

… Instructions, like registers and words of data, are
also 32 bits long
† Example: add $t0, $s1, $s2
† registers
i hhave numbers,
b $t0 9 $
$t0=9, $s1=17,
1 17 $$s2=18
2 18

† Instruction Format:

000000 10001 10010 01000 00000 100000

†

op rs rt rd shamt funct

† Wh do
What d the
h field
f ld names stand
d for?
f ?
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MIPS instruction set

… Instruction format for load/store instructions
† How to accomplish regularity?
† New principle: Good design demands a compromise

… Introduce a new type of instruction format

† I-type for data transfer instructions the other format was R-type for
register
† Example: lw $t0, 32($s2)

35 18 9 32

op rs rt 16 bit number

† Where is the compromise?

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MIPS instruction set

… Control flow instructions
† This instructions change the "next" instruction to be executed
† MIPS conditional branch instructions:

bne $t0, $t1, Label

beq $t0, $t1, Label

† Example: if (i = =j) h = i + j;

bne $s0, $s1, Label

add $s3,
$ $
$s0, $
$s1
Label:
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MIPS instruction set

… Control flow instructions
† These instructions change the "next" instruction to be executed

† MIPS unconditional branch instructions:

j l
label
b l

† Example:

if (i!=j) beq $s4, $s5, Lab1

h=i+j; add $s3, $s4, $s5
else j Lab2
h=i-j; Lab1: sub $s3, $s4, $s5
Lab2: ...

† Can you build a simple for loop?

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MIPS instruction set

… Material covered up to now
Instruction Meaning
add $s1,$s2,$s3 $s1 = $s2 + $s3
sub $s1,$s2,$s3 $s1 = $s2 – $s3
lw $
$s1,100($s2)
, ($ ) $s1 = M[$s2+100]
$ [$ ]
sw $s1,100($s2) M[$s2+100] = $s1
bne $s4,$s5,L Next instr. is at Label if $s4 ° $s5
beq $s4,$s5,L Next instr. is at Label if $s4 = $s5
j Label Next instr. is at Label

Formats:
op rs rt
t rd
d shamt
h t f
funct
t
R
op rs rt 16 bit address
I
op 26 bit address
J
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MIPS instruction set

… Branch-if-less-than instruction
† New instruction Branch-if-less-than !
if $s1 < $s2 then
$t0 = 1

slt $t0, $s1, $s2 else

$t0 = 0

† After this, it is possible to do

"blt $s1, $s2, Label"

† Note that the assembler needs a register to do this,

— there are policies of use conventions for registers
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MIPS instruction set

Instruction Example Meaning
branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100
Equal test; PC relative branch
branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100
Not equal
q test;; PC relative
set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp.
set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; 2’s
2 s comp
comp.
set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; natural no.
set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; natural
jump j 10000 goto 10000
Jump to target address
jump register jr $31 go to $31
For switch, procedure return
jump and link jal 10000 $31 = PC + 4; go to 10000