ASIC Physical Design

CMOS Processes
Smith Text: Chapters 2 & 3
Physical design process overview
 CMOS transistor structure and fabrication steps
 Standard cell layouts
 Creation, verification & characterization of a standard-cell
based logic circuit block
 Creation of a chip from circuit blocks
IC/ASIC Design Flow
Behavioral Verify
Design Function

DFT/BIST Gate-Level Verify

& ATPG Netlist Function

Transistor-Level Verify Function

Netlist & Timing

DRC & LVS Physical Verify

Verification Layout Timing

Mask Data
ASIC Design Flow
Cell-Based IC
Cell-Based Block
Basic standard
Cell layout

Source: Weste “CMOS VLSI Design”

N-channel MOS transistor

drain

gate bulk
+ + + +
VGS L
VGS so urce VDS
W VDS

gate T ox

n-type n-type bulk

so urce electrons drain
GND or
depletion VSS
Ex region
p-type mob ile ch annel charge fixed depletion charge

02.03
CMOS Inverter Cross-Section

Source: Weste “CMOS VLSI Design”

Inverter cross-section with well and
substrate contacts

Source: Weste “CMOS VLSI Design”

IC fabrication process
2 4
1 hour
3 5
1 fu rn ace sp in
wa fer resist

grow crystal sa w grow oxid e

etch
resist As +
oxid e
mask

6 7 8 9 10 11 12

4. Grow oxide SiO2 8. Etch exposed oxide

5. Apply photoresist 9-10. Implant ions in exposed substrate
6. UV light exposes resist 11. Strip resist
7. Remove exposed resist 12. Etch oxide
 P-substrate
CMOS
SiO2 layer
Process
steps Photoresist

Expose and etch

Etch SiO2

Remove photoresist

Implant n-well

Remove SiO2
Source: Weste “CMOS VLSI Design”
 Deposit poly
CMOS
Process Etch
steps
Deposit SiO2

Etch

Diffusion

Remove SiO2

Source: Weste “CMOS VLSI Design”

CMOS Process steps

Source: Weste “CMOS VLSI Design”

CMOS n-well process transistor

Source: Weste “CMOS VLSI Design”

Inverter
mask set N-well

Poly

N+ diffusion

P+ diffusion

Contacts

Metal

Source: Weste “CMOS VLSI Design”

 Standard Cell Mask Set

Submit mask
info to fab.

Source: Smith, Figure 2.7

MOSIS fab processes
(http://www.mosis.org)

ASIC Design Kit

Source: Weste “CMOS VLSI Design”

CMOS process design rules

Source: Smith, Figure 2.11

MOSIS
Design
Rules

Smith text:
Tables 2.7-2.9
MOSIS
Design
Rules

Smith text:
Tables 2.7-2.9
MOSIS
Design
Rules
MOSIS Design Rules