Analysis of Overlap in Power Electronic Drives

in Marine Networks
Senananda P Abhayasinghe and Richard R W G Bucknall
Naval Architecture and Marine Engineering Section
Department of Mechanical Engineering
University College London
E-mail: s.abhayasinghe@ucl.ac.uk, E-mail: r_bucknall@meng.ucl.ac.uk

Abstract- Isolated power networks such as those used in ships,

submarines, offshore drilling rigs, oil production platforms etc.
have different source impedance characteristics compared to
shore based grid supplies meaning waveform quality is
significantly degraded when power electronic systems are used,
for example there is a noticeable increase in notching caused by
overlap due to the use of SCRs. This paper examines notching
and resulting non-characteristic distortion in marine power
systems using analytical method and by simulation using PS-
CAD software. The effect of notching at different locations in a
ship’s power network changes with source inductance and
examples are given which allow ‘simulated results’ and
‘theoretical results’ to be compared. Calculated values and
simulation results of notch width with changes in firing delay
angles are presented and discussed in some detail for typical
marine drive units. Existing methods of reducing the notch area
is discussed using simulation results.
Index Terms: Commutation Notch, Electric Propulsion,
Inductance, Harmonics, Overlap, VSD, Voltage Distortion.
I. BACKGROUND
The traditional choice of a diesel engine or gas/steam
turbine as a mechanical propulsion system imposes some
restrictions when designing a ship as compared with one
having a ‘tailored’ Electric Propulsion (EP) system [1]. A
tailored EP system gives more options in layout e.g.
allocating cargo or passenger space, and in designing the type
of vessel or installation. An EP system is basically made up
of generators, power network and variable speed drives
(VSD) that control the speed of electric propulsion motors.
This arrangement offers flexibility in ship design, layout and
operation such as prime-movers and generators can be located
off the shaft line whilst the electric propulsion motors and the
VSDs can be located further aft in a ship. Podded motors
located outside the hull offer even greater flexibility.
EP systems also offer better maneuverability, reduced noise
and vibration, superior dynamic performance and can be used
in an Integrated Full Electric Propulsion System (IFEP)
arrangement that allows flexibility in operation including
using minimum number of electric generators on-line for
given operational scenarios [1, 2]. An IFEP system is easily
controlled and is able to respond immediately to dynamic and
unusual disturbances e.g. change in loading condition at the
propeller or part-system failure. Fig.1 shows how EP system
can achieve propulsion redundancy in which two electric
motors are driving a single propeller or two propellers. If one
section of the bus bar fails then the remaining section of the
bus bar can maintain propulsion since the Power Management
Fig.1 Electric propulsion configuration showing split bus bar and redundancy
II. INTRODUCTION
There are numerous ways of achieving variable speeds but
Pulse Width Modulation (PWM) approach is widely used in
the marine industry. Fig.2 illustrates a basic PWM
arrangement. The AC generated power is converted to DC
voltage by the converter and then the DC is inverted back to
AC by the inverter which produces a variable voltage and
variable frequency to drive the motor at variable speed. The
motor power is controlled by the inverter to maintain the
speed of a ship set by the navigator.
The PWM does not produce or draw sinusoidal waveforms
rather they are pseudo-AC waveforms that contain harmonics
and notching as shown in Fig.5. Such non-sinusoidal
waveforms can cause instability in the power network [3,4].
The steepness (dv/dt) and width of notches especially in
conventional thyristor converters such as Load Commutated
Inverter (LCI) may give rise to instability and mal-operation
in the power network such as harmonic resonance, control
system failure, instrumentation misreadings, light flicker, etc.
Such distortion can even cause malfunction of protective
devices in a power network leading to blackout situations.
This paper examines the aspect of notching which is
apparent on VSDs using diodes and thyristors because such
devices are not perfect switches and because the circuits
contain inductance.
AC SOURCE SOLID STATE SOLID STATE
CONVERTER INVERTER ELECTRIC
MOTOR
DC BUS
CAPACITOR BANK

System (PMS) is able to limit electrical power to consumers

to prevent overloading the power network [1, 2]. Fig.2 Drive System - converter, inverter and electric motor arrangement
 III. THEORY
Diodes D1, D3 and D5 of the six pulse diode bridge shown
in Fig.3 operate in turn with D4, D6 and D2 to produce a DC
waveform from a three-phase AC supply. Fig.4 shows the
output DC voltage (VL) and input phase voltage waveforms
(Va, Vb and Vc) of 6 pulse bridge when fed from an ideal and
balanced source. As can be seen in Fig.4, diode D1 begins to
conduct at 30° through D6 because phase voltage Va is more
positive than the other two phases during the period from 30°
to 150° and Vb is more negative than the remaining phases
for the period from 0° to 90°. Conduction changes from D6 to
D2 when Vc becomes the most negative phase at 90°. Diode
D3 takes over the conduction from D1 at 150° when Vb
becomes the most positive phase while maintaining the return Fig.5 A diagram showing line voltage waveforms, current transfer
path through D2. The remaining diodes (D3,D4; D5,D4; between switching devices during overlap and notch width (µ) [10]
D5,D6) will follow a similar pattern of conduction during the
remaining period of the cycle and the sequence is then A circulating current of “i” is assumed to be flowing from
repeated for every cycle. It can be seen that transfer of incoming diode D1 through outgoing diode D5 (Fig.3) in a
conduction occurs at every 60 degrees 6 times during one closed path during overlap (Fig.4 and Fig.6 at 30 degrees).
cycle producing 6 ripples of DC voltage waveform at the When source inductance of L, input phase voltage(RMS) of V
output of the converter. The arrangement is therefore termed and instantaneous input phase voltages of Va, Vb and Vc are
6 pulse bridge. The transfer of current flow from one considered in Fig.3 the voltage difference between Va and
switching device to another is termed commutation [4]. Vc during overlap at 30° (using Fig.6) can be written as;
In reality, commutation will not occur immediately because
the source inductance causes delay in switching off the Va-Vc = Ldi/dt – (- Ldi/dt )
already conducting diode. This will result in both diodes Since Va-Vc is the line voltage √3VMAXSinωt.
(incoming and outgoing) conducting simultaneously. Hence, √3VMAXSinωt = 2 Ldi/dt
during the overlap period, it may be considered that a di = [(√3.VMAX )/2L] x Sinωt.dt (1)
momentary ‘short-circuit’ occurs when current flow changes
from one diode to the other. Overlap starts when incoming By integrating equation (1) circulation current “i” can be
switching device starts conducting and is complete when expressed as;
incoming switching device reaches the load current level. The “i” = [(√3.VMAX )/2L] x [-(Cosωt )/ω] + C (2)
period of overlap depends on the inductive reactance of the
system and the load current. The time taken for the At t= 0, “i” = 0, => C = (√3.VMAX )/2ωL
completion of current transfer from one diode to another is Applying the value of C in equation (2);
called overlap period or commutation angle (µ) as can be seen “i” = [(√3.VMAX )/2ωL][1- Cosωt] (3)
from Fig.5 [4].
IL Overlap completes when i = Load Current (IL),
ωt = commutating angle (µ), ωL = inductive reactance (XL)
Ia

Ib

Ic

A
1
La
2
D1 D3 D5 Applying them in equation (3);
B Lb IL = [(√3.VMAX )/2XL] x [1-Cosµ]
LOAD

1 2

C Lc Therefore, µ = Cos-1[1-2ILXL/√3.VMAX] (4)

1 2

D4 D6 D2
Hence source inductance influences µ [4].

Fig.3 6 Pulse diode bridge with source inductance L, input phase

voltage (RMS) of V and phase voltage waveforms Va, Vb and Vc
Vc Va

= Va-Vc

30 ° Time t

Fig.6 Overlap of phase voltage waveforms Vc and Va at 30 degrees, current

Fig.4 Waveforms (50Hz) of 6 pulse bridge fed from an ideal source, transfer from D5 to D1
showing conduction pattern of diodes
 A. Thyristor Bridge
If diodes in Fig.3 are replaced with thyristors such as in Assuming that µ is small, the commutation notch depth (D)
the Type 45 Frigate PWM drive and fed from an ideal source, can be written as an approximation in equation (6) below [6].
voltage and current waveforms can be seen in Fig.7. Trigger D = √2 VLL Sin α (6)
pulses are required to be so arranged that a pair of thyristors If line voltage is VLL then VL can be given by
(one in the positive and the other in the relevant negative VL = 1.35VLL Cos α (7)
side) is triggered simultaneously so that the return current
through the load back to the source is not blocked. This is Load current (I L) for a pure resistive load can be given by
actually needed only at the start of operation in order to VL/R where R is the load resistance [7].
commence the current flow. Once the conduction is started, It is also important to study the behavior of the depth of
firing only one thyristor at a time is sufficient because the commutation notch at various points of a power network.
corresponding thyristor in the opposite leg remains Fig.9 illustrates a transformer or reactor coupling arrangement
conducting. of a converter fed from a power network with source
The DC output voltage of the thyristor bridge (VL) can be inductance of LS, line inductance of L1 and transformer or
controlled by varying the firing angle α. The highest mean reactor inductance of L2. The total system inductance (LS+
value of the load voltage is achieved when the firing angle is L1+L2) and firing angle decide the notch width as per
zero degrees and the load voltage reaches its zero mean value equation (5) while highest notch depth at the converter input
when the firing angle is 90 degrees. If the firing angle is (point C in Fig.9) is decided by the firing angle for a given set
increased more than 90 degrees then the converter mean of circumstances as per equation (6). Notch depths at points A
output voltage will become negative and therefore and B will depend on the values of LS, L1 and L2 which can
arrangement can be made to flow power from DC load side to be given as percentages of the highest notch depth using
source. Regenerative braking into the power system can often equation (8).
be used but with obvious restrictions as to the amount of
power which can be regenerated when dissipating the kinetic Notch depth (d) at point B = D x (LS+L1) / (LS+L1+L2) (8)
energy of the load and motor.
Fig.8 shows phase voltage waveform of a 6 pulse thyristor The notch depth at the Point of Common Coupling (PCC)
bridge fed from an inductive source with firing angle of 10 B can be reduced by increasing the reactance of the coupling
degrees. The waveform shows clear notches with two fast transformer or reactor while maintaining minimum source
changing sides during overlap. The equation (5) can be and line inductance. However notch width increases with
derived to calculate the notch width in a similar manner to the system inductance increase as per equation (5) and therefore
equation (4) derived for diode bridge [4]. the increase of reactor inductance is limited. The notch area
can be expressed as a product of the notch width and the
i.e. µ = Cos-1[Cosα – (2ILXL/√3.VMAX)] – α (5) notch depth; i.e. D.µ. or as a product of system inductance
and load current; i.e. XL . I L [6].
IV. SYSTEM MODELING AND RESULT DISCUSSION
Simulations were carried out on both diode and thyristor
bridges using PS-CAD software to observe the response of
notch width for different values of source inductance.
Simulated results show that notch width of thyristor bridge
when fired at zero degrees is identical to that of the diode
bridge under the same conditions such as system inductance
etc. This can be further demonstrated by equation (5). Hence,
in order to study the behaviour of the notch width,
simulations were carried out only on diode bridge by varying
source inductance from zero to 100 µH for a resistive load of
10 Ω. Graphs representing simulated results and analytical
VIna VInb
Phase Vltage
VInC
values of notch width in Fig.10 show linear increase with the
0.20
increase of source inductance. However analytical results are
slightly higher than simulated results. This is because of the
0.10
slightly higher load current in calculation than simulation due
to diode impedance that has not been used for calculation in
0.00
equation (4).
y (V)

-0.10

AC SOURCE
LS L1-Line2 L2-Transformer AC-DC
-0.20
1 2 1 1 2
C CONVERTER
A B
0.0200 0.0217 0.0233 0.0250 0.0267 0.0283 0.0300 0.0317 0.0333 0.0350 0.0367 0.0383 0.0400 ...
...
...

Fig.8 Inductive source phase voltage waveforms feeding a thyristor bridge, Fig.9 Converter coupling arrangement through a transformer; note
firing angle 10 degrees points A, B and C
 Notching w hen firing angle of 10 Degrees
NOTCH WIDTH VS INDUCTANCE Va Vb Vc
350 300

300 200

Analytical
250 100

Phase Voltage (V)

200
Micro Sec

0
Simulated
150 -100

100 -200

50 -300
Seco... 0.0200 0.0217 0.0233 0.0250 0.0267 0.0283 0.0300 0.0317 0.0333 0.0350 0.0367 0.0383 0.0400 ...
...
...
0
0 10 20 30 40 50 60 70 80 90 100 Fig.12 Phase voltage waveforms (50Hz) showing notch at firing angle of
Micro H

Fig.10 Graphs (Analytical and Simulated) indicating increase of notch
width in µ Sec VS source inductance from zero to 100 µH.
It should be noted that notch widths of phase voltage
waveforms and that of corresponding line voltage waveform
are of same value while notch depth of the line voltage
waveform is the sum of notch depths of two phase voltage
waveforms subjected to overlap. In addition to notching in
two phase voltage waveforms involved in overlap, it was
observed in Fig.11 that the remaining phase voltage
waveform has also been distorted during overlap. As
discussed in section III, load current decreases during overlap
due to the fact that outgoing diode draws current from the
incoming diode. This decreased load current, while reducing
the voltage drop across the load, returns to the source causing
a slight distortion in the remaining phase voltage waveform
that is not subjected to overlap. However, the simulation
result in Fig.12 shows that distortion is reduced when an
inductor was introduced in the load side. This paper suggests
that discharge of the newly introduced inductor during
overlap minimizes the distortion of the remaining phase
voltage waveform.
It can also be seen in Fig.11 that there is only one fast
changing side of phase voltage waveform at the end of the
overlap period. This is because potentials of two phase
voltage waveforms are equal when overlap commences while
a potential difference exists between two phases when overlap
completes. However, there will be a potential difference
between the two phases subjected to overlap in thyristor
bridge at the start as well as at the end of overlap, resulting in
two fast changing sides as shown in Fig.12. These potential
differences vary with the firing delay angle of thyristors along
the voltage waveforms, and therefore the notch depth also
follows.
0.30
Va
10 degrees with 20 µH load inductor
Analytical studies and simulations were carried out to
further investigate the behavior of the notch width and the
depth with the increase of firing angle of the thyrister bridge.
Graphs representing both analytical and simulation results in
Fig.13 illustrate the behavior of notch width and the notch
depth at point C for a range of firing angles from zero to 80
degrees when source induction of 0.02 mH and load
resistance 10Ω have been used in the PS-CAD model.
Equations (5) and (6) were used to calculate the notch width
and notch depth respectively. The graphs indicate that the
calculated value of the notch width is slightly higher than the
simulated values. This is due to the fact that impedance of
thyristors and source has not been used in calculating load
current although these properties contribute to the simulation
result in decreasing the load current. As per equation (5),
notch width reduces with load current decrease whilst
difference in load current has no effect on notch depth as per
equation (6). The difference between calculated load current
and that obtained from simulation does not affect the notch
depth and therefore two graphs representing notch depth for
calculated and simulated values in Fig.13 are identical. It can
be seen from Fig.13 and Fig.14 that notch depth has reached
about 344 volts at firing angle of 60 degrees for a system
having peak line voltage of 400V. Fig.14 clearly shows two
large notches and four small notches of line voltage
waveform AB for one complete cycle of the fundamental
frequency. The two large notches are generated when overlap
occurs between phase voltages A and B while four small
notches are generated when either phase A or B overlaps with
phase C. Higher depth of notches such as measured above can
cause potential risk to any power network.
500
450
Vb
DIODE BRIDGE LS = 0.2 mH, RESISTIVE LOAD 5 OHMS
Vc Notch Width Analytical
W ID T H M IC R O S & D E P T H V

400

0.20
350
300
0.10
250
200 Notch Depth Analytical
Va, Vb, Vc,

0.00
& and Simulation
150

-0.10
100
50Notch Width Simulation
-0.20
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
-0.30
FIRING ANGLE IN DEGREES
TIME 0.0200 0.0217 0.0233 0.0250 0.0267 0.0283 0.0300 0.0317 0.0333 0.0350 0.0367 0.0383 0.0400 ...
...
...

Fig.11 Distorted phase voltage waveforms (50Hz) of a thyristor bridge at Fig.13 Graphs sowing the calculation and simulation results of notch
firing angle zero without load inductor µ
 Phase Vltage
VL-A
0.40
0.30
VL-AB
500
0.20
0.10
Notch at A
0.00
400

y
-0.10
-0.20
300 -0.30
-0.40
VL_B
200 0.40
L in e V o lt a g e in V

0.30

100 0.20
0.10
0.00
Notch at B
0

y
-0.10
-0.20
-100 -0.30
-0.40
-200 0.40
VL-C

-300
0.30
0.20
Notch at C
0.10
-400 0.00

y
-0.10
-0.20
-500 -0.30

Fig.14 Notches in line voltage waveform of a thyristor bridge at α=60°

-0.40
0.020 0.030 0.040 0.050 0.060 ...
...
...

Fig.15 Notch at points A, B and C of Fig.9 at firing angle 15 degrees

Fig.15 illustrates notch levels at points A, B and C of the

diagram in Fig.9 when firing angle of 15 degrees with source,
line and reactor inductance of 0.5mH each are used.
Calculation as well as simulation results show that the notch
depth at points C, B and A are 102V, 68V and 34V
respectively. The notch width at all points A, B and C are
identical as the notch width is decided by the total system
inductance as per equation (5). The notch depth at PCC (B) is
two third of the highest value at upstream (C) of the
converter. Notch depth at PCC can be reduced by increasing
the reactor inductance but this would be limited by the notch
width which is decided by the total system inductance.
A sudden change in the voltage waveform due to notching
can cause charge or discharge or ‘ringing’ (voltage
oscillations) of resistor-capacitor circuits in a power network
and this interchange of energy can cause overheating resistors
and even failure of capacitors etc [8]. Overheated resistors
may dissipate energy causing operational issues such as
requirement for additional cooling and reduced efficiency etc.
Commutation notches produced by thyristor converters will
move along the voltage waveform when firing angle changes
[2]. Deep line notching can also lead to thyristor misfiring
when notch width exceeds the duration of the gate pulse and
multiple crossovers [8]. Failure of VSDs can occur when they
are running at different speeds and are fed from the same
network, such as in offshore installations etc. These failures
can even become more critical when thristor bridge converter-
inverter fed motors run at low speeds since notch depth
becomes excessive as firing delay increases. Fig.14 is an
example of excessive notch depth. Notches generated by
converters reside at different locations of voltage waveforms
depending on the thyristor firing angle. These commutation
notches propagate throughout the network and can cause
malfunction of other systems as described in section II.
Some of the methods used to mitigate harmonics do not
necessarily mitigate these non-characteristic distortions while
some methods such as phase shifting transformers and filter
capacitors attenuate notch to a certain extent. Due to real time
control (within one half cycle) some broadband active filters
can be used for notch reduction as they inject reactive power
into the notch. This method can treat harmonics as well as
inter-harmonics and high frequency components associated
with notches including load generated disturbances. The
arrangement is made in such a way that a current waveform
representing all the frequency components associated with
distortion is drawn from the real time control broadband filter
arrangement while the current at fundamental frequency is
drawn from the source[9].
V. CONCLUSION
Distortion in a power network caused by commutation
notches is of significant interest as it can cause instability,
malfunction of control systems and degradation of the
reliability of operation of important control and safety
systems. Effect of notch depth and notch width has been
examined at different locations of an isolated power network
for different source inductances and different firing angles.
Analytical and simulation results of notch width and notch
depth have been compared; reasons for the difference of
results have been discussed. Notch width and depth can be
reduced by decreasing the source inductance. Notch width
decreases with the increase of firing angle while notch depth
increases with firing angle; i.e. higher dv/dt. For a given
system inductance, notch width is constant at any point of the
power network while notch depth increases along the way
forward feeder. Notch depth at PCC can be reduced by
increasing the reactor inductance between PCC and converter.
VI. FUTURE WORK
A complete EP system will be modeled in PS-CAD to
study power network distortions and their associated
characteristic and non-characteristic frequency components in
detail. Existing methods of mitigating voltage distortion will
further be analyzed and research will focus on novel methods
to mitigate them.
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